HDMI_ACR_44_0    1482 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
HDMI_ACR_44_0    1524 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
HDMI_ACR_44_0    1414 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
HDMI_ACR_44_0    1406 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
HDMI_ACR_44_0      79 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_44_0, DIG, id),\
HDMI_ACR_44_0     183 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
HDMI_ACR_44_0     682 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_ACR_44_0;
HDMI_ACR_44_0    1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
HDMI_ACR_44_0      69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_44_0, DIG, id),\
HDMI_ACR_44_0     153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_ACR_44_0;
HDMI_ACR_44_0      90 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));