HDMI_ACR_32_1    1478 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
HDMI_ACR_32_1    1520 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
HDMI_ACR_32_1    1410 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
HDMI_ACR_32_1    1403 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
HDMI_ACR_32_1      78 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_32_1, DIG, id),\
HDMI_ACR_32_1     182 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
HDMI_ACR_32_1     681 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_ACR_32_1;
HDMI_ACR_32_1    1338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
HDMI_ACR_32_1      68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_32_1, DIG, id),\
HDMI_ACR_32_1     152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_ACR_32_1;
HDMI_ACR_32_1      88 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);