HDMI_ACR_32_0    1475 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
HDMI_ACR_32_0    1517 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
HDMI_ACR_32_0    1407 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
HDMI_ACR_32_0    1400 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
HDMI_ACR_32_0      77 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_32_0, DIG, id),\
HDMI_ACR_32_0     181 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
HDMI_ACR_32_0     680 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_ACR_32_0;
HDMI_ACR_32_0    1335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
HDMI_ACR_32_0      67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_32_0, DIG, id),\
HDMI_ACR_32_0     151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_ACR_32_0;
HDMI_ACR_32_0      87 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));