HDLCD_REG_INT_MASK 51 drivers/gpu/drm/arm/hdlcd_crtc.c unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); HDLCD_REG_INT_MASK 53 drivers/gpu/drm/arm/hdlcd_crtc.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); HDLCD_REG_INT_MASK 61 drivers/gpu/drm/arm/hdlcd_crtc.c unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); HDLCD_REG_INT_MASK 63 drivers/gpu/drm/arm/hdlcd_crtc.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); HDLCD_REG_INT_MASK 160 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0); HDLCD_REG_INT_MASK 168 drivers/gpu/drm/arm/hdlcd_drv.c unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); HDLCD_REG_INT_MASK 173 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask); HDLCD_REG_INT_MASK 182 drivers/gpu/drm/arm/hdlcd_drv.c unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); HDLCD_REG_INT_MASK 192 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);