HD64461_IO_OFFSET 19 arch/sh/include/asm/hd64461.h #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000) HD64461_IO_OFFSET 25 arch/sh/include/asm/hd64461.h #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000) HD64461_IO_OFFSET 30 arch/sh/include/asm/hd64461.h #define HD64461_STBCR HD64461_IO_OFFSET(0x00000000) HD64461_IO_OFFSET 47 arch/sh/include/asm/hd64461.h #define HD64461_SYSCR HD64461_IO_OFFSET(0x02) HD64461_IO_OFFSET 50 arch/sh/include/asm/hd64461.h #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04) HD64461_IO_OFFSET 53 arch/sh/include/asm/hd64461.h #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000) HD64461_IO_OFFSET 56 arch/sh/include/asm/hd64461.h #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002) HD64461_IO_OFFSET 59 arch/sh/include/asm/hd64461.h #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004) HD64461_IO_OFFSET 70 arch/sh/include/asm/hd64461.h #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010) HD64461_IO_OFFSET 75 arch/sh/include/asm/hd64461.h #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012) HD64461_IO_OFFSET 76 arch/sh/include/asm/hd64461.h #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */ HD64461_IO_OFFSET 77 arch/sh/include/asm/hd64461.h #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */ HD64461_IO_OFFSET 78 arch/sh/include/asm/hd64461.h #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */ HD64461_IO_OFFSET 79 arch/sh/include/asm/hd64461.h #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */ HD64461_IO_OFFSET 80 arch/sh/include/asm/hd64461.h #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */ HD64461_IO_OFFSET 83 arch/sh/include/asm/hd64461.h #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e) HD64461_IO_OFFSET 86 arch/sh/include/asm/hd64461.h #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */ HD64461_IO_OFFSET 87 arch/sh/include/asm/hd64461.h #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */ HD64461_IO_OFFSET 88 arch/sh/include/asm/hd64461.h #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */ HD64461_IO_OFFSET 89 arch/sh/include/asm/hd64461.h #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */ HD64461_IO_OFFSET 91 arch/sh/include/asm/hd64461.h #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */ HD64461_IO_OFFSET 92 arch/sh/include/asm/hd64461.h #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */ HD64461_IO_OFFSET 93 arch/sh/include/asm/hd64461.h #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */ HD64461_IO_OFFSET 103 arch/sh/include/asm/hd64461.h #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */ HD64461_IO_OFFSET 104 arch/sh/include/asm/hd64461.h #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */ HD64461_IO_OFFSET 105 arch/sh/include/asm/hd64461.h #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */ HD64461_IO_OFFSET 106 arch/sh/include/asm/hd64461.h #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */ HD64461_IO_OFFSET 107 arch/sh/include/asm/hd64461.h #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */ HD64461_IO_OFFSET 108 arch/sh/include/asm/hd64461.h #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */ HD64461_IO_OFFSET 109 arch/sh/include/asm/hd64461.h #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */ HD64461_IO_OFFSET 112 arch/sh/include/asm/hd64461.h #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */ HD64461_IO_OFFSET 113 arch/sh/include/asm/hd64461.h #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */ HD64461_IO_OFFSET 114 arch/sh/include/asm/hd64461.h #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */ HD64461_IO_OFFSET 115 arch/sh/include/asm/hd64461.h #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */ HD64461_IO_OFFSET 116 arch/sh/include/asm/hd64461.h #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */ HD64461_IO_OFFSET 117 arch/sh/include/asm/hd64461.h #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */ HD64461_IO_OFFSET 118 arch/sh/include/asm/hd64461.h #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */ HD64461_IO_OFFSET 119 arch/sh/include/asm/hd64461.h #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */ HD64461_IO_OFFSET 120 arch/sh/include/asm/hd64461.h #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */ HD64461_IO_OFFSET 121 arch/sh/include/asm/hd64461.h #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */ HD64461_IO_OFFSET 122 arch/sh/include/asm/hd64461.h #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */ HD64461_IO_OFFSET 123 arch/sh/include/asm/hd64461.h #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */ HD64461_IO_OFFSET 127 arch/sh/include/asm/hd64461.h #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */ HD64461_IO_OFFSET 128 arch/sh/include/asm/hd64461.h #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */ HD64461_IO_OFFSET 129 arch/sh/include/asm/hd64461.h #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */ HD64461_IO_OFFSET 130 arch/sh/include/asm/hd64461.h #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */ HD64461_IO_OFFSET 131 arch/sh/include/asm/hd64461.h #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */ HD64461_IO_OFFSET 133 arch/sh/include/asm/hd64461.h #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */ HD64461_IO_OFFSET 134 arch/sh/include/asm/hd64461.h #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */ HD64461_IO_OFFSET 135 arch/sh/include/asm/hd64461.h #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */ HD64461_IO_OFFSET 136 arch/sh/include/asm/hd64461.h #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */ HD64461_IO_OFFSET 137 arch/sh/include/asm/hd64461.h #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */ HD64461_IO_OFFSET 195 arch/sh/include/asm/hd64461.h #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a) HD64461_IO_OFFSET 198 arch/sh/include/asm/hd64461.h #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c) HD64461_IO_OFFSET 201 arch/sh/include/asm/hd64461.h #define HD64461_PGCR HD64461_IO_OFFSET(0x202e) HD64461_IO_OFFSET 204 arch/sh/include/asm/hd64461.h #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */ HD64461_IO_OFFSET 205 arch/sh/include/asm/hd64461.h #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */ HD64461_IO_OFFSET 206 arch/sh/include/asm/hd64461.h #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */ HD64461_IO_OFFSET 207 arch/sh/include/asm/hd64461.h #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */ HD64461_IO_OFFSET 210 arch/sh/include/asm/hd64461.h #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */ HD64461_IO_OFFSET 211 arch/sh/include/asm/hd64461.h #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */ HD64461_IO_OFFSET 212 arch/sh/include/asm/hd64461.h #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */ HD64461_IO_OFFSET 213 arch/sh/include/asm/hd64461.h #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */ HD64461_IO_OFFSET 216 arch/sh/include/asm/hd64461.h #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */ HD64461_IO_OFFSET 217 arch/sh/include/asm/hd64461.h #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */ HD64461_IO_OFFSET 218 arch/sh/include/asm/hd64461.h #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */ HD64461_IO_OFFSET 219 arch/sh/include/asm/hd64461.h #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */ HD64461_IO_OFFSET 222 arch/sh/include/asm/hd64461.h #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */ HD64461_IO_OFFSET 223 arch/sh/include/asm/hd64461.h #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */ HD64461_IO_OFFSET 224 arch/sh/include/asm/hd64461.h #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */ HD64461_IO_OFFSET 225 arch/sh/include/asm/hd64461.h #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */ HD64461_IO_OFFSET 228 arch/sh/include/asm/hd64461.h #define HD64461_NIRR HD64461_IO_OFFSET(0x5000) HD64461_IO_OFFSET 229 arch/sh/include/asm/hd64461.h #define HD64461_NIMR HD64461_IO_OFFSET(0x5002) HD64461_IO_OFFSET 336 drivers/video/fbdev/hitfb.c hitfb_fix.mmio_start = HD64461_IO_OFFSET(0x1000); HD64461_IO_OFFSET 338 drivers/video/fbdev/hitfb.c hitfb_fix.smem_start = HD64461_IO_OFFSET(0x02000000);