HALT 42 arch/arm/mach-clps711x/board-dt.c DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128); HALT 395 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); HALT 397 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); HALT 972 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); HALT 979 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); HALT 630 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); HALT 632 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); HALT 952 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); HALT 1324 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); HALT 608 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); HALT 738 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);