HALF_SLICE_CHICKEN3  255 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
HALF_SLICE_CHICKEN3  340 drivers/gpu/drm/i915/gt/intel_workarounds.c 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
HALF_SLICE_CHICKEN3  498 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
HALF_SLICE_CHICKEN3 1946 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
HALF_SLICE_CHICKEN3  108 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
HALF_SLICE_CHICKEN3 9387 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(HALF_SLICE_CHICKEN3,