HALF_SLICE_CHICKEN2 344 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); HALF_SLICE_CHICKEN2 2845 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); HALF_SLICE_CHICKEN2 107 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ HALF_SLICE_CHICKEN2 3158 drivers/gpu/drm/i915/i915_perf.c return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) || HALF_SLICE_CHICKEN2 3204 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)