AM35XX_CONTROL_IP_SW_RESET 61 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 64 arch/arm/mach-omap2/omap_phy_internal.c omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 67 arch/arm/mach-omap2/omap_phy_internal.c omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 69 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 230 arch/arm/mach-omap2/pdata-quirks.c v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 232 arch/arm/mach-omap2/pdata-quirks.c omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); AM35XX_CONTROL_IP_SW_RESET 233 arch/arm/mach-omap2/pdata-quirks.c omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */