GT_WRITE           29 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
GT_WRITE           30 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
GT_WRITE           46 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC0_OFS, delta);
GT_WRITE           47 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
GT_WRITE           62 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
GT_WRITE           77 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
GT_WRITE           91 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
GT_WRITE          136 arch/mips/kernel/cevt-gt641xx.c 	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
GT_WRITE           27 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRCAUSE_OFS, cause);
GT_WRITE           39 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRMASK_OFS, mask);
GT_WRITE           51 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRMASK_OFS, mask);
GT_WRITE           55 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRCAUSE_OFS, cause);
GT_WRITE           67 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRMASK_OFS, mask);
GT_WRITE          107 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRMASK_OFS, 0);
GT_WRITE          108 arch/mips/kernel/irq-gt641xx.c 	GT_WRITE(GT_INTRCAUSE_OFS, 0);
GT_WRITE          182 arch/mips/mti-malta/malta-init.c 		GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
GT_WRITE          185 arch/mips/mti-malta/malta-init.c 		GT_WRITE(GT_PCI0_CMD_OFS, 0);
GT_WRITE          192 arch/mips/mti-malta/malta-init.c 			GT_WRITE(GT_PCI0IOREMAP_OFS, map);
GT_WRITE          108 arch/mips/pci/fixup-cobalt.c 		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
GT_WRITE          116 arch/mips/pci/fixup-cobalt.c 		GT_WRITE(GT_PCI0_TOR_OFS,
GT_WRITE          122 arch/mips/pci/fixup-cobalt.c 		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
GT_WRITE           40 arch/mips/pci/ops-gt64xxx_pci0.c 	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_WRITE           44 arch/mips/pci/ops-gt64xxx_pci0.c 	GT_WRITE(GT_PCI0_CFGADDR_OFS,
GT_WRITE           56 arch/mips/pci/ops-gt64xxx_pci0.c 			GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
GT_WRITE           77 arch/mips/pci/ops-gt64xxx_pci0.c 		GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_WRITE           92 arch/mips/pci/pci-malta.c 		GT_WRITE(GT_PCI0_CFGADDR_OFS,
GT_WRITE          100 arch/mips/pci/pci-malta.c 		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));