GT_RENDER_USER_INTERRUPT   29 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	if (iir & GT_RENDER_USER_INTERRUPT) {
GT_RENDER_USER_INTERRUPT  212 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
GT_RENDER_USER_INTERRUPT  246 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
GT_RENDER_USER_INTERRUPT  272 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	if (gt_iir & GT_RENDER_USER_INTERRUPT)
GT_RENDER_USER_INTERRUPT  360 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		(GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT  362 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT  365 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		(GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT  367 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT  372 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT  434 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	gt_irqs |= GT_RENDER_USER_INTERRUPT;
GT_RENDER_USER_INTERRUPT 3075 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
GT_RENDER_USER_INTERRUPT 2237 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
GT_RENDER_USER_INTERRUPT 1021 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT 1022 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	       GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;