AM33XX_CM_REGADDR 44 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) AM33XX_CM_REGADDR 46 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) AM33XX_CM_REGADDR 48 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) AM33XX_CM_REGADDR 50 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) AM33XX_CM_REGADDR 52 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) AM33XX_CM_REGADDR 54 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) AM33XX_CM_REGADDR 56 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) AM33XX_CM_REGADDR 58 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) AM33XX_CM_REGADDR 60 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) AM33XX_CM_REGADDR 62 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) AM33XX_CM_REGADDR 64 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) AM33XX_CM_REGADDR 66 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) AM33XX_CM_REGADDR 68 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) AM33XX_CM_REGADDR 70 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) AM33XX_CM_REGADDR 72 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) AM33XX_CM_REGADDR 74 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) AM33XX_CM_REGADDR 76 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) AM33XX_CM_REGADDR 78 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) AM33XX_CM_REGADDR 80 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) AM33XX_CM_REGADDR 82 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) AM33XX_CM_REGADDR 84 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) AM33XX_CM_REGADDR 86 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) AM33XX_CM_REGADDR 88 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) AM33XX_CM_REGADDR 90 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) AM33XX_CM_REGADDR 92 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) AM33XX_CM_REGADDR 94 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) AM33XX_CM_REGADDR 96 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) AM33XX_CM_REGADDR 98 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) AM33XX_CM_REGADDR 100 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) AM33XX_CM_REGADDR 102 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) AM33XX_CM_REGADDR 104 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) AM33XX_CM_REGADDR 106 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) AM33XX_CM_REGADDR 108 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) AM33XX_CM_REGADDR 110 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) AM33XX_CM_REGADDR 112 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) AM33XX_CM_REGADDR 114 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) AM33XX_CM_REGADDR 116 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) AM33XX_CM_REGADDR 118 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) AM33XX_CM_REGADDR 120 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) AM33XX_CM_REGADDR 122 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) AM33XX_CM_REGADDR 124 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) AM33XX_CM_REGADDR 126 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) AM33XX_CM_REGADDR 128 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) AM33XX_CM_REGADDR 130 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) AM33XX_CM_REGADDR 132 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) AM33XX_CM_REGADDR 134 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) AM33XX_CM_REGADDR 136 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) AM33XX_CM_REGADDR 138 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) AM33XX_CM_REGADDR 140 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) AM33XX_CM_REGADDR 142 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) AM33XX_CM_REGADDR 144 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) AM33XX_CM_REGADDR 146 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) AM33XX_CM_REGADDR 148 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) AM33XX_CM_REGADDR 150 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) AM33XX_CM_REGADDR 152 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) AM33XX_CM_REGADDR 154 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) AM33XX_CM_REGADDR 156 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) AM33XX_CM_REGADDR 158 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) AM33XX_CM_REGADDR 160 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) AM33XX_CM_REGADDR 162 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) AM33XX_CM_REGADDR 164 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) AM33XX_CM_REGADDR 166 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) AM33XX_CM_REGADDR 168 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) AM33XX_CM_REGADDR 170 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) AM33XX_CM_REGADDR 172 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) AM33XX_CM_REGADDR 174 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) AM33XX_CM_REGADDR 176 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) AM33XX_CM_REGADDR 178 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) AM33XX_CM_REGADDR 180 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) AM33XX_CM_REGADDR 182 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) AM33XX_CM_REGADDR 184 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) AM33XX_CM_REGADDR 186 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) AM33XX_CM_REGADDR 188 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) AM33XX_CM_REGADDR 190 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) AM33XX_CM_REGADDR 192 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) AM33XX_CM_REGADDR 194 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) AM33XX_CM_REGADDR 196 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) AM33XX_CM_REGADDR 200 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) AM33XX_CM_REGADDR 202 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) AM33XX_CM_REGADDR 204 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) AM33XX_CM_REGADDR 206 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) AM33XX_CM_REGADDR 208 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) AM33XX_CM_REGADDR 210 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) AM33XX_CM_REGADDR 212 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) AM33XX_CM_REGADDR 214 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) AM33XX_CM_REGADDR 216 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) AM33XX_CM_REGADDR 218 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) AM33XX_CM_REGADDR 220 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) AM33XX_CM_REGADDR 222 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) AM33XX_CM_REGADDR 224 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) AM33XX_CM_REGADDR 226 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) AM33XX_CM_REGADDR 228 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) AM33XX_CM_REGADDR 230 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) AM33XX_CM_REGADDR 232 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) AM33XX_CM_REGADDR 234 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) AM33XX_CM_REGADDR 236 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) AM33XX_CM_REGADDR 238 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) AM33XX_CM_REGADDR 240 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) AM33XX_CM_REGADDR 242 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) AM33XX_CM_REGADDR 244 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) AM33XX_CM_REGADDR 246 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) AM33XX_CM_REGADDR 248 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) AM33XX_CM_REGADDR 250 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) AM33XX_CM_REGADDR 252 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) AM33XX_CM_REGADDR 254 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) AM33XX_CM_REGADDR 256 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) AM33XX_CM_REGADDR 258 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) AM33XX_CM_REGADDR 260 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) AM33XX_CM_REGADDR 262 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) AM33XX_CM_REGADDR 264 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) AM33XX_CM_REGADDR 266 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) AM33XX_CM_REGADDR 268 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) AM33XX_CM_REGADDR 270 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) AM33XX_CM_REGADDR 272 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) AM33XX_CM_REGADDR 274 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) AM33XX_CM_REGADDR 276 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) AM33XX_CM_REGADDR 278 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) AM33XX_CM_REGADDR 280 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) AM33XX_CM_REGADDR 282 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) AM33XX_CM_REGADDR 284 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) AM33XX_CM_REGADDR 286 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) AM33XX_CM_REGADDR 288 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) AM33XX_CM_REGADDR 290 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) AM33XX_CM_REGADDR 292 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) AM33XX_CM_REGADDR 294 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) AM33XX_CM_REGADDR 296 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) AM33XX_CM_REGADDR 298 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) AM33XX_CM_REGADDR 300 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) AM33XX_CM_REGADDR 302 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) AM33XX_CM_REGADDR 304 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) AM33XX_CM_REGADDR 306 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) AM33XX_CM_REGADDR 308 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) AM33XX_CM_REGADDR 312 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) AM33XX_CM_REGADDR 314 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) AM33XX_CM_REGADDR 316 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) AM33XX_CM_REGADDR 318 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) AM33XX_CM_REGADDR 320 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) AM33XX_CM_REGADDR 322 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) AM33XX_CM_REGADDR 324 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) AM33XX_CM_REGADDR 326 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) AM33XX_CM_REGADDR 328 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) AM33XX_CM_REGADDR 330 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) AM33XX_CM_REGADDR 332 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) AM33XX_CM_REGADDR 334 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) AM33XX_CM_REGADDR 336 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) AM33XX_CM_REGADDR 338 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) AM33XX_CM_REGADDR 342 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) AM33XX_CM_REGADDR 344 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) AM33XX_CM_REGADDR 348 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) AM33XX_CM_REGADDR 352 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) AM33XX_CM_REGADDR 354 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) AM33XX_CM_REGADDR 358 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) AM33XX_CM_REGADDR 360 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) AM33XX_CM_REGADDR 362 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) AM33XX_CM_REGADDR 364 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) AM33XX_CM_REGADDR 366 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) AM33XX_CM_REGADDR 368 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) AM33XX_CM_REGADDR 372 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) AM33XX_CM_REGADDR 374 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)