AM33XX_CM_DPLL_MOD 312 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) AM33XX_CM_DPLL_MOD 314 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) AM33XX_CM_DPLL_MOD 316 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) AM33XX_CM_DPLL_MOD 318 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) AM33XX_CM_DPLL_MOD 320 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) AM33XX_CM_DPLL_MOD 322 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) AM33XX_CM_DPLL_MOD 324 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) AM33XX_CM_DPLL_MOD 326 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) AM33XX_CM_DPLL_MOD 328 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) AM33XX_CM_DPLL_MOD 330 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) AM33XX_CM_DPLL_MOD 332 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) AM33XX_CM_DPLL_MOD 334 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) AM33XX_CM_DPLL_MOD 336 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) AM33XX_CM_DPLL_MOD 338 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)