GRPH_INT_CONTROL 6908 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 6909 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 6912 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 6913 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 6916 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 6917 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
GRPH_INT_CONTROL 7260 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
GRPH_INT_CONTROL 7262 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
GRPH_INT_CONTROL 7266 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
GRPH_INT_CONTROL 7268 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
GRPH_INT_CONTROL 7272 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
GRPH_INT_CONTROL 7274 drivers/gpu/drm/radeon/cik.c 		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
GRPH_INT_CONTROL 4479 drivers/gpu/drm/radeon/evergreen.c 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
GRPH_INT_CONTROL 4584 drivers/gpu/drm/radeon/evergreen.c 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
GRPH_INT_CONTROL 5967 drivers/gpu/drm/radeon/si.c 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
GRPH_INT_CONTROL 6125 drivers/gpu/drm/radeon/si.c 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);