GPCR 374 arch/arm/mach-pxa/mfp-pxa2xx.c GPCR(i * 32) = ~PGSR(i); GPCR 398 arch/arm/mach-pxa/mfp-pxa2xx.c GPCR(i * 32) = ~saved_gplr[i]; GPCR 129 arch/arm/mach-sa1100/assabet.c GPCR = SDA; GPCR 145 arch/arm/mach-sa1100/assabet.c GPCR = SCK; GPCR 150 arch/arm/mach-sa1100/assabet.c GPCR = SDA; GPCR 155 arch/arm/mach-sa1100/assabet.c GPCR = SCK; GPCR 165 arch/arm/mach-sa1100/assabet.c GPCR = SCK | SDA; GPCR 179 arch/arm/mach-sa1100/assabet.c GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ GPCR 194 arch/arm/mach-sa1100/assabet.c GPCR = (~gplr) & (SDA | SCK | MOD); GPCR 559 arch/arm/mach-sa1100/assabet.c GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; GPCR 567 arch/arm/mach-sa1100/assabet.c GPCR = GPIO_GPIO27; GPCR 178 arch/arm/mach-sa1100/badge4.c GPCR = (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 | GPCR 193 arch/arm/mach-sa1100/badge4.c GPCR = (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL); GPCR 197 arch/arm/mach-sa1100/badge4.c GPCR = (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2); GPCR 201 arch/arm/mach-sa1100/badge4.c GPCR = BADGE4_GPIO_MUXSEL0; GPCR 206 arch/arm/mach-sa1100/badge4.c GPCR = BADGE4_GPIO_TESTPT_J7; GPCR 210 arch/arm/mach-sa1100/badge4.c GPCR = BADGE4_GPIO_PCMEN5V; /* initially off */ GPCR 283 arch/arm/mach-sa1100/badge4.c GPCR = BADGE4_GPIO_PCMEN5V; GPCR 440 arch/arm/mach-sa1100/generic.c GPCR = GPIO_MBGNT; GPCR 459 arch/arm/mach-sa1100/generic.c GPCR = GPIO_MBGNT; GPCR 285 arch/arm/mach-sa1100/h3xxx.c GPCR = 0x0fffffff; /* All outputs are set low by default */ GPCR 269 arch/arm/mach-sa1100/jornada720.c GPCR = GPIO_GPIO20; /* stop gpio20 */ GPCR 112 arch/arm/mach-sa1100/jornada720_ssp.c GPCR = GPIO_GPIO25; GPCR 133 arch/arm/mach-sa1100/pleb.c GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */ GPCR 107 arch/arm/mach-sa1100/pm.c GPCR = ~gpio; GPCR 135 arch/arm/mach-sa1100/shannon.c GPCR = SHANNON_GPIO_CODEC_RESET; GPCR 115 drivers/gpio/gpio-intel-mid.c gpcr = gpio_reg(chip, offset, GPCR); GPCR 115 drivers/gpio/gpio-merrifield.c gpcr = gpio_reg(chip, offset, GPCR);