GMBUS_REG_READ    109 drivers/gpu/drm/gma500/intel_gmbus.c 	reserved = GMBUS_REG_READ(gpio->reg) &
GMBUS_REG_READ    123 drivers/gpu/drm/gma500/intel_gmbus.c 	return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
GMBUS_REG_READ    133 drivers/gpu/drm/gma500/intel_gmbus.c 	return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
GMBUS_REG_READ    150 drivers/gpu/drm/gma500/intel_gmbus.c 	GMBUS_REG_READ(gpio->reg); /* Posting */
GMBUS_REG_READ    167 drivers/gpu/drm/gma500/intel_gmbus.c 	GMBUS_REG_READ(gpio->reg);
GMBUS_REG_READ    275 drivers/gpu/drm/gma500/intel_gmbus.c 			GMBUS_REG_READ(GMBUS2+reg_offset);
GMBUS_REG_READ    279 drivers/gpu/drm/gma500/intel_gmbus.c 				if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
GMBUS_REG_READ    282 drivers/gpu/drm/gma500/intel_gmbus.c 				if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
GMBUS_REG_READ    285 drivers/gpu/drm/gma500/intel_gmbus.c 				val = GMBUS_REG_READ(GMBUS3 + reg_offset);
GMBUS_REG_READ    305 drivers/gpu/drm/gma500/intel_gmbus.c 			GMBUS_REG_READ(GMBUS2+reg_offset);
GMBUS_REG_READ    308 drivers/gpu/drm/gma500/intel_gmbus.c 				if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
GMBUS_REG_READ    311 drivers/gpu/drm/gma500/intel_gmbus.c 				if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
GMBUS_REG_READ    321 drivers/gpu/drm/gma500/intel_gmbus.c 				GMBUS_REG_READ(GMBUS2+reg_offset);
GMBUS_REG_READ    325 drivers/gpu/drm/gma500/intel_gmbus.c 		if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
GMBUS_REG_READ    327 drivers/gpu/drm/gma500/intel_gmbus.c 		if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)