GMBUS2 275 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); GMBUS2 279 drivers/gpu/drm/gma500/intel_gmbus.c if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS2 282 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) GMBUS2 305 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); GMBUS2 308 drivers/gpu/drm/gma500/intel_gmbus.c if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS2 311 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS2 321 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(GMBUS2+reg_offset); GMBUS2 325 drivers/gpu/drm/gma500/intel_gmbus.c if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) GMBUS2 327 drivers/gpu/drm/gma500/intel_gmbus.c if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) GMBUS2 343 drivers/gpu/drm/i915/display/intel_gmbus.c ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); GMBUS2 345 drivers/gpu/drm/i915/display/intel_gmbus.c ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); GMBUS2 372 drivers/gpu/drm/i915/display/intel_gmbus.c GMBUS2, GMBUS_ACTIVE, 0,