GIC_DIST_ENABLE_SET 97 arch/arm/mach-ux500/pm.c er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); GIC_DIST_ENABLE_SET 150 arch/arm/mach-ux500/pm.c GIC_DIST_ENABLE_SET + (i + 1) * 4); GIC_DIST_ENABLE_SET 156 drivers/irqchip/irq-gic-common.c writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); GIC_DIST_ENABLE_SET 224 drivers/irqchip/irq-gic.c gic_poke_irq(d, GIC_DIST_ENABLE_SET); GIC_DIST_ENABLE_SET 256 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; GIC_DIST_ENABLE_SET 280 drivers/irqchip/irq-gic.c *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); GIC_DIST_ENABLE_SET 602 drivers/irqchip/irq-gic.c readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); GIC_DIST_ENABLE_SET 649 drivers/irqchip/irq-gic.c dist_base + GIC_DIST_ENABLE_SET + i * 4); GIC_DIST_ENABLE_SET 680 drivers/irqchip/irq-gic.c ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); GIC_DIST_ENABLE_SET 712 drivers/irqchip/irq-gic.c writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); GIC_DIST_ENABLE_SET 106 drivers/irqchip/irq-hip04.c writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + GIC_DIST_ENABLE_SET 411 virt/kvm/arm/vgic/vgic-mmio-v2.c REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,