GIC_CPU_CTRL       47 arch/arm/mach-oxnas/platsmp.c 		gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
GIC_CPU_CTRL       50 arch/arm/mach-tegra/irq.c 		writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
GIC_CPU_CTRL      484 drivers/irqchip/irq-gic.c 	bypass = readl(cpu_base + GIC_CPU_CTRL);
GIC_CPU_CTRL      487 drivers/irqchip/irq-gic.c 	writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
GIC_CPU_CTRL      563 drivers/irqchip/irq-gic.c 	val = readl(cpu_base + GIC_CPU_CTRL);
GIC_CPU_CTRL      565 drivers/irqchip/irq-gic.c 	writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
GIC_CPU_CTRL      279 drivers/irqchip/irq-hip04.c 	writel_relaxed(1, base + GIC_CPU_CTRL);
GIC_CPU_CTRL      273 virt/kvm/arm/vgic/vgic-mmio-v2.c 	case GIC_CPU_CTRL:
GIC_CPU_CTRL      320 virt/kvm/arm/vgic/vgic-mmio-v2.c 	case GIC_CPU_CTRL:
GIC_CPU_CTRL      452 virt/kvm/arm/vgic/vgic-mmio-v2.c 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,