GENMASK_ULL 127 arch/arm/mm/cache-l2x0-pmu.c mask = GENMASK_ULL(31, 0); GENMASK_ULL 313 arch/arm64/include/asm/kvm_arm.h (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8) GENMASK_ULL 587 arch/arm64/include/asm/kvm_mmu.h return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); GENMASK_ULL 57 arch/arm64/include/asm/tlbflush.h __ta &= GENMASK_ULL(43, 0); \ GENMASK_ULL 1877 arch/arm64/kernel/ptrace.c (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \ GENMASK_ULL 1878 arch/arm64/kernel/ptrace.c GENMASK_ULL(20, 13) | GENMASK_ULL(11, 10) | GENMASK_ULL(5, 5)) GENMASK_ULL 1880 arch/arm64/kernel/ptrace.c (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) GENMASK_ULL 57 arch/arm64/kvm/va_layout.c va_mask = GENMASK_ULL(tag_lsb - 1, 0); GENMASK_ULL 58 arch/arm64/kvm/va_layout.c tag_val = get_random_long() & GENMASK_ULL(vabits_actual - 2, tag_lsb); GENMASK_ULL 170 arch/arm64/kvm/va_layout.c addr |= ((u64)origptr & GENMASK_ULL(10, 7)); GENMASK_ULL 179 arch/arm64/mm/init.c phys_addr_t offset = memblock_start_of_DRAM() & GENMASK_ULL(63, 32); GENMASK_ULL 132 arch/mips/include/asm/mips-cm.h #define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32) GENMASK_ULL 139 arch/mips/include/asm/mips-cm.h #define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15) GENMASK_ULL 175 arch/mips/include/asm/mips-cm.h #define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58) GENMASK_ULL 276 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48) GENMASK_ULL 277 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6) GENMASK_ULL 312 arch/x86/events/amd/iommu.c count &= GENMASK_ULL(47, 0); GENMASK_ULL 403 arch/x86/include/asm/hyperv-tlfs.h #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) GENMASK_ULL 407 arch/x86/include/asm/hyperv-tlfs.h #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) GENMASK_ULL 409 arch/x86/include/asm/hyperv-tlfs.h #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) GENMASK_ULL 43 arch/x86/include/asm/mce.h #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38) GENMASK_ULL 122 arch/x86/include/asm/vmx.h return vmx_basic & GENMASK_ULL(30, 0); GENMASK_ULL 127 arch/x86/include/asm/vmx.h return (vmx_basic & GENMASK_ULL(44, 32)) >> 32; GENMASK_ULL 137 arch/x86/include/asm/vmx.h return (vmx_misc & GENMASK_ULL(24, 16)) >> 16; GENMASK_ULL 142 arch/x86/include/asm/vmx.h return (vmx_misc & GENMASK_ULL(27, 25)) >> 25; GENMASK_ULL 147 arch/x86/include/asm/vmx.h return (vmx_misc & GENMASK_ULL(63, 32)) >> 32; GENMASK_ULL 23 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, GENMASK_ULL 39 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, GENMASK_ULL 684 arch/x86/kernel/cpu/mce/amd.c u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; GENMASK_ULL 706 arch/x86/kernel/cpu/mce/amd.c dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; GENMASK_ULL 721 arch/x86/kernel/cpu/mce/amd.c dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); GENMASK_ULL 817 arch/x86/kernel/cpu/mce/amd.c temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); GENMASK_ULL 819 arch/x86/kernel/cpu/mce/amd.c temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; GENMASK_ULL 894 arch/x86/kernel/cpu/mce/amd.c m.addr &= GENMASK_ULL(55, lsb); GENMASK_ULL 670 arch/x86/kernel/cpu/mce/core.c m->addr &= GENMASK_ULL(55, lsb); GENMASK_ULL 423 arch/x86/kvm/mmu.c #define MMIO_SPTE_GEN_MASK GENMASK_ULL(17, 0) GENMASK_ULL 427 arch/x86/kvm/mmu.c #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \ GENMASK_ULL 432 arch/x86/kvm/mmu.c #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \ GENMASK_ULL 596 arch/x86/kvm/mmu.c GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); GENMASK_ULL 1062 arch/x86/kvm/vmx/nested.c BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); GENMASK_ULL 1120 arch/x86/kvm/vmx/nested.c if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) GENMASK_ULL 1124 arch/x86/kvm/vmx/nested.c if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) GENMASK_ULL 1136 arch/x86/kvm/vmx/nested.c BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | GENMASK_ULL 1139 arch/x86/kvm/vmx/nested.c GENMASK_ULL(13, 9) | BIT_ULL(31); GENMASK_ULL 1954 arch/x86/kvm/vmx/vmx.c if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) GENMASK_ULL 21 drivers/acpi/acpi_extlog.c #define EXT_ELOG_ENTRY_MASK GENMASK_ULL(51, 0) /* elog entry address mask */ GENMASK_ULL 43 drivers/acpi/acpi_lpit.c u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset + GENMASK_ULL 2154 drivers/ata/libahci.c devslp &= ~GENMASK_ULL(24, 2); GENMASK_ULL 871 drivers/clk/clk-stm32f4.c GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0); GENMASK_ULL 19 drivers/clk/qcom/gdsc.c #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) GENMASK_ULL 20 drivers/clk/qcom/gdsc.c #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16) GENMASK_ULL 21 drivers/clk/qcom/gdsc.c #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12) GENMASK_ULL 293 drivers/clocksource/hyperv_timer.c tsc_msr &= GENMASK_ULL(11, 0); GENMASK_ULL 658 drivers/cpufreq/intel_pstate.c value &= ~GENMASK_ULL(31, 24); GENMASK_ULL 827 drivers/cpufreq/intel_pstate.c value &= ~GENMASK_ULL(31, 24); GENMASK_ULL 843 drivers/cpufreq/intel_pstate.c value &= ~GENMASK_ULL(31, 0); GENMASK_ULL 1636 drivers/cpufreq/intel_pstate.c hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; GENMASK_ULL 152 drivers/crypto/qat/qat_common/adf_sriov.c adf_enable_vf2pf_interrupts(accel_dev, GENMASK_ULL(totalvfs - 1, 0)); GENMASK_ULL 211 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c GENMASK_ULL(GET_MAX_BANKS(accel_dev) - 1, 0)); GENMASK_ULL 400 drivers/edac/amd64_edac.c base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9); GENMASK_ULL 401 drivers/edac/amd64_edac.c mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9); GENMASK_ULL 413 drivers/edac/amd64_edac.c *base = (csbase & GENMASK_ULL(15, 5)) << 6; GENMASK_ULL 414 drivers/edac/amd64_edac.c *base |= (csbase & GENMASK_ULL(30, 19)) << 8; GENMASK_ULL 418 drivers/edac/amd64_edac.c *mask &= ~((GENMASK_ULL(15, 5) << 6) | GENMASK_ULL 419 drivers/edac/amd64_edac.c (GENMASK_ULL(30, 19) << 8)); GENMASK_ULL 421 drivers/edac/amd64_edac.c *mask |= (csmask & GENMASK_ULL(15, 5)) << 6; GENMASK_ULL 422 drivers/edac/amd64_edac.c *mask |= (csmask & GENMASK_ULL(30, 19)) << 8; GENMASK_ULL 432 drivers/edac/amd64_edac.c GENMASK_ULL(30,19) | GENMASK_ULL(13,5); GENMASK_ULL 435 drivers/edac/amd64_edac.c GENMASK_ULL(28,19) | GENMASK_ULL(13,5); GENMASK_ULL 627 drivers/edac/amd64_edac.c dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; GENMASK_ULL 663 drivers/edac/amd64_edac.c input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) + GENMASK_ULL 1162 drivers/edac/amd64_edac.c addr = m->addr & GENMASK_ULL(end_bit, start_bit); GENMASK_ULL 1172 drivers/edac/amd64_edac.c if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7) GENMASK_ULL 1180 drivers/edac/amd64_edac.c cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3; GENMASK_ULL 1189 drivers/edac/amd64_edac.c return cc6_base | (addr & GENMASK_ULL(23, 0)); GENMASK_ULL 1194 drivers/edac/amd64_edac.c tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1); GENMASK_ULL 1197 drivers/edac/amd64_edac.c tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9; GENMASK_ULL 1200 drivers/edac/amd64_edac.c tmp_addr |= addr & GENMASK_ULL(11, 0); GENMASK_ULL 1265 drivers/edac/amd64_edac.c pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); GENMASK_ULL 1270 drivers/edac/amd64_edac.c pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); GENMASK_ULL 1627 drivers/edac/amd64_edac.c addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); GENMASK_ULL 1793 drivers/edac/amd64_edac.c return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); GENMASK_ULL 67 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0) GENMASK_ULL 71 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21) GENMASK_ULL 72 drivers/edac/bluefield_edac.c #define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24) GENMASK_ULL 95 drivers/edac/ie31200_edac.c #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) GENMASK_ULL 142 drivers/edac/ie31200_edac.c #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) GENMASK_ULL 144 drivers/edac/ie31200_edac.c #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) GENMASK_ULL 158 drivers/edac/ie31200_edac.c #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) GENMASK_ULL 165 drivers/edac/ie31200_edac.c #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) GENMASK_ULL 123 drivers/edac/pnd2_edac.c #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) GENMASK_ULL 353 drivers/edac/pnd2_edac.c if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) { GENMASK_ULL 362 drivers/edac/pnd2_edac.c rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0); GENMASK_ULL 453 drivers/edac/pnd2_edac.c GENMASK_ULL(APL_ASYMSHIFT - 1, 0)); GENMASK_ULL 463 drivers/edac/pnd2_edac.c GENMASK_ULL(DNV_ASYMSHIFT - 1, 0)); GENMASK_ULL 547 drivers/edac/pnd2_edac.c GENMASK_ULL(APL_ASYMSHIFT - 1, 0)); GENMASK_ULL 52 drivers/edac/sb_edac.c (((v) & GENMASK_ULL(hi, lo)) >> (lo)) GENMASK_ULL 443 drivers/edac/skx_base.c rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); GENMASK_ULL 27 drivers/edac/skx_common.h (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) GENMASK_ULL 12 drivers/firmware/efi/cper-x86.c #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2) GENMASK_ULL 13 drivers/firmware/efi/cper-x86.c #define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8) GENMASK_ULL 47 drivers/firmware/efi/cper-x86.c #define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0))) GENMASK_ULL 48 drivers/firmware/efi/cper-x86.c #define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16) GENMASK_ULL 49 drivers/firmware/efi/cper-x86.c #define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18) GENMASK_ULL 50 drivers/firmware/efi/cper-x86.c #define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22) GENMASK_ULL 57 drivers/firmware/efi/cper-x86.c #define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30) GENMASK_ULL 59 drivers/firmware/efi/cper-x86.c #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33) GENMASK_ULL 68 drivers/firmware/efi/cper-x86.c #define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16) GENMASK_ULL 19 drivers/firmware/stratix10-rsu.c #define RSU_STATE_MASK GENMASK_ULL(31, 0) GENMASK_ULL 20 drivers/firmware/stratix10-rsu.c #define RSU_VERSION_MASK GENMASK_ULL(63, 32) GENMASK_ULL 21 drivers/firmware/stratix10-rsu.c #define RSU_ERROR_LOCATION_MASK GENMASK_ULL(31, 0) GENMASK_ULL 22 drivers/firmware/stratix10-rsu.c #define RSU_ERROR_DETAIL_MASK GENMASK_ULL(63, 32) GENMASK_ULL 23 drivers/firmware/stratix10-rsu.c #define RSU_FW_VERSION_MASK GENMASK_ULL(15, 0) GENMASK_ULL 1332 drivers/firmware/ti_sci.h #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) GENMASK_ULL 1333 drivers/firmware/ti_sci.h #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) GENMASK_ULL 27 drivers/fpga/dfl-afu-error.c #define ERROR_MASK GENMASK_ULL(63, 0) GENMASK_ULL 37 drivers/fpga/dfl-fme-error.c #define INJECT_ERROR_MASK GENMASK_ULL(2, 0) GENMASK_ULL 39 drivers/fpga/dfl-fme-error.c #define ERROR_MASK GENMASK_ULL(63, 0) GENMASK_ULL 72 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); GENMASK_ULL 117 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); GENMASK_ULL 231 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); GENMASK_ULL 39 drivers/fpga/dfl-fme-mgr.c #define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */ GENMASK_ULL 45 drivers/fpga/dfl-fme-mgr.c #define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0) GENMASK_ULL 48 drivers/fpga/dfl-fme-mgr.c #define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */ GENMASK_ULL 49 drivers/fpga/dfl-fme-mgr.c #define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */ GENMASK_ULL 53 drivers/fpga/dfl-fme-mgr.c #define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0) GENMASK_ULL 68 drivers/fpga/dfl.h #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ GENMASK_ULL 71 drivers/fpga/dfl.h #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ GENMASK_ULL 72 drivers/fpga/dfl.h #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ GENMASK_ULL 74 drivers/fpga/dfl.h #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ GENMASK_ULL 80 drivers/fpga/dfl.h #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ GENMASK_ULL 93 drivers/fpga/dfl.h #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ GENMASK_ULL 99 drivers/fpga/dfl.h #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */ GENMASK_ULL 100 drivers/fpga/dfl.h #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */ GENMASK_ULL 101 drivers/fpga/dfl.h #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */ GENMASK_ULL 102 drivers/fpga/dfl.h #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */ GENMASK_ULL 106 drivers/fpga/dfl.h #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0) GENMASK_ULL 108 drivers/fpga/dfl.h #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32) GENMASK_ULL 129 drivers/fpga/dfl.h #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ GENMASK_ULL 130 drivers/fpga/dfl.h #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */ GENMASK_ULL 131 drivers/fpga/dfl.h #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */ GENMASK_ULL 142 drivers/fpga/dfl.h #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */ GENMASK_ULL 122 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; GENMASK_ULL 123 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; GENMASK_ULL 124 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; GENMASK_ULL 135 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c me = (*pos & GENMASK_ULL(33, 24)) >> 24; GENMASK_ULL 136 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; GENMASK_ULL 137 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c queue = (*pos & GENMASK_ULL(53, 44)) >> 44; GENMASK_ULL 138 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; GENMASK_ULL 629 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c offset = (*pos & GENMASK_ULL(6, 0)); GENMASK_ULL 630 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c se = (*pos & GENMASK_ULL(14, 7)) >> 7; GENMASK_ULL 631 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c sh = (*pos & GENMASK_ULL(22, 15)) >> 15; GENMASK_ULL 632 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c cu = (*pos & GENMASK_ULL(30, 23)) >> 23; GENMASK_ULL 633 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c wave = (*pos & GENMASK_ULL(36, 31)) >> 31; GENMASK_ULL 634 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c simd = (*pos & GENMASK_ULL(44, 37)) >> 37; GENMASK_ULL 701 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c offset = (*pos & GENMASK_ULL(11, 0)) >> 2; GENMASK_ULL 702 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c se = (*pos & GENMASK_ULL(19, 12)) >> 12; GENMASK_ULL 703 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c sh = (*pos & GENMASK_ULL(27, 20)) >> 20; GENMASK_ULL 704 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c cu = (*pos & GENMASK_ULL(35, 28)) >> 28; GENMASK_ULL 705 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c wave = (*pos & GENMASK_ULL(43, 36)) >> 36; GENMASK_ULL 706 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c simd = (*pos & GENMASK_ULL(51, 44)) >> 44; GENMASK_ULL 707 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c thread = (*pos & GENMASK_ULL(59, 52)) >> 52; GENMASK_ULL 708 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c bank = (*pos & GENMASK_ULL(61, 60)) >> 60; GENMASK_ULL 228 drivers/gpu/drm/arm/malidp_crtc.c GENMASK_ULL(14, 0); GENMASK_ULL 1284 drivers/gpu/drm/i915/display/intel_display_power.c #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) GENMASK_ULL 294 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0); GENMASK_ULL 2111 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); GENMASK_ULL 2699 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ GENMASK_ULL 37 drivers/gpu/drm/i915/gvt/dmabuf.c #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12)) GENMASK_ULL 352 drivers/gpu/drm/i915/gvt/gtt.c #define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30) GENMASK_ULL 353 drivers/gpu/drm/i915/gvt/gtt.c #define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21) GENMASK_ULL 354 drivers/gpu/drm/i915/gvt/gtt.c #define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16) GENMASK_ULL 355 drivers/gpu/drm/i915/gvt/gtt.c #define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12) GENMASK_ULL 357 drivers/gpu/drm/i915/gvt/gtt.c #define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52) GENMASK_ULL 13 drivers/gpu/drm/i915/i915_buddy.h #define I915_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) GENMASK_ULL 14 drivers/gpu/drm/i915/i915_buddy.h #define I915_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) GENMASK_ULL 18 drivers/gpu/drm/i915/i915_buddy.h #define I915_BUDDY_HEADER_ORDER GENMASK_ULL(9, 0) GENMASK_ULL 102 drivers/gpu/drm/vc4/vc4_kms.c if ((in & GENMASK_ULL(62, 32)) > 0) { GENMASK_ULL 58 drivers/i2c/busses/i2c-rk3x.c #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8) GENMASK_ULL 2006 drivers/i3c/master.c if ((boardinfo->pid & GENMASK_ULL(63, 48)) || GENMASK_ULL 86 drivers/iio/accel/adxl372.c #define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0) GENMASK_ULL 90 drivers/iio/accel/adxl372.c #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4) GENMASK_ULL 92 drivers/iio/accel/adxl372.c #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0) GENMASK_ULL 96 drivers/iio/accel/adxl372.c #define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5) GENMASK_ULL 3156 drivers/iommu/amd_iommu_init.c u64 val = *value & GENMASK_ULL(47, 0); GENMASK_ULL 3164 drivers/iommu/amd_iommu_init.c *value &= GENMASK_ULL(47, 0); GENMASK_ULL 145 drivers/iommu/arm-smmu-v3.c #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) GENMASK_ULL 173 drivers/iommu/arm-smmu-v3.c #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) GENMASK_ULL 193 drivers/iommu/arm-smmu-v3.c #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) GENMASK_ULL 214 drivers/iommu/arm-smmu-v3.c #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0) GENMASK_ULL 215 drivers/iommu/arm-smmu-v3.c #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6) GENMASK_ULL 219 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1) GENMASK_ULL 225 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) GENMASK_ULL 227 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) GENMASK_ULL 228 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) GENMASK_ULL 234 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2) GENMASK_ULL 235 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) GENMASK_ULL 236 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) GENMASK_ULL 240 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) GENMASK_ULL 245 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_STRW GENMASK_ULL(31, 30) GENMASK_ULL 249 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44) GENMASK_ULL 252 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0) GENMASK_ULL 253 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32) GENMASK_ULL 259 drivers/iommu/arm-smmu-v3.c #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) GENMASK_ULL 263 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) GENMASK_ULL 264 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_T0SZ GENMASK_ULL(5, 0) GENMASK_ULL 265 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) GENMASK_ULL 266 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_TG0 GENMASK_ULL(15, 14) GENMASK_ULL 267 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) GENMASK_ULL 268 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_IRGN0 GENMASK_ULL(9, 8) GENMASK_ULL 269 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) GENMASK_ULL 270 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_ORGN0 GENMASK_ULL(11, 10) GENMASK_ULL 271 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) GENMASK_ULL 272 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_SH0 GENMASK_ULL(13, 12) GENMASK_ULL 281 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32) GENMASK_ULL 282 drivers/iommu/arm-smmu-v3.c #define ARM64_TCR_IPS GENMASK_ULL(34, 32) GENMASK_ULL 291 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) GENMASK_ULL 293 drivers/iommu/arm-smmu-v3.c #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) GENMASK_ULL 319 drivers/iommu/arm-smmu-v3.c #define CMDQ_0_OP GENMASK_ULL(7, 0) GENMASK_ULL 322 drivers/iommu/arm-smmu-v3.c #define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32) GENMASK_ULL 323 drivers/iommu/arm-smmu-v3.c #define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) GENMASK_ULL 324 drivers/iommu/arm-smmu-v3.c #define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) GENMASK_ULL 326 drivers/iommu/arm-smmu-v3.c #define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) GENMASK_ULL 328 drivers/iommu/arm-smmu-v3.c #define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) GENMASK_ULL 330 drivers/iommu/arm-smmu-v3.c #define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32) GENMASK_ULL 331 drivers/iommu/arm-smmu-v3.c #define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48) GENMASK_ULL 333 drivers/iommu/arm-smmu-v3.c #define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12) GENMASK_ULL 334 drivers/iommu/arm-smmu-v3.c #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12) GENMASK_ULL 336 drivers/iommu/arm-smmu-v3.c #define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12) GENMASK_ULL 337 drivers/iommu/arm-smmu-v3.c #define CMDQ_ATC_0_SID GENMASK_ULL(63, 32) GENMASK_ULL 339 drivers/iommu/arm-smmu-v3.c #define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0) GENMASK_ULL 340 drivers/iommu/arm-smmu-v3.c #define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12) GENMASK_ULL 342 drivers/iommu/arm-smmu-v3.c #define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12) GENMASK_ULL 343 drivers/iommu/arm-smmu-v3.c #define CMDQ_PRI_0_SID GENMASK_ULL(63, 32) GENMASK_ULL 344 drivers/iommu/arm-smmu-v3.c #define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0) GENMASK_ULL 345 drivers/iommu/arm-smmu-v3.c #define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12) GENMASK_ULL 347 drivers/iommu/arm-smmu-v3.c #define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12) GENMASK_ULL 351 drivers/iommu/arm-smmu-v3.c #define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22) GENMASK_ULL 352 drivers/iommu/arm-smmu-v3.c #define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24) GENMASK_ULL 353 drivers/iommu/arm-smmu-v3.c #define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32) GENMASK_ULL 354 drivers/iommu/arm-smmu-v3.c #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2) GENMASK_ULL 361 drivers/iommu/arm-smmu-v3.c #define EVTQ_0_ID GENMASK_ULL(7, 0) GENMASK_ULL 368 drivers/iommu/arm-smmu-v3.c #define PRIQ_0_SID GENMASK_ULL(31, 0) GENMASK_ULL 369 drivers/iommu/arm-smmu-v3.c #define PRIQ_0_SSID GENMASK_ULL(51, 32) GENMASK_ULL 377 drivers/iommu/arm-smmu-v3.c #define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0) GENMASK_ULL 378 drivers/iommu/arm-smmu-v3.c #define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12) GENMASK_ULL 1265 drivers/iommu/arm-smmu.c return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff); GENMASK_ULL 162 drivers/iommu/arm-smmu.h #define TTBRn_ASID GENMASK_ULL(63, 48) GENMASK_ULL 300 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); GENMASK_ULL 309 drivers/iommu/intel-pasid.c return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0)); GENMASK_ULL 329 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); GENMASK_ULL 339 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); GENMASK_ULL 395 drivers/iommu/intel-pasid.c pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); GENMASK_ULL 77 drivers/iommu/io-pgtable-arm.c #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12) GENMASK_ULL 256 drivers/irqchip/irq-alpine-msi.c priv->addr = res.start & GENMASK_ULL(63,20); GENMASK_ULL 204 drivers/irqchip/irq-gic-v3-its.c if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) GENMASK_ULL 324 drivers/irqchip/irq-gic-v3-its.c u64 mask = GENMASK_ULL(h, l); GENMASK_ULL 1699 drivers/irqchip/irq-gic-v3-its.c gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); GENMASK_ULL 2044 drivers/irqchip/irq-gic-v3-its.c addr = val & GENMASK_ULL(51, 12); GENMASK_ULL 2130 drivers/irqchip/irq-gic-v3-its.c paddr &= GENMASK_ULL(51, 12); GENMASK_ULL 2135 drivers/irqchip/irq-gic-v3-its.c paddr &= GENMASK_ULL(51, 16); GENMASK_ULL 2825 drivers/irqchip/irq-gic-v3-its.c GENMASK_ULL(51, 12); GENMASK_ULL 2832 drivers/irqchip/irq-gic-v3-its.c GENMASK_ULL(51, 16); GENMASK_ULL 180 drivers/mmc/host/cavium.c u64 bus_id_mask = GENMASK_ULL(61, 60); GENMASK_ULL 193 drivers/mmc/host/cavium.c return FIELD_GET(GENMASK_ULL(61, 60), reg); GENMASK_ULL 121 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8) GENMASK_ULL 122 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0) GENMASK_ULL 130 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36) GENMASK_ULL 133 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60) GENMASK_ULL 136 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49) GENMASK_ULL 137 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41) GENMASK_ULL 138 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38) GENMASK_ULL 139 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32) GENMASK_ULL 140 drivers/mmc/host/cavium.h #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0) GENMASK_ULL 143 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60) GENMASK_ULL 147 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51) GENMASK_ULL 151 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_BLOCK_CNT GENMASK_ULL(47, 32) GENMASK_ULL 152 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0) GENMASK_ULL 161 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36) GENMASK_ULL 162 drivers/mmc/host/cavium.h #define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0) GENMASK_ULL 172 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_STS_BUS_ID GENMASK_ULL(61, 60) GENMASK_ULL 190 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_STS_RSP_TYPE GENMASK_ULL(11, 9) GENMASK_ULL 191 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_STS_CMD_TYPE GENMASK_ULL(8, 7) GENMASK_ULL 192 drivers/mmc/host/cavium.h #define MIO_EMM_RSP_STS_CMD_IDX GENMASK_ULL(6, 1) GENMASK_ULL 195 drivers/mmc/host/cavium.h #define MIO_EMM_SAMPLE_CMD_CNT GENMASK_ULL(25, 16) GENMASK_ULL 196 drivers/mmc/host/cavium.h #define MIO_EMM_SAMPLE_DAT_CNT GENMASK_ULL(9, 0) GENMASK_ULL 198 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH_BUS_ID GENMASK_ULL(61, 60) GENMASK_ULL 204 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH_BUS_WIDTH GENMASK_ULL(42, 40) GENMASK_ULL 205 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH_POWER_CLASS GENMASK_ULL(35, 32) GENMASK_ULL 206 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH_CLK_HI GENMASK_ULL(31, 16) GENMASK_ULL 207 drivers/mmc/host/cavium.h #define MIO_EMM_SWITCH_CLK_LO GENMASK_ULL(15, 0) GENMASK_ULL 46 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define RST_RESERVED_BITS GENMASK_ULL(31, 0) GENMASK_ULL 50 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) GENMASK_ULL 55 drivers/mmc/host/renesas_sdhi_internal_dmac.c #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) GENMASK_ULL 1299 drivers/net/can/flexcan.c imask = GENMASK_ULL(priv->offload.mb_last, GENMASK_ULL 1097 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); GENMASK_ULL 1160 drivers/net/dsa/sja1105/sja1105_main.c l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); GENMASK_ULL 395 drivers/net/dsa/sja1105/sja1105_spi.c unsigned long port_bitmap = GENMASK_ULL(SJA1105_NUM_PORTS - 1, 0); GENMASK_ULL 11 drivers/net/dsa/sja1105/sja1105_tas.c #define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0) GENMASK_ULL 98 drivers/net/ethernet/amazon/ena/ena_com.c if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { GENMASK_ULL 493 drivers/net/ethernet/amazon/ena/ena_eth_com.c GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); GENMASK_ULL 590 drivers/net/ethernet/amazon/ena/ena_eth_com.c ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); GENMASK_ULL 3106 drivers/net/ethernet/amazon/ena/ena_netdev.c netdev->features & GENMASK_ULL(31, 0); GENMASK_ULL 3108 drivers/net/ethernet/amazon/ena/ena_netdev.c (netdev->features & GENMASK_ULL(63, 32)) >> 32; GENMASK_ULL 62 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) GENMASK_ULL 3105 drivers/net/ethernet/intel/i40e/i40e_ethtool.c #define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0) GENMASK_ULL 3106 drivers/net/ethernet/intel/i40e/i40e_ethtool.c #define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16) GENMASK_ULL 3107 drivers/net/ethernet/intel/i40e/i40e_ethtool.c #define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0) GENMASK_ULL 49 drivers/net/ethernet/marvell/octeontx2/af/cgx.h #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) GENMASK_ULL 122 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define EVTREG_ID GENMASK_ULL(8, 3) GENMASK_ULL 129 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define EVTREG_ERRTYPE GENMASK_ULL(18, 9) GENMASK_ULL 134 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_MAJOR_VER GENMASK_ULL(12, 9) GENMASK_ULL 135 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_MINOR_VER GENMASK_ULL(16, 13) GENMASK_ULL 140 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_MAC_ADDR GENMASK_ULL(56, 9) GENMASK_ULL 145 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9) GENMASK_ULL 150 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9) GENMASK_ULL 171 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9) GENMASK_ULL 172 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10) GENMASK_ULL 173 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11) GENMASK_ULL 174 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15) GENMASK_ULL 180 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define CMDREG_ID GENMASK_ULL(7, 2) GENMASK_ULL 189 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define CMDMTU_SIZE GENMASK_ULL(23, 8) GENMASK_ULL 194 drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h #define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10) GENMASK_ULL 264 drivers/net/ethernet/marvell/octeontx2/af/npc.h #define VTAG0_TYPE_MASK GENMASK_ULL(14, 12) GENMASK_ULL 265 drivers/net/ethernet/marvell/octeontx2/af/npc.h #define VTAG0_LID_MASK GENMASK_ULL(10, 8) GENMASK_ULL 266 drivers/net/ethernet/marvell/octeontx2/af/npc.h #define VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) GENMASK_ULL 155 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= GENMASK_ULL(item->size.bits - 1, 0); GENMASK_ULL 166 drivers/net/ethernet/mellanox/mlxsw/item.h u64 mask = GENMASK_ULL(item->size.bits - 1, 0) << item->shift; GENMASK_ULL 19 drivers/net/ethernet/mscc/ocelot_board.c #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) GENMASK_ULL 167 drivers/net/ethernet/mscc/ocelot_board.c full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | GENMASK_ULL 305 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (insn & ~GENMASK_ULL(NFP_USTORE_OP_BITS, 0)) GENMASK_ULL 31 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_STATUS_MAGIC GENMASK_ULL(63, 48) GENMASK_ULL 32 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_STATUS_MAJOR GENMASK_ULL(47, 44) GENMASK_ULL 33 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_STATUS_MINOR GENMASK_ULL(43, 32) GENMASK_ULL 34 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_STATUS_CODE GENMASK_ULL(31, 16) GENMASK_ULL 35 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_STATUS_RESULT GENMASK_ULL(15, 8) GENMASK_ULL 39 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_COMMAND_OPTION GENMASK_ULL(63, 32) GENMASK_ULL 40 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_COMMAND_CODE GENMASK_ULL(31, 16) GENMASK_ULL 46 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_BUFFER_CPP GENMASK_ULL(63, 40) GENMASK_ULL 47 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_BUFFER_ADDRESS GENMASK_ULL(39, 0) GENMASK_ULL 50 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_DFLT_BUFFER_CPP GENMASK_ULL(63, 40) GENMASK_ULL 51 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_DFLT_BUFFER_ADDRESS GENMASK_ULL(39, 0) GENMASK_ULL 54 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_DFLT_BUFFER_DMA_CHUNK_ORDER GENMASK_ULL(63, 58) GENMASK_ULL 55 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_DFLT_BUFFER_SIZE_4KB GENMASK_ULL(15, 8) GENMASK_ULL 56 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_DFLT_BUFFER_SIZE_MB GENMASK_ULL(7, 0) GENMASK_ULL 24 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0) GENMASK_ULL 25 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8) GENMASK_ULL 26 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48) GENMASK_ULL 27 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54) GENMASK_ULL 37 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8) GENMASK_ULL 38 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12) GENMASK_ULL 39 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20) GENMASK_ULL 41 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23) GENMASK_ULL 42 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26) GENMASK_ULL 463 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c *addr &= ~GENMASK_ULL(idx_lsb, iid_lsb); GENMASK_ULL 501 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb); GENMASK_ULL 590 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb); GENMASK_ULL 597 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb); GENMASK_ULL 618 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb); GENMASK_ULL 653 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb); GENMASK_ULL 693 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c *addr &= ~GENMASK_ULL(29, 24); GENMASK_ULL 694 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c *addr |= ((u64)dest_island << 24) & GENMASK_ULL(29, 24); GENMASK_ULL 183 drivers/net/fjes/fjes_hw.c (__le32)(param->req_start & GENMASK_ULL(31, 0))); GENMASK_ULL 185 drivers/net/fjes/fjes_hw.c (__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32)); GENMASK_ULL 189 drivers/net/fjes/fjes_hw.c (__le32)(param->res_start & GENMASK_ULL(31, 0))); GENMASK_ULL 191 drivers/net/fjes/fjes_hw.c (__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32)); GENMASK_ULL 195 drivers/net/fjes/fjes_hw.c (__le32)(param->share_start & GENMASK_ULL(31, 0))); GENMASK_ULL 197 drivers/net/fjes/fjes_hw.c (__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32)); GENMASK_ULL 31 drivers/net/wireless/ath/ath10k/ce.h #define CE_DESC_ADDR_MASK GENMASK_ULL(34, 0) GENMASK_ULL 671 drivers/ntb/test/ntb_perf.c mask = GENMASK_ULL(perf->pcnt, 0); GENMASK_ULL 259 drivers/ntb/test/ntb_pingpong.c pmask = GENMASK_ULL(ntb_peer_port_count(ntb), 0); GENMASK_ULL 307 drivers/ntb/test/ntb_pingpong.c pp->pmask = GENMASK_ULL(pidx, 0) >> 1; GENMASK_ULL 308 drivers/ntb/test/ntb_pingpong.c pp->nmask = GENMASK_ULL(pcnt - 1, pidx); GENMASK_ULL 344 drivers/pci/controller/pcie-cadence-ep.c pci_addr &= GENMASK_ULL(63, 2); GENMASK_ULL 455 drivers/pci/controller/pcie-rockchip-ep.c pci_addr &= GENMASK_ULL(63, 2); GENMASK_ULL 73 drivers/perf/arm_dsu_pmu.c GENMASK_ULL((DSU_PMU_COUNTER_WIDTH((idx)) - 1), 0) GENMASK_ULL 35 drivers/perf/arm_pmu.c return GENMASK_ULL(63, 0); GENMASK_ULL 37 drivers/perf/arm_pmu.c return GENMASK_ULL(31, 0); GENMASK_ULL 86 drivers/perf/arm_smmuv3_pmu.c #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) GENMASK_ULL 123 drivers/perf/arm_smmuv3_pmu.c return FIELD_GET(GENMASK_ULL(_end, _start), \ GENMASK_ULL 698 drivers/perf/arm_smmuv3_pmu.c u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0); GENMASK_ULL 789 drivers/perf/arm_smmuv3_pmu.c smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0); GENMASK_ULL 18 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0) GENMASK_ULL 19 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0) GENMASK_ULL 25 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0) GENMASK_ULL 26 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0) GENMASK_ULL 30 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0) GENMASK_ULL 31 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8) GENMASK_ULL 35 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) GENMASK_ULL 36 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) GENMASK_ULL 43 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0) GENMASK_ULL 44 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0) GENMASK_ULL 50 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0) GENMASK_ULL 51 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0) GENMASK_ULL 55 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0) GENMASK_ULL 56 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8) GENMASK_ULL 60 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) GENMASK_ULL 61 drivers/platform/mellanox/mlxbf-tmfifo-regs.h #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) GENMASK_ULL 129 drivers/platform/x86/intel_speed_select_if/isst_if_common.c full_cmd = (cmd & GENMASK_ULL(15, 0)) << 16; GENMASK_ULL 130 drivers/platform/x86/intel_speed_select_if/isst_if_common.c full_cmd |= (sub_cmd & GENMASK_ULL(15, 0)); GENMASK_ULL 155 drivers/platform/x86/intel_speed_select_if/isst_if_common.c mbox_cmd.command = (sst_cmd->cmd & GENMASK_ULL(31, 16)) >> 16; GENMASK_ULL 156 drivers/platform/x86/intel_speed_select_if/isst_if_common.c mbox_cmd.sub_command = sst_cmd->cmd & GENMASK_ULL(15, 0); GENMASK_ULL 61 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c (parameter & GENMASK_ULL(13, 0)) << 16 | GENMASK_ULL 69 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_pci.c (mbox_cmd->parameter & GENMASK_ULL(13, 0)) << 16 | GENMASK_ULL 169 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val &= ~GENMASK_ULL(31, 24); GENMASK_ULL 1261 fs/proc/task_mmu.c #define PM_PFRAME_MASK GENMASK_ULL(PM_PFRAME_BITS - 1, 0) GENMASK_ULL 162 include/asm-generic/mshyperv.h vpset->valid_bank_mask = GENMASK_ULL(nr_bank - 1, 0); GENMASK_ULL 125 include/linux/clocksource.h #define CLOCKSOURCE_MASK(bits) GENMASK_ULL((bits) - 1, 0) GENMASK_ULL 79 include/linux/i3c/device.h #define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33) GENMASK_ULL 81 include/linux/i3c/device.h #define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0)) GENMASK_ULL 82 include/linux/i3c/device.h #define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16) GENMASK_ULL 83 include/linux/i3c/device.h #define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12) GENMASK_ULL 84 include/linux/i3c/device.h #define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0)) GENMASK_ULL 164 include/linux/irqchip/arm-gic-v3.h #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) GENMASK_ULL 190 include/linux/irqchip/arm-gic-v3.h #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) GENMASK_ULL 191 include/linux/irqchip/arm-gic-v3.h #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) GENMASK_ULL 375 include/linux/irqchip/arm-gic-v3.h #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12)) GENMASK_ULL 405 include/linux/irqchip/arm-gic-v3.h #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) GENMASK_ULL 407 include/linux/irqchip/arm-gic-v3.h (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) GENMASK_ULL 409 include/linux/irqchip/arm-gic-v3.h (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) GENMASK_ULL 304 include/linux/mtd/spi-nor.h #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) GENMASK_ULL 310 include/linux/mtd/spi-nor.h #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) GENMASK_ULL 41 include/media/media-entity.h #define MEDIA_ID_MASK GENMASK_ULL(MEDIA_BITS_PER_ID - 1, 0) GENMASK_ULL 5699 include/net/cfg80211.h u64 mask = GENMASK_ULL(max_bssid - 1, 0); GENMASK_ULL 164 lib/842/842_compress.c return add_bits(p, d & GENMASK_ULL(s - 1, 0), s); GENMASK_ULL 118 lib/842/842_decompress.c *d &= GENMASK_ULL(n - 1, 0); GENMASK_ULL 57 lib/packing.c *box_mask = GENMASK_ULL(new_box_start_bit, new_box_end_bit); GENMASK_ULL 161 lib/packing.c proj_mask = GENMASK_ULL(proj_start_bit, proj_end_bit); GENMASK_ULL 162 lib/packing.c box_mask = GENMASK_ULL(box_start_bit, box_end_bit); GENMASK_ULL 51 sound/soc/sof/intel/byt.c #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) GENMASK_ULL 954 virt/kvm/arm/vgic/vgic-its.c indirect_ptr &= GENMASK_ULL(51, 16); GENMASK_ULL 1474 virt/kvm/arm/vgic/vgic-its.c reg &= ~GENMASK_ULL(15, 12); GENMASK_ULL 1634 virt/kvm/arm/vgic/vgic-its.c #define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56)) GENMASK_ULL 23 virt/kvm/arm/vgic/vgic-mmio-v3.c return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); GENMASK_ULL 33 virt/kvm/arm/vgic/vgic-mmio-v3.c reg &= ~GENMASK_ULL(upper, lower); GENMASK_ULL 34 virt/kvm/arm/vgic/vgic-mmio-v3.c val &= GENMASK_ULL(len * 8 - 1, 0); GENMASK_ULL 346 virt/kvm/arm/vgic/vgic-mmio-v3.c (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) GENMASK_ULL 348 virt/kvm/arm/vgic/vgic-mmio-v3.c (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ GENMASK_ULL 349 virt/kvm/arm/vgic/vgic-mmio-v3.c GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) GENMASK_ULL 72 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0) GENMASK_ULL 75 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16) GENMASK_ULL 76 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0) GENMASK_ULL 80 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49) GENMASK_ULL 82 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5) GENMASK_ULL 83 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0) GENMASK_ULL 86 virt/kvm/arm/vgic/vgic.h #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16) GENMASK_ULL 88 virt/kvm/arm/vgic/vgic.h #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0) GENMASK_ULL 89 virt/kvm/arm/vgic/vgic.h #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12) GENMASK_ULL 91 virt/kvm/arm/vgic/vgic.h #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16) GENMASK_ULL 92 virt/kvm/arm/vgic/vgic.h #define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52)