GENMASK            21 arch/arm/kernel/smp_scu.c #define SCU_CPU_STATUS_MASK	GENMASK(1, 0)
GENMASK           371 arch/arm/mm/cache-uniphier.c 	data->way_mask = GENMASK(cache_size / data->nsets / data->line_size - 1,
GENMASK           113 arch/arm/mm/pmsa-v7.c 	u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0);
GENMASK           121 arch/arm/mm/pmsa-v7.c 	u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16);
GENMASK           452 arch/arm64/include/asm/cpufeature.h 	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
GENMASK            72 arch/arm64/include/asm/pointer_auth.h #define ptrauth_user_pac_mask()	GENMASK(54, vabits_actual)
GENMASK           218 arch/arm64/include/asm/sysreg.h #define SYS_PAR_EL1_FST			GENMASK(6, 1)
GENMASK           377 arch/arm64/kernel/insn.c 	return (insn >> shift) & GENMASK(4, 0);
GENMASK           416 arch/arm64/kernel/insn.c 	insn &= ~(GENMASK(4, 0) << shift);
GENMASK           445 arch/arm64/kernel/insn.c 	insn &= ~GENMASK(31, 30);
GENMASK           813 arch/arm64/kernel/insn.c 	insn &= ~GENMASK(4, 0);
GENMASK           923 arch/arm64/kernel/insn.c 		mask = GENMASK(4, 0);
GENMASK           927 arch/arm64/kernel/insn.c 		mask = GENMASK(5, 0);
GENMASK           296 arch/arm64/kvm/guest.c 	GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1,	\
GENMASK           299 arch/arm64/kvm/guest.c 	GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
GENMASK            45 arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c 	fault_ipa |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
GENMASK          1320 arch/arm64/kvm/sys_regs.c 		p->regval &= ~GENMASK(27, 3);
GENMASK            84 arch/arm64/kvm/va_layout.c 						    tag_val & GENMASK(11, 0),
GENMASK            91 arch/arm64/kvm/va_layout.c 						    tag_val & GENMASK(23, 12),
GENMASK            29 arch/arm64/mm/context.c #define ASID_MASK		(~GENMASK(asid_bits - 1, 0))
GENMASK            18 arch/csky/mm/asid.c #define ASID_MASK(info)			(~GENMASK((info)->bits - 1, 0))
GENMASK            11 arch/mips/generic/board-ocelot.c #define CHIP_ID_PART_ID			GENMASK(27, 12)
GENMASK           278 arch/mips/include/asm/kvm_host.h #define VPN2_MASK		GENMASK(cpu_vmbits - 1, 13)
GENMASK            51 arch/mips/include/asm/mach-loongson32/regs-clk.h #define FRAC_N				GENMASK(23, 16)
GENMASK            52 arch/mips/include/asm/mach-loongson32/regs-clk.h #define RST_TIME			GENMASK(3, 2)
GENMASK            53 arch/mips/include/asm/mach-loongson32/regs-clk.h #define SDRAM_DIV			GENMASK(1, 0)
GENMASK            57 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_DC				GENMASK(30, 24)
GENMASK            59 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CAM				GENMASK(22, 16)
GENMASK            61 arch/mips/include/asm/mach-loongson32/regs-clk.h #define DIV_CPU				GENMASK(14, 8)
GENMASK            67 arch/mips/include/asm/mach-loongson32/regs-mux.h #define UART_SPLIT			GENMASK(31, 30)
GENMASK            68 arch/mips/include/asm/mach-loongson32/regs-mux.h #define OUTPUT_CLK			GENMASK(29, 26)
GENMASK           101 arch/mips/include/asm/mach-loongson32/regs-mux.h #define PHY_INTF_SELI			GENMASK(30, 28)
GENMASK           103 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SDIO_DMA_EN			GENMASK(24, 23)
GENMASK           107 arch/mips/include/asm/mach-loongson32/regs-mux.h #define SRAM_CTRL			GENMASK(15, 0)
GENMASK           133 arch/mips/include/asm/mips-cm.h #define CM_GCR_CONFIG_NUM_CLUSTERS		GENMASK(29, 23)
GENMASK           134 arch/mips/include/asm/mips-cm.h #define CM_GCR_CONFIG_NUMIOCU			GENMASK(15, 8)
GENMASK           135 arch/mips/include/asm/mips-cm.h #define CM_GCR_CONFIG_PCORES			GENMASK(7, 0)
GENMASK           140 arch/mips/include/asm/mips-cm.h #define CM_GCR_BASE_CMDEFTGT			GENMASK(1, 0)
GENMASK           148 arch/mips/include/asm/mips-cm.h #define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)
GENMASK           152 arch/mips/include/asm/mips-cm.h #define CM_GCR_REV_MAJOR			GENMASK(15, 8)
GENMASK           153 arch/mips/include/asm/mips-cm.h #define CM_GCR_REV_MINOR			GENMASK(7, 0)
GENMASK           174 arch/mips/include/asm/mips-cm.h #define CM_GCR_ERROR_CAUSE_ERRTYPE		GENMASK(31, 27)
GENMASK           176 arch/mips/include/asm/mips-cm.h #define CM_GCR_ERROR_CAUSE_ERRINFO		GENMASK(26, 0)
GENMASK           183 arch/mips/include/asm/mips-cm.h #define CM_GCR_ERROR_MULT_ERR2ND		GENMASK(4, 0)
GENMASK           187 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE	GENMASK(31, 12)
GENMASK           192 arch/mips/include/asm/mips-cm.h #define CM_GCR_GIC_BASE_GICBASE			GENMASK(31, 17)
GENMASK           197 arch/mips/include/asm/mips-cm.h #define CM_GCR_CPC_BASE_CPCBASE			GENMASK(31, 15)
GENMASK           205 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_BASE_BASEADDR		GENMASK(31, 16)
GENMASK           212 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_MASK_ADDRMASK		GENMASK(31, 16)
GENMASK           213 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_MASK_CCAOVR			GENMASK(7, 5)
GENMASK           216 arch/mips/include/asm/mips-cm.h #define CM_GCR_REGn_MASK_CMTGT			GENMASK(1, 0)
GENMASK           233 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_CONFIG_SET_SIZE		GENMASK(15, 12)
GENMASK           234 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_CONFIG_LINE_SIZE		GENMASK(11, 8)
GENMASK           235 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_CONFIG_ASSOC			GENMASK(7, 0)
GENMASK           239 arch/mips/include/asm/mips-cm.h #define CM_GCR_SYS_CONFIG2_MAXVPW		GENMASK(3, 0)
GENMASK           243 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_PFT_CONTROL_PAGEMASK		GENMASK(31, 12)
GENMASK           245 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_PFT_CONTROL_NPFT		GENMASK(7, 0)
GENMASK           250 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2_PFT_CONTROL_B_PORTID		GENMASK(7, 0)
GENMASK           255 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_COP_RESULT			GENMASK(8, 6)
GENMASK           262 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_COP_TYPE			GENMASK(4, 2)
GENMASK           270 arch/mips/include/asm/mips-cm.h #define CM_GCR_L2SM_COP_CMD			GENMASK(1, 0)
GENMASK           287 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_COHERENCE_COHDOMAINEN		GENMASK(7, 0)
GENMASK           292 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_CONFIG_IOCUTYPE		GENMASK(11, 10)
GENMASK           293 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_CONFIG_PVPE			GENMASK(9, 0)
GENMASK           297 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_OTHER_CORENUM			GENMASK(31, 16)	/* CM < 3 */
GENMASK           300 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_OTHER_BLOCK			GENMASK(25, 24)	/* CM >= 3.5 */
GENMASK           305 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_OTHER_CLUSTER			GENMASK(21, 16)	/* CM >= 3.5 */
GENMASK           306 arch/mips/include/asm/mips-cm.h #define CM3_GCR_Cx_OTHER_CORE			GENMASK(13, 8)	/* CM >= 3 */
GENMASK           308 arch/mips/include/asm/mips-cm.h #define CM3_GCR_Cx_OTHER_VP			GENMASK(2, 0)	/* CM >= 3 */
GENMASK           312 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE		GENMASK(31, 12)
GENMASK           316 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_ID_CLUSTER			GENMASK(15, 8)
GENMASK           317 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_ID_CORE			GENMASK(7, 0)
GENMASK           323 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK	GENMASK(27, 20)
GENMASK           324 arch/mips/include/asm/mips-cm.h #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA	GENMASK(7, 1)
GENMASK           110 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_CMD				GENMASK(3, 0)
GENMASK           119 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_STAT_CONF_SEQSTATE		GENMASK(22, 19)
GENMASK           137 arch/mips/include/asm/mips-cpc.h #define CPC_Cx_OTHER_CORENUM			GENMASK(23, 16)
GENMASK           166 arch/mips/include/asm/mips-gic.h #define GIC_CONFIG_COUNTBITS		GENMASK(27, 24)
GENMASK           167 arch/mips/include/asm/mips-gic.h #define GIC_CONFIG_NUMINTERRUPTS	GENMASK(23, 16)
GENMASK           168 arch/mips/include/asm/mips-gic.h #define GIC_CONFIG_PVPS			GENMASK(6, 0)
GENMASK           195 arch/mips/include/asm/mips-gic.h #define GIC_WEDGE_INTR			GENMASK(7, 0)
GENMASK           213 arch/mips/include/asm/mips-gic.h #define GIC_MAP_PIN_MAP			GENMASK(5, 0)
GENMASK           264 arch/mips/include/asm/mips-gic.h #define GIC_VX_OTHER_VPNUM		GENMASK(5, 0)
GENMASK           268 arch/mips/include/asm/mips-gic.h #define GIC_VX_IDENT_VPNUM		GENMASK(5, 0)
GENMASK            20 arch/mips/kernel/cmpxchg.c 	mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
GENMASK            61 arch/mips/kernel/cmpxchg.c 	mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
GENMASK           936 arch/mips/kernel/cpu-probe.c 			if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
GENMASK           939 arch/mips/kernel/cpu-probe.c 				asid_mask = GENMASK(max_mmid_width - 1, 0);
GENMASK           193 arch/mips/kernel/module.c 	unsigned long mask = GENMASK(bits - 1, 0);
GENMASK          1007 arch/sparc/include/asm/hypervisor.h #define HV_CCB_ARG0_TYPE_NUCLEUS	GENMASK(5, 4)
GENMASK          1013 arch/sparc/include/asm/hypervisor.h #define HV_CCB_VA_NUCLEUS		GENMASK(13, 12)
GENMASK          3760 arch/x86/events/intel/uncore_snbep.c #define SKX_CHA_BIT_MASK	GENMASK(27, 0)
GENMASK            15 arch/x86/include/asm/cpu_device_id.h #define X86_STEPPINGS(mins, maxs)    GENMASK(maxs, mins)
GENMASK           831 arch/x86/kernel/cpu/mce/amd.c 		dram_hole_base = tmp & GENMASK(31, 24);
GENMASK            47 arch/x86/kernel/cpu/resctrl/pseudo_lock.c static unsigned long pseudo_lock_minor_avail = GENMASK(MINORBITS, 0);
GENMASK          2624 arch/x86/kvm/vmx/nested.c 		       vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
GENMASK           674 arch/x86/pci/fixup.c #define AMD_141b_MMIO_BASE_MMIOBASE_MASK	GENMASK(31,8)
GENMASK           677 arch/x86/pci/fixup.c #define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK	GENMASK(31,8)
GENMASK           680 arch/x86/pci/fixup.c #define AMD_141b_MMIO_HIGH_MMIOBASE_MASK	GENMASK(7,0)
GENMASK           682 arch/x86/pci/fixup.c #define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK	GENMASK(23,16)
GENMASK           928 drivers/acpi/acpi_lpss.c #define LPSS_PMCSR_Dx_MASK		GENMASK(1, 0)
GENMASK           933 drivers/acpi/acpi_lpss.c #define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)
GENMASK            19 drivers/acpi/pmic/intel_pmic_xpower.c #define GPI1_LDO_MASK		GENMASK(2, 0)
GENMASK            23 drivers/acpi/pmic/intel_pmic_xpower.c #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK		GENMASK(1, 0)
GENMASK            23 drivers/ata/ahci_mtk.c #define SYS_CFG_SATA_MSK	GENMASK(31, 30)
GENMASK           704 drivers/ata/libahci_platform.c 	writel(GENMASK(host->n_ports, 0), mmio + HOST_IRQ_STAT);
GENMASK          1211 drivers/base/regmap/regmap.c 	rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb);
GENMASK            82 drivers/bluetooth/btmtksdio.c #define RX_PKT_LEN		GENMASK(31, 16)
GENMASK            34 drivers/bus/qcom-ebi2.c #define EBI2_CSN_MASK GENMASK(9, 0)
GENMASK            80 drivers/bus/sunxi-rsb.c #define RSB_INTS_TRANS_ERR_DATA		GENMASK(11, 8)
GENMASK           348 drivers/bus/sunxi-rsb.c 	*buf = readl(rsb->regs + RSB_DATA) & GENMASK(len * 8 - 1, 0);
GENMASK            28 drivers/char/ipmi/kcs_bmc.c #define KCS_STATUS_STATE_MASK   GENMASK(7, 6)
GENMASK           978 drivers/char/tpm/tpm2-cmd.c 				~(GENMASK(2, 0) << TPM2_CC_ATTR_CHANDLES);
GENMASK          1062 drivers/char/tpm/tpm2-cmd.c 		if (cc == (chip->cc_attrs_tbl[i] & GENMASK(15, 0)))
GENMASK           249 drivers/char/tpm/tpm2-space.c 	nr_handles = (attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0);
GENMASK           286 drivers/char/tpm/tpm2-space.c 		4 * ((attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0));
GENMASK            73 drivers/clk/actions/owl-divider.c 	reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
GENMASK            42 drivers/clk/actions/owl-mux.c 	reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
GENMASK            55 drivers/clk/at91/at91sam9x5.c 	.pid_mask = GENMASK(5, 0),
GENMASK            56 drivers/clk/at91/at91sam9x5.c 	.div_mask = GENMASK(17, 16),
GENMASK            18 drivers/clk/at91/clk-sam9x60-pll.c #define		PMC_PLL_CTRL0_DIV_MSK		GENMASK(7, 0)
GENMASK            24 drivers/clk/at91/clk-sam9x60-pll.c #define		PMC_PLL_CTRL1_FRACR_MSK		GENMASK(21, 0)
GENMASK            25 drivers/clk/at91/clk-sam9x60-pll.c #define		PMC_PLL_CTRL1_MUL_MSK		GENMASK(30, 24)
GENMASK            31 drivers/clk/at91/clk-sam9x60-pll.c #define		PMC_PLL_ACR_LOOP_FILTER_MSK	GENMASK(31, 24)
GENMASK            21 drivers/clk/at91/clk-usb.c #define SAM9X5_USBS_MASK	GENMASK(0, 0)
GENMASK            22 drivers/clk/at91/clk-usb.c #define SAM9X60_USBS_MASK	GENMASK(1, 0)
GENMASK            99 drivers/clk/at91/dt-compat.c 	.pid_mask = GENMASK(5, 0),
GENMASK           100 drivers/clk/at91/dt-compat.c 	.div_mask = GENMASK(17, 16),
GENMASK           101 drivers/clk/at91/dt-compat.c 	.gckcss_mask = GENMASK(10, 8),
GENMASK            56 drivers/clk/at91/sam9x60.c 	.gckcss_mask = GENMASK(12, 8),
GENMASK            57 drivers/clk/at91/sam9x60.c 	.pid_mask = GENMASK(6, 0),
GENMASK            34 drivers/clk/at91/sama5d2.c 	.gckcss_mask = GENMASK(10, 8),
GENMASK            35 drivers/clk/at91/sama5d2.c 	.pid_mask = GENMASK(6, 0),
GENMASK            34 drivers/clk/at91/sama5d4.c 	.pid_mask = GENMASK(6, 0),
GENMASK            44 drivers/clk/bcm/clk-bcm2835.c # define CM_DIV_FRAC_MASK	GENMASK(CM_DIV_FRAC_BITS - 1, 0)
GENMASK           222 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLL_KA_MASK		GENMASK(9, 7)
GENMASK           224 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLL_KI_MASK		GENMASK(21, 19)
GENMASK           226 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLL_KP_MASK		GENMASK(18, 15)
GENMASK           229 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLLH_KA_MASK	GENMASK(21, 19)
GENMASK           231 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLLH_KI_LOW_MASK	GENMASK(23, 22)
GENMASK           233 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLLH_KI_HIGH_MASK	GENMASK(0, 0)
GENMASK           235 drivers/clk/bcm/clk-bcm2835.c #define A2W_PLLH_KP_MASK	GENMASK(4, 1)
GENMASK           925 drivers/clk/bcm/clk-bcm2835.c 		GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
GENMASK           948 drivers/clk/bcm/clk-bcm2835.c 		maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
GENMASK           517 drivers/clk/clk-ast2600.c 	regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
GENMASK            88 drivers/clk/clk-fractional-divider.c 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
GENMASK           122 drivers/clk/clk-fractional-divider.c 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
GENMASK           178 drivers/clk/clk-fractional-divider.c 	fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
GENMASK           181 drivers/clk/clk-fractional-divider.c 	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
GENMASK            32 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_CTRL_ODIV_MASK		GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
GENMASK            33 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_CTRL_IDIV_MASK		GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
GENMASK            34 drivers/clk/clk-hsdk-pll.c #define CGU_PLL_CTRL_FBDIV_MASK		GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
GENMASK            48 drivers/clk/clk-multiplier.c 	val &= GENMASK(mult->width - 1, 0);
GENMASK           139 drivers/clk/clk-multiplier.c 	val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);
GENMASK            32 drivers/clk/clk-npcm7xx.c #define PLLCON_FBDV	GENMASK(27, 16)
GENMASK            33 drivers/clk/clk-npcm7xx.c #define PLLCON_OTDV2	GENMASK(15, 13)
GENMASK            35 drivers/clk/clk-npcm7xx.c #define PLLCON_OTDV1	GENMASK(10, 8)
GENMASK            36 drivers/clk/clk-npcm7xx.c #define PLLCON_INDV	GENMASK(5, 0)
GENMASK           328 drivers/clk/clk-npcm7xx.c 	{0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
GENMASK           332 drivers/clk/clk-npcm7xx.c 	{4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
GENMASK           336 drivers/clk/clk-npcm7xx.c 	{6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
GENMASK           339 drivers/clk/clk-npcm7xx.c 	{8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
GENMASK           342 drivers/clk/clk-npcm7xx.c 	{10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
GENMASK           345 drivers/clk/clk-npcm7xx.c 	{12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
GENMASK           348 drivers/clk/clk-npcm7xx.c 	{14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
GENMASK           351 drivers/clk/clk-npcm7xx.c 	{16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
GENMASK           354 drivers/clk/clk-npcm7xx.c 	{18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
GENMASK           357 drivers/clk/clk-npcm7xx.c 	{21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
GENMASK           360 drivers/clk/clk-npcm7xx.c 	{23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
GENMASK          1198 drivers/clk/clk-qoriq.c 		mult = (mult & GENMASK(8, 1)) >> 1;
GENMASK          1200 drivers/clk/clk-qoriq.c 		mult = (mult & GENMASK(6, 1)) >> 1;
GENMASK           740 drivers/clk/clk-stm32h7.c 		GENMASK(fd->fwidth - 1, 0);
GENMASK           753 drivers/clk/clk-stm32h7.c 	mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
GENMASK           757 drivers/clk/clk-stm32h7.c 	mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
GENMASK            18 drivers/clk/davinci/pll-da830.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            33 drivers/clk/davinci/pll-da850.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            86 drivers/clk/davinci/pll-da850.c 	.ocsrc_mask = GENMASK(4, 0),
GENMASK           164 drivers/clk/davinci/pll-da850.c 	.pllm_mask = GENMASK(4, 0),
GENMASK           195 drivers/clk/davinci/pll-da850.c 	.ocsrc_mask = GENMASK(4, 0),
GENMASK            18 drivers/clk/davinci/pll-dm355.c 	.pllm_mask = GENMASK(7, 0),
GENMASK            59 drivers/clk/davinci/pll-dm355.c 	.pllm_mask = GENMASK(7, 0),
GENMASK            21 drivers/clk/davinci/pll-dm365.c 	.pllm_mask = GENMASK(9, 0),
GENMASK           102 drivers/clk/davinci/pll-dm365.c 	.pllm_mask = GENMASK(9, 0),
GENMASK            18 drivers/clk/davinci/pll-dm644x.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            59 drivers/clk/davinci/pll-dm644x.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            18 drivers/clk/davinci/pll-dm646x.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            70 drivers/clk/davinci/pll-dm646x.c 	.pllm_mask = GENMASK(4, 0),
GENMASK            51 drivers/clk/davinci/psc.c #define MDSTAT_STATE_MASK	GENMASK(5, 0)
GENMASK            53 drivers/clk/davinci/psc.c #define PDSTAT_STATE_MASK	GENMASK(4, 0)
GENMASK            28 drivers/clk/imx/clk-frac-pll.c #define PLL_FRAC_DIV_MASK	GENMASK(30, 7)
GENMASK            29 drivers/clk/imx/clk-frac-pll.c #define PLL_INT_DIV_MASK	GENMASK(6, 0)
GENMASK            30 drivers/clk/imx/clk-frac-pll.c #define PLL_OUTPUT_DIV_MASK	GENMASK(4, 0)
GENMASK            24 drivers/clk/imx/clk-pll14xx.c #define MDIV_MASK	GENMASK(21, 12)
GENMASK            26 drivers/clk/imx/clk-pll14xx.c #define PDIV_MASK	GENMASK(9, 4)
GENMASK            28 drivers/clk/imx/clk-pll14xx.c #define SDIV_MASK	GENMASK(2, 0)
GENMASK            30 drivers/clk/imx/clk-pll14xx.c #define KDIV_MASK	GENMASK(15, 0)
GENMASK            25 drivers/clk/imx/clk-sccg-pll.c #define PLL_DIVF1_MASK		GENMASK(18, 13)
GENMASK            26 drivers/clk/imx/clk-sccg-pll.c #define PLL_DIVF2_MASK		GENMASK(12, 7)
GENMASK            27 drivers/clk/imx/clk-sccg-pll.c #define PLL_DIVR1_MASK		GENMASK(27, 25)
GENMASK            28 drivers/clk/imx/clk-sccg-pll.c #define PLL_DIVR2_MASK		GENMASK(24, 19)
GENMASK            29 drivers/clk/imx/clk-sccg-pll.c #define PLL_DIVQ_MASK           GENMASK(6, 1)
GENMASK            30 drivers/clk/imx/clk-sccg-pll.c #define PLL_REF_MASK		GENMASK(2, 0)
GENMASK            66 drivers/clk/imx/clk-sccg-pll.c #define SSCG_PLL_BYPASS_MASK		GENMASK(5, 4)
GENMASK            90 drivers/clk/ingenic/cgu.c 	m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
GENMASK            92 drivers/clk/ingenic/cgu.c 	n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
GENMASK            95 drivers/clk/ingenic/cgu.c 	od_enc &= GENMASK(pll_info->od_bits - 1, 0);
GENMASK           188 drivers/clk/ingenic/cgu.c 	ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
GENMASK           191 drivers/clk/ingenic/cgu.c 	ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
GENMASK           194 drivers/clk/ingenic/cgu.c 	ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
GENMASK           299 drivers/clk/ingenic/cgu.c 			 GENMASK(clk_info->mux.bits - 1, 0);
GENMASK           345 drivers/clk/ingenic/cgu.c 		mask = GENMASK(clk_info->mux.bits - 1, 0);
GENMASK           377 drivers/clk/ingenic/cgu.c 		      GENMASK(clk_info->div.bits - 1, 0);
GENMASK           487 drivers/clk/ingenic/cgu.c 		mask = GENMASK(clk_info->div.bits - 1, 0);
GENMASK            25 drivers/clk/loongson1/clk-loongson1b.c 	rate = 12 + (pll & GENMASK(5, 0));
GENMASK            66 drivers/clk/mediatek/clk-mux.c 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);
GENMASK            78 drivers/clk/mediatek/clk-mux.c 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);
GENMASK           100 drivers/clk/mediatek/clk-mux.c 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);
GENMASK            78 drivers/clk/mediatek/clk-pll.c 	if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
GENMASK           135 drivers/clk/mediatek/clk-pll.c 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
GENMASK           220 drivers/clk/mediatek/clk-pll.c 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);
GENMASK            13 drivers/clk/meson/parm.h #define PMASK(width)			GENMASK(width - 1, 0)
GENMASK            14 drivers/clk/meson/parm.h #define SETPMASK(width, shift)		GENMASK(shift + width - 1, shift)
GENMASK            41 drivers/clk/qcom/clk-alpha-pll.c # define PLL_POST_DIV_MASK(p)	GENMASK((p)->width, 0)
GENMASK           471 drivers/clk/qcom/clk-alpha-pll.c 			a = low & GENMASK(alpha_width - 1, 0);
GENMASK          1043 drivers/clk/qcom/clk-rcg2.c 	level &= GENMASK(4, 1);
GENMASK            22 drivers/clk/qcom/clk-regmap-mux.c 	unsigned int mask = GENMASK(mux->width - 1, 0);
GENMASK            40 drivers/clk/qcom/clk-regmap-mux.c 	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
GENMASK            19 drivers/clk/qcom/clk-spmi-pmic-div.c #define DIV_CTL1_DIV_FACTOR_MASK	GENMASK(2, 0)
GENMASK           202 drivers/clk/renesas/rcar-gen3-cpg.c 	zclk->mask = GENMASK(offset + 4, offset);
GENMASK            78 drivers/clk/rockchip/clk-ddr.c 	val &= GENMASK(ddrclk->mux_width - 1, 0);
GENMASK            24 drivers/clk/rockchip/clk-muxgrf.c 	unsigned int mask = GENMASK(mux->width - 1, 0);
GENMASK            38 drivers/clk/rockchip/clk-muxgrf.c 	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
GENMASK           205 drivers/clk/rockchip/clk.c 			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
GENMASK           250 drivers/clk/rockchip/clk.c 	div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
GENMASK           253 drivers/clk/rockchip/clk.c 	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
GENMASK            31 drivers/clk/socfpga/clk-gate-a10.c 		val &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK            24 drivers/clk/socfpga/clk-gate-s10.c 		val &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK            37 drivers/clk/socfpga/clk-gate-s10.c 	val &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK           100 drivers/clk/socfpga/clk-gate.c 		val &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK            30 drivers/clk/socfpga/clk-periph-a10.c 		div &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK            26 drivers/clk/socfpga/clk-periph-s10.c 	val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
GENMASK            28 drivers/clk/socfpga/clk-periph.c 			val &= GENMASK(socfpgaclk->width - 1, 0);
GENMASK            67 drivers/clk/sprd/div.c 	reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
GENMASK            56 drivers/clk/sprd/mux.c 	reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);
GENMASK            29 drivers/clk/sprd/pll.c 	GENMASK(pwidth(pll, member) + pshift(pll, member) - 1,	\
GENMASK          1448 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 	val &= ~GENMASK(25, 16);
GENMASK          1451 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 	val &= ~GENMASK(29, 26);
GENMASK          1464 drivers/clk/sunxi-ng/ccu-sun4i-a10.c 	val &= ~GENMASK(7, 6);
GENMASK           952 drivers/clk/sunxi-ng/ccu-sun50i-a64.c 	val &= ~GENMASK(19, 16);
GENMASK          1213 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 		val &= ~GENMASK(25, 24);
GENMASK          1222 drivers/clk/sunxi-ng/ccu-sun50i-h6.c 	val &= ~(GENMASK(21, 16) | BIT(0));
GENMASK          1001 drivers/clk/sunxi-ng/ccu-sun5i.c 	val &= ~GENMASK(29, 26);
GENMASK          1012 drivers/clk/sunxi-ng/ccu-sun5i.c 	val &= ~GENMASK(7, 6);
GENMASK          1242 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 	val &= ~GENMASK(19, 16);
GENMASK          1253 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 	val &= ~GENMASK(7, 6);
GENMASK          1256 drivers/clk/sunxi-ng/ccu-sun6i-a31.c 	val &= ~GENMASK(13, 12);
GENMASK           740 drivers/clk/sunxi-ng/ccu-sun8i-a23.c 	val &= ~GENMASK(19, 16);
GENMASK           800 drivers/clk/sunxi-ng/ccu-sun8i-a33.c 	val &= ~GENMASK(19, 16);
GENMASK           878 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 	val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,
GENMASK          1153 drivers/clk/sunxi-ng/ccu-sun8i-h3.c 	val &= ~GENMASK(19, 16);
GENMASK          1312 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 	val &= ~GENMASK(19, 16);
GENMASK          1322 drivers/clk/sunxi-ng/ccu-sun8i-r40.c 	val &= ~GENMASK(25, 20);
GENMASK           811 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c 	val &= ~GENMASK(19, 16);
GENMASK          1204 drivers/clk/sunxi-ng/ccu-sun9i-a80.c 	val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1,
GENMASK           538 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c 	val &= ~GENMASK(19, 16);
GENMASK           108 drivers/clk/sunxi-ng/ccu_div.c 	reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
GENMASK           210 drivers/clk/sunxi-ng/ccu_mp.c 	reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
GENMASK           211 drivers/clk/sunxi-ng/ccu_mp.c 	reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
GENMASK           135 drivers/clk/sunxi-ng/ccu_mult.c 	reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
GENMASK           191 drivers/clk/sunxi-ng/ccu_mux.c 	reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
GENMASK           137 drivers/clk/sunxi-ng/ccu_nk.c 	reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
GENMASK           138 drivers/clk/sunxi-ng/ccu_nk.c 	reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
GENMASK           167 drivers/clk/sunxi-ng/ccu_nkm.c 	reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift);
GENMASK           168 drivers/clk/sunxi-ng/ccu_nkm.c 	reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
GENMASK           169 drivers/clk/sunxi-ng/ccu_nkm.c 	reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
GENMASK           193 drivers/clk/sunxi-ng/ccu_nkmp.c 		n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,
GENMASK           196 drivers/clk/sunxi-ng/ccu_nkmp.c 		k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1,
GENMASK           199 drivers/clk/sunxi-ng/ccu_nkmp.c 		m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1,
GENMASK           202 drivers/clk/sunxi-ng/ccu_nkmp.c 		p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1,
GENMASK           186 drivers/clk/sunxi-ng/ccu_nm.c 		reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
GENMASK           218 drivers/clk/sunxi-ng/ccu_nm.c 	reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
GENMASK           219 drivers/clk/sunxi-ng/ccu_nm.c 	reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
GENMASK           112 drivers/clk/sunxi-ng/ccu_phase.c 	reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
GENMASK            22 drivers/clk/sunxi/clk-a10-pll2.c #define SUN4I_PLL2_PRE_DIV_MASK		GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
GENMASK            26 drivers/clk/sunxi/clk-a10-pll2.c #define SUN4I_PLL2_N_MASK		GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
GENMASK            30 drivers/clk/sunxi/clk-a10-pll2.c #define SUN4I_PLL2_POST_DIV_MASK	GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
GENMASK           270 drivers/clk/sunxi/clk-mod0.c 	value &= ~GENMASK(phase->offset + 3, phase->offset);
GENMASK            64 drivers/clk/sunxi/clk-sun6i-ar100.c 	.muxmask = GENMASK(1, 0),
GENMASK            28 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_MUX_MASK		GENMASK(17, 16)
GENMASK            33 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_DIV_MASK		GENMASK(5, 4)
GENMASK            39 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_PLL4_DIV_MASK	GENMASK(12, 8)
GENMASK            20 drivers/clk/tegra/clk-sdmmc-mux.c #define DIV_MASK GENMASK(7, 0)
GENMASK            22 drivers/clk/tegra/clk-sdmmc-mux.c #define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
GENMASK           615 drivers/clk/tegra/clk-tegra210.c 	writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
GENMASK          2847 drivers/clk/tegra/clk-tegra210.c 	reg &= ~GENMASK(20, 0);
GENMASK          3439 drivers/clk/tegra/clk-tegra210.c 		writel(GENMASK(26, 21) | BIT(7),
GENMASK          3459 drivers/clk/tegra/clk-tegra210.c 		writel(GENMASK(26, 22) | BIT(7),
GENMASK            86 drivers/clk/ti/clock.h #define CLKF_SOC_MASK			GENMASK(11, 8)
GENMASK            26 drivers/clk/x86/clk-pmc-atom.c #define PMC_MASK_CLK_CTL		GENMASK(1, 0)
GENMASK            86 drivers/clk/zynqmp/clkc.c #define CLK_TOPOLOGY_TYPE		GENMASK(3, 0)
GENMASK            87 drivers/clk/zynqmp/clkc.c #define CLK_TOPOLOGY_FLAGS		GENMASK(23, 8)
GENMASK            88 drivers/clk/zynqmp/clkc.c #define CLK_TOPOLOGY_TYPE_FLAGS		GENMASK(31, 24)
GENMASK            95 drivers/clk/zynqmp/clkc.c #define CLK_PARENTS_ID			GENMASK(15, 0)
GENMASK            96 drivers/clk/zynqmp/clkc.c #define CLK_PARENTS_FLAGS		GENMASK(31, 16)
GENMASK           103 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_NODE_INDEX		GENMASK(13, 0)
GENMASK           104 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_NODE_TYPE		GENMASK(19, 14)
GENMASK           105 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_NODE_SUBCLASS		GENMASK(25, 20)
GENMASK           106 drivers/clk/zynqmp/clkc.c #define CLK_ATTR_NODE_CLASS		GENMASK(31, 26)
GENMASK           351 drivers/clocksource/arm_arch_timer.c 	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
GENMASK           256 drivers/clocksource/ingenic-timer.c 	tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2);
GENMASK            25 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_PIV			GENMASK(19, 0)		/* Periodic Interval Value */
GENMASK            32 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_PICNT			GENMASK(31, 20)		/* Interval Counter */
GENMASK            33 drivers/clocksource/timer-atmel-pit.c #define AT91_PIT_CPIV			GENMASK(19, 0)		/* Inverval Value */
GENMASK            30 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_TIMMODE_MASK		GENMASK(3, 2)
GENMASK            31 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_RESET_MASK		GENMASK(1, 0)
GENMASK            33 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_UNRESET			GENMASK(1, 0)
GENMASK            35 drivers/clocksource/timer-davinci.c #define DAVINCI_TIMER_ENAMODE_MASK		GENMASK(1, 0)
GENMASK           169 drivers/clocksource/timer-imx-tpm.c 					GENMASK(counter_width - 1,
GENMASK           228 drivers/clocksource/timer-imx-tpm.c 	writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
GENMASK            35 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK		GENMASK(10, 8)
GENMASK            41 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK		GENMASK(7, 6)
GENMASK            42 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK		GENMASK(5, 4)
GENMASK            43 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK		GENMASK(3, 2)
GENMASK            44 drivers/clocksource/timer-meson6.c #define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK		GENMASK(1, 0)
GENMASK            35 drivers/clocksource/timer-npcm7xx.c #define NPCM7XX_Tx_OPER			GENMASK(28, 27)
GENMASK            32 drivers/clocksource/timer-sprd.c #define TIMER_VALUE_LO_MASK	GENMASK(31, 0)
GENMASK            17 drivers/cpufreq/qcom-cpufreq-hw.c #define LUT_SRC				GENMASK(31, 30)
GENMASK            18 drivers/cpufreq/qcom-cpufreq-hw.c #define LUT_L_VAL			GENMASK(7, 0)
GENMASK            19 drivers/cpufreq/qcom-cpufreq-hw.c #define LUT_CORE_COUNT			GENMASK(18, 16)
GENMASK            20 drivers/cpufreq/qcom-cpufreq-hw.c #define LUT_VOLT			GENMASK(11, 0)
GENMASK            24 drivers/crypto/atmel-sha-regs.h #define SHA_MR_ALGO_MASK		GENMASK(10, 8)
GENMASK            65 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE		GENMASK(4, 0)
GENMASK            66 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZE		GENMASK(9, 5)
GENMASK            72 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_DESCRQ_PUSH_LEN		GENMASK(5, 0)
GENMASK            73 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_DESCRQ_PUSH_ADDR		GENMASK(31, 6)
GENMASK            75 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_DESCRQ_STAT_LEVEL		GENMASK(3, 0)
GENMASK            76 drivers/crypto/axis/artpec6_crypto.c #define PDMA_OUT_DESCRQ_STAT_SIZE		GENMASK(7, 4)
GENMASK            80 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_BUF_CFG_DATA_BUF_SIZE		GENMASK(4, 0)
GENMASK            81 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE		GENMASK(9, 5)
GENMASK            82 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_BUF_CFG_STAT_BUF_SIZE		GENMASK(14, 10)
GENMASK            90 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_STATQ_PUSH_LEN			GENMASK(5, 0)
GENMASK            91 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_STATQ_PUSH_ADDR			GENMASK(31, 6)
GENMASK            93 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_DESCRQ_PUSH_LEN			GENMASK(5, 0)
GENMASK            94 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_DESCRQ_PUSH_ADDR		GENMASK(31, 6)
GENMASK            96 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_DESCRQ_STAT_LEVEL		GENMASK(3, 0)
GENMASK            97 drivers/crypto/axis/artpec6_crypto.c #define PDMA_IN_DESCRQ_STAT_SIZE		GENMASK(7, 4)
GENMASK           107 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_OPER		GENMASK(19, 16)
GENMASK           109 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_HASH_SEL_CTX	GENMASK(21, 20)
GENMASK           112 drivers/crypto/axis/artpec6_crypto.c #define A6_CRY_MD_CIPHER_LEN	GENMASK(21, 20)
GENMASK           117 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_OPER		GENMASK(11, 8)
GENMASK           119 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_HASH_SEL_CTX	GENMASK(13, 12)
GENMASK           122 drivers/crypto/axis/artpec6_crypto.c #define A7_CRY_MD_CIPHER_LEN	GENMASK(13, 12)
GENMASK            47 drivers/crypto/caam/dpseci_cmd.h 	GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1,	\
GENMASK           185 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
GENMASK           214 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
GENMASK            75 drivers/crypto/ccree/cc_driver.h #define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
GENMASK            28 drivers/crypto/ccree/cc_hw_queue_defs.h 	GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name))
GENMASK            39 drivers/crypto/ccree/cc_lli_defs.h #define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET)
GENMASK            40 drivers/crypto/ccree/cc_lli_defs.h #define LLI_HADDR_MASK GENMASK( \
GENMASK            52 drivers/crypto/hisilicon/qm.c #define QM_SQ_TYPE_MASK			GENMASK(3, 0)
GENMASK            70 drivers/crypto/hisilicon/qm.c #define QM_EQE_CQN_MASK			GENMASK(15, 0)
GENMASK           115 drivers/crypto/hisilicon/qm.c #define QM_SQC_VFT_BASE_MASK_V2		GENMASK(5, 0)
GENMASK           117 drivers/crypto/hisilicon/qm.c #define QM_SQC_VFT_NUM_MASK_v2		GENMASK(9, 0)
GENMASK           144 drivers/crypto/hisilicon/qm.c #define QM_SQE_DATA_ALIGN_MASK		GENMASK(6, 0)
GENMASK            14 drivers/crypto/hisilicon/qm.h #define AXUSER_CMD_TYPE			GENMASK(14, 12)
GENMASK            37 drivers/crypto/hisilicon/qm.h #define SQC_CACHE_WB_THRD		GENMASK(10, 5)
GENMASK            39 drivers/crypto/hisilicon/qm.h #define CQC_CACHE_WB_THRD		GENMASK(17, 12)
GENMASK            54 drivers/crypto/hisilicon/qm.h #define CURRENT_FUN_MASK		GENMASK(5, 0)
GENMASK            55 drivers/crypto/hisilicon/qm.h #define CURRENT_Q_MASK			GENMASK(31, 16)
GENMASK            90 drivers/crypto/hisilicon/sec/sec_drv.c #define   SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M		GENMASK(3, 0)
GENMASK            92 drivers/crypto/hisilicon/sec/sec_drv.c #define   SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_M		GENMASK(6, 4)
GENMASK           136 drivers/crypto/hisilicon/sec/sec_drv.c #define   SEC_Q_DEPTH_CFG_DEPTH_M			GENMASK(11, 0)
GENMASK           206 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_DEBUG_BD_INFO_SOFT_ERR_CHECK_M	GENMASK(22, 0)
GENMASK           208 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_DEBUG_BD_INFO_HARD_ERR_CHECK_M	GENMASK(9, 0)
GENMASK           211 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_DEBUG_BD_INFO_GET_ID_M		GENMASK(19, 0)
GENMASK           218 drivers/crypto/hisilicon/sec/sec_drv.c #define SEC_OUT_BD_INFO_Q_ID_M			GENMASK(11, 0)
GENMASK           938 drivers/crypto/hisilicon/sec/sec_drv.c 	writel_relaxed(GENMASK(info->num_saas - 1, 0),
GENMASK            23 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_T_LEN_M			GENMASK(4, 0)
GENMASK            26 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_C_WIDTH_M			GENMASK(6, 5)
GENMASK            35 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_C_MODE_M			GENMASK(9, 7)
GENMASK            46 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_DAT_SKIP_M			GENMASK(13, 12)
GENMASK            48 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_C_GRAN_SIZE_19_16_M		GENMASK(17, 14)
GENMASK            51 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_CIPHER_M			GENMASK(19, 18)
GENMASK            57 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_AUTH_M			GENMASK(21, 20)
GENMASK            66 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_HM_M				GENMASK(26, 25)
GENMASK            68 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_ICV_OR_SKEY_EN_M		GENMASK(28, 27)
GENMASK            72 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_FLAG_M			GENMASK(30, 29)
GENMASK            73 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W0_C_GRAN_SIZE_21_20_M		GENMASK(30, 29)
GENMASK            80 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_AUTH_GRAN_SIZE_M		GENMASK(21, 0)
GENMASK            86 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_A_ALG_M			GENMASK(28, 25)
GENMASK            99 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W1_C_ALG_M			GENMASK(31, 29)
GENMASK           107 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W2_C_GRAN_SIZE_15_0_M		GENMASK(15, 0)
GENMASK           109 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W2_GRAN_NUM_M			GENMASK(31, 16)
GENMASK           113 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W3_AUTH_LEN_OFFSET_M		GENMASK(9, 0)
GENMASK           115 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W3_CIPHER_LEN_OFFSET_M		GENMASK(19, 10)
GENMASK           117 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W3_MAC_LEN_M			GENMASK(24, 20)
GENMASK           119 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W3_A_KEY_LEN_M			GENMASK(29, 25)
GENMASK           121 drivers/crypto/hisilicon/sec/sec_drv.h #define SEC_BD_W3_C_KEY_LEN_M			GENMASK(31, 30)
GENMASK            14 drivers/crypto/hisilicon/zip/zip.h #define HZIP_BD_STATUS_M			GENMASK(7, 0)
GENMASK            16 drivers/crypto/hisilicon/zip/zip.h #define HZIP_IN_SGE_DATA_OFFSET_M		GENMASK(23, 0)
GENMASK            18 drivers/crypto/hisilicon/zip/zip.h #define HZIP_OUT_SGE_DATA_OFFSET_M		GENMASK(23, 0)
GENMASK            20 drivers/crypto/hisilicon/zip/zip.h #define HZIP_REQ_TYPE_M				GENMASK(7, 0)
GENMASK            23 drivers/crypto/hisilicon/zip/zip.h #define HZIP_BUF_TYPE_M				GENMASK(11, 8)
GENMASK           148 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(29, 0),
GENMASK           496 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(5, 0),
GENMASK           547 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(7, 0),
GENMASK           588 drivers/crypto/inside-secure/safexcel.c 	writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
GENMASK           627 drivers/crypto/inside-secure/safexcel.c 			       GENMASK(priv->config.rings - 1, 0),
GENMASK           638 drivers/crypto/inside-secure/safexcel.c 			GENMASK(15, 12)) != GENMASK(15, 12))
GENMASK           680 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(31, 0),
GENMASK           728 drivers/crypto/inside-secure/safexcel.c 		writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
GENMASK           732 drivers/crypto/inside-secure/safexcel.c 		writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
GENMASK           737 drivers/crypto/inside-secure/safexcel.c 	writel(GENMASK(30, 20), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
GENMASK          1257 drivers/crypto/inside-secure/safexcel.c 	priv->config.rings = min_t(u32, val & GENMASK(3, 0), max_rings);
GENMASK          1259 drivers/crypto/inside-secure/safexcel.c 	val = (val & GENMASK(27, 25)) >> 25;
GENMASK          1537 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(5, 0), EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_STAT);
GENMASK          1538 drivers/crypto/inside-secure/safexcel.c 		writel(GENMASK(7, 0), EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_STAT);
GENMASK          1737 drivers/crypto/inside-secure/safexcel.c 			writel(GENMASK(31, 0),
GENMASK           215 drivers/crypto/inside-secure/safexcel.h #define EIP197_xDR_PROC_xD_PKT_MASK		GENMASK(6, 0)
GENMASK           232 drivers/crypto/inside-secure/safexcel.h #define EIP197_N_PES_MASK			GENMASK(4, 0)
GENMASK           233 drivers/crypto/inside-secure/safexcel.h #define EIP97_N_PES_MASK			GENMASK(2, 0)
GENMASK           235 drivers/crypto/inside-secure/safexcel.h #define EIP197_HWDATAW_MASK			GENMASK(3, 0)
GENMASK           236 drivers/crypto/inside-secure/safexcel.h #define EIP97_HWDATAW_MASK			GENMASK(2, 0)
GENMASK           240 drivers/crypto/inside-secure/safexcel.h #define EIP197_CFSIZE_MASK			GENMASK(3, 0)
GENMASK           241 drivers/crypto/inside-secure/safexcel.h #define EIP97_CFSIZE_MASK			GENMASK(4, 0)
GENMASK           245 drivers/crypto/inside-secure/safexcel.h #define EIP197_RFSIZE_MASK			GENMASK(3, 0)
GENMASK           246 drivers/crypto/inside-secure/safexcel.h #define EIP97_RFSIZE_MASK			GENMASK(4, 0)
GENMASK           256 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE	GENMASK(15, 14)
GENMASK           289 drivers/crypto/inside-secure/safexcel.h #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)
GENMASK           406 drivers/crypto/inside-secure/safexcel.h #define EIP197_TRC_ENABLE_MASK			GENMASK(6, 4)
GENMASK           407 drivers/crypto/inside-secure/safexcel.h #define EIP197_CS_BANKSEL_MASK			GENMASK(14, 12)
GENMASK           502 drivers/crypto/inside-secure/safexcel.h #define EIP197_TOKEN_OPCODE_BYPASS		GENMASK(3, 0)
GENMASK           543 drivers/crypto/inside-secure/safexcel.h #define EIP197_OPTION_2_TOKEN_IV_CMD	GENMASK(11, 10)
GENMASK           544 drivers/crypto/inside-secure/safexcel.h #define EIP197_OPTION_4_TOKEN_IV_CMD	GENMASK(11, 9)
GENMASK           151 drivers/crypto/inside-secure/safexcel_ring.c 			(lower_32_bits(context) & GENMASK(31, 2)) >> 2;
GENMASK            21 drivers/crypto/marvell/cesa.h #define CESA_TDMA_DST_BURST			GENMASK(2, 0)
GENMASK            25 drivers/crypto/marvell/cesa.h #define CESA_TDMA_SRC_BURST			GENMASK(8, 6)
GENMASK            55 drivers/crypto/marvell/cesa.h #define CESA_SA_CFG_STOP_DIG_ERR		GENMASK(1, 0)
GENMASK            96 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_OP_MSK			GENMASK(1, 0)
GENMASK           103 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_MACM_MSK		GENMASK(6, 4)
GENMASK           107 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_CRYPTM_MSK		GENMASK(9, 8)
GENMASK           118 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_AES_LEN_MSK		GENMASK(25, 24)
GENMASK           123 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_CFG_FRAG_MSK		GENMASK(31, 30)
GENMASK           179 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_MAC_DATA_MSK		cpu_to_le32(GENMASK(15, 0))
GENMASK           182 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK		cpu_to_le32(GENMASK(31, 16))
GENMASK           188 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_MAC_DIGEST_MSK		cpu_to_le32(GENMASK(15, 0))
GENMASK           191 drivers/crypto/marvell/cesa.h #define CESA_SA_DESC_MAC_FRAG_LEN_MSK		cpu_to_le32(GENMASK(31, 16))
GENMASK           279 drivers/crypto/marvell/cesa.h #define CESA_TDMA_TYPE_MSK			GENMASK(26, 0)
GENMASK            63 drivers/crypto/mediatek/mtk-aes.c #define AES_FLAGS_CIPHER_MSK	GENMASK(4, 0)
GENMASK            17 drivers/crypto/mediatek/mtk-platform.c #define MTK_BURST_SIZE_MSK		GENMASK(7, 4)
GENMASK            26 drivers/crypto/mediatek/mtk-platform.c #define MTK_DFSE_IDLE			GENMASK(3, 0)
GENMASK            29 drivers/crypto/mediatek/mtk-platform.c #define MTK_DFSE_RING_ID(x)		(((x) >> 12) & GENMASK(3, 0))
GENMASK            39 drivers/crypto/mediatek/mtk-platform.c #define MTK_IN_TBUF_SIZE(x)		(((x) >> 4) & GENMASK(3, 0))
GENMASK            40 drivers/crypto/mediatek/mtk-platform.c #define MTK_IN_DBUF_SIZE(x)		(((x) >> 8) & GENMASK(3, 0))
GENMASK            41 drivers/crypto/mediatek/mtk-platform.c #define MTK_OUT_DBUF_SIZE(x)		(((x) >> 16) & GENMASK(3, 0))
GENMASK            42 drivers/crypto/mediatek/mtk-platform.c #define MTK_CMD_FIFO_SIZE(x)		(((x) >> 8) & GENMASK(3, 0))
GENMASK            43 drivers/crypto/mediatek/mtk-platform.c #define MTK_RES_FIFO_SIZE(x)		(((x) >> 12) & GENMASK(3, 0))
GENMASK            61 drivers/crypto/mediatek/mtk-platform.c #define MTK_HIA_DATA_WIDTH(x)		(((x) >> 25) & GENMASK(1, 0))
GENMASK            62 drivers/crypto/mediatek/mtk-platform.c #define MTK_HIA_DMA_LENGTH(x)		(((x) >> 20) & GENMASK(4, 0))
GENMASK            63 drivers/crypto/mediatek/mtk-platform.c #define MTK_CDR_STAT_CLR		GENMASK(4, 0)
GENMASK            64 drivers/crypto/mediatek/mtk-platform.c #define MTK_RDR_STAT_CLR		GENMASK(7, 0)
GENMASK            66 drivers/crypto/mediatek/mtk-platform.c #define MTK_AIC_INT_MSK			GENMASK(5, 0)
GENMASK            67 drivers/crypto/mediatek/mtk-platform.c #define MTK_AIC_VER_MSK			(GENMASK(15, 0) | GENMASK(27, 20))
GENMASK            70 drivers/crypto/mediatek/mtk-platform.c #define MTK_AIC_G_CLR			GENMASK(30, 20)
GENMASK            23 drivers/crypto/mediatek/mtk-sha.c #define SHA_DATA_LEN_MSK	cpu_to_le32(GENMASK(16, 0))
GENMASK            44 drivers/crypto/mediatek/mtk-sha.c #define SHA_TFM_DIGEST(x)	cpu_to_le32(((x) & GENMASK(3, 0)) << 24)
GENMASK            51 drivers/crypto/mediatek/mtk-sha.c #define SHA_FLAGS_ALGO_MSK	GENMASK(8, 4)
GENMASK            32 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CTR_WIDTH_MASK	GENMASK(8, 7)
GENMASK            36 drivers/crypto/omap-aes.h #define AES_REG_CTRL_CTR_WIDTH_128	GENMASK(8, 7)
GENMASK            37 drivers/crypto/omap-aes.h #define AES_REG_CTRL_GCM		GENMASK(17, 16)
GENMASK            40 drivers/crypto/omap-aes.h #define AES_REG_CTRL_KEY_SIZE		GENMASK(4, 3)
GENMASK            44 drivers/crypto/omap-aes.h #define AES_REG_CTRL_MASK		GENMASK(24, 2)
GENMASK            48 drivers/crypto/qce/common.h #define QCE_MODE_MASK			GENMASK(12, 8)
GENMASK           107 drivers/crypto/qce/regs-v5.h #define CORE_STEP_REV_MASK		GENMASK(15, 0)
GENMASK           109 drivers/crypto/qce/regs-v5.h #define CORE_MINOR_REV_MASK		GENMASK(23, 16)
GENMASK           111 drivers/crypto/qce/regs-v5.h #define CORE_MAJOR_REV_MASK		GENMASK(31, 24)
GENMASK           116 drivers/crypto/qce/regs-v5.h #define DOUT_SIZE_AVAIL_MASK		GENMASK(30, 26)
GENMASK           118 drivers/crypto/qce/regs-v5.h #define DIN_SIZE_AVAIL_MASK		GENMASK(25, 21)
GENMASK           127 drivers/crypto/qce/regs-v5.h #define CRYPTO_STATE_MASK		GENMASK(13, 10)
GENMASK           145 drivers/crypto/qce/regs-v5.h #define REQ_SIZE_MASK			GENMASK(20, 17)
GENMASK           164 drivers/crypto/qce/regs-v5.h #define MAX_QUEUED_REQ_MASK		GENMASK(24, 16)
GENMASK           170 drivers/crypto/qce/regs-v5.h #define IRQ_ENABLES_MASK		GENMASK(13, 10)
GENMASK           174 drivers/crypto/qce/regs-v5.h #define PIPE_SET_SELECT_MASK		GENMASK(8, 5)
GENMASK           192 drivers/crypto/qce/regs-v5.h #define AUTH_NONCE_NUM_WORDS_MASK	GENMASK(22, 20)
GENMASK           200 drivers/crypto/qce/regs-v5.h #define AUTH_POS_MASK			GENMASK(15, 14)
GENMASK           205 drivers/crypto/qce/regs-v5.h #define AUTH_SIZE_MASK			GENMASK(13, 9)
GENMASK           226 drivers/crypto/qce/regs-v5.h #define AUTH_MODE_MASK			GENMASK(8, 6)
GENMASK           233 drivers/crypto/qce/regs-v5.h #define AUTH_KEY_SIZE_MASK		GENMASK(5, 3)
GENMASK           238 drivers/crypto/qce/regs-v5.h #define AUTH_ALG_MASK			GENMASK(2, 0)
GENMASK           248 drivers/crypto/qce/regs-v5.h #define ENCR_XTS_DU_SIZE_MASK		GENMASK(19, 0)
GENMASK           272 drivers/crypto/qce/regs-v5.h #define CNTR_ALG_MASK			GENMASK(12, 11)
GENMASK           278 drivers/crypto/qce/regs-v5.h #define ENCR_MODE_MASK			GENMASK(9, 6)
GENMASK           286 drivers/crypto/qce/regs-v5.h #define ENCR_KEY_SZ_MASK		GENMASK(5, 3)
GENMASK           293 drivers/crypto/qce/regs-v5.h #define ENCR_ALG_MASK			GENMASK(2, 0)
GENMASK           317 drivers/crypto/qce/regs-v5.h #define BAM_PIPE_SETS_MASK		GENMASK(12, 9)
GENMASK           319 drivers/crypto/qce/regs-v5.h #define AXI_WR_BEATS_MASK		GENMASK(18, 13)
GENMASK           321 drivers/crypto/qce/regs-v5.h #define AXI_RD_BEATS_MASK		GENMASK(24, 19)
GENMASK            37 drivers/crypto/stm32/stm32-cryp.c #define FLG_MODE_MASK           GENMASK(15, 0)
GENMASK            73 drivers/crypto/stm32/stm32-hash.c #define HASH_STR_NBLW_MASK		GENMASK(4, 0)
GENMASK            87 drivers/crypto/stm32/stm32-hash.c #define HASH_FLAGS_ALGO_MASK		GENMASK(21, 18)
GENMASK           400 drivers/crypto/sunxi-ss/sun4i-ss-hash.c 			wb &= GENMASK((nbw * 8) - 1, 0);
GENMASK            63 drivers/dma/altera-msgdma.c #define MSGDMA_DESC_CTL_TR_ERR_IRQ	GENMASK(23, 16)
GENMASK           123 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_MASK			GENMASK(9, 0)
GENMASK           124 drivers/dma/altera-msgdma.c #define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ	GENMASK(8, 0)
GENMASK            57 drivers/dma/bcm-sba-raid.c #define SBA_TYPE_MASK					GENMASK(1, 0)
GENMASK            62 drivers/dma/bcm-sba-raid.c #define SBA_USER_DEF_MASK				GENMASK(15, 0)
GENMASK            64 drivers/dma/bcm-sba-raid.c #define SBA_R_MDATA_MASK				GENMASK(7, 0)
GENMASK            66 drivers/dma/bcm-sba-raid.c #define SBA_C_MDATA_MS_MASK				GENMASK(1, 0)
GENMASK            72 drivers/dma/bcm-sba-raid.c #define SBA_C_MDATA_MASK				GENMASK(7, 0)
GENMASK            74 drivers/dma/bcm-sba-raid.c #define SBA_C_MDATA_BNUMx_MASK				GENMASK(1, 0)
GENMASK            76 drivers/dma/bcm-sba-raid.c #define SBA_C_MDATA_DNUM_MASK				GENMASK(4, 0)
GENMASK            80 drivers/dma/bcm-sba-raid.c #define SBA_CMD_MASK					GENMASK(3, 0)
GENMASK           624 drivers/dma/dma-jz4780.c 		count += desc->desc[i].dtc & GENMASK(23, 0);
GENMASK           319 drivers/dma/dw-axi-dmac/dw-axi-dmac.h 	DWAXIDMAC_IRQ_ALL_ERR		= (GENMASK(21, 16) | GENMASK(14, 5)),
GENMASK           320 drivers/dma/dw-axi-dmac/dw-axi-dmac.h 	DWAXIDMAC_IRQ_ALL		= GENMASK(31, 0)
GENMASK            15 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_VIEWPORT_MASK				GENMASK(2, 0)
GENMASK            16 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_DONE_INT_MASK				GENMASK(7, 0)
GENMASK            17 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_ABORT_INT_MASK				GENMASK(23, 16)
GENMASK            18 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_WRITE_CH_COUNT_MASK			GENMASK(3, 0)
GENMASK            19 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_READ_CH_COUNT_MASK			GENMASK(19, 16)
GENMASK            20 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_CH_STATUS_MASK				GENMASK(6, 5)
GENMASK            21 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_DOORBELL_CH_MASK			GENMASK(2, 0)
GENMASK            22 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_LINKED_LIST_ERR_MASK			GENMASK(7, 0)
GENMASK            24 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_CH_ODD_MSI_DATA_MASK			GENMASK(31, 16)
GENMASK            25 drivers/dma/dw-edma/dw-edma-v0-regs.h #define EDMA_V0_CH_EVEN_MSI_DATA_MASK			GENMASK(15, 0)
GENMASK           171 drivers/dma/dw/regs.h #define DWC_CTLH_BLOCK_TS_MASK	GENMASK(11, 0)
GENMASK           233 drivers/dma/dw/regs.h #define IDMA32C_CTLH_BLOCK_TS_MASK	GENMASK(16, 0)
GENMASK            23 drivers/dma/fsl-edma-common.h #define EDMA_SEEI_SEEI(x)	((x) & GENMASK(4, 0))
GENMASK            24 drivers/dma/fsl-edma-common.h #define EDMA_CEEI_CEEI(x)	((x) & GENMASK(4, 0))
GENMASK            25 drivers/dma/fsl-edma-common.h #define EDMA_CINT_CINT(x)	((x) & GENMASK(4, 0))
GENMASK            26 drivers/dma/fsl-edma-common.h #define EDMA_CERR_CERR(x)	((x) & GENMASK(4, 0))
GENMASK            28 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DSIZE(x)		(((x) & GENMASK(2, 0)))
GENMASK            29 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_DMOD(x)		(((x) & GENMASK(4, 0)) << 3)
GENMASK            30 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_SSIZE(x)		(((x) & GENMASK(2, 0)) << 8)
GENMASK            31 drivers/dma/fsl-edma-common.h #define EDMA_TCD_ATTR_SMOD(x)		(((x) & GENMASK(4, 0)) << 11)
GENMASK            43 drivers/dma/fsl-edma-common.h #define EDMA_TCD_CITER_CITER(x)		((x) & GENMASK(14, 0))
GENMASK            44 drivers/dma/fsl-edma-common.h #define EDMA_TCD_BITER_BITER(x)		((x) & GENMASK(14, 0))
GENMASK            62 drivers/dma/fsl-qdma.c #define QDMA_SG_LEN_MASK		GENMASK(29, 0)
GENMASK            63 drivers/dma/fsl-qdma.c #define QDMA_CCDF_MASK			GENMASK(28, 20)
GENMASK            65 drivers/dma/fsl-qdma.c #define FSL_QDMA_DEDR_CLEAR		GENMASK(31, 0)
GENMASK            66 drivers/dma/fsl-qdma.c #define FSL_QDMA_BCQIDR_CLEAR		GENMASK(31, 0)
GENMASK            67 drivers/dma/fsl-qdma.c #define FSL_QDMA_DEIER_CLEAR		GENMASK(31, 0)
GENMASK            59 drivers/dma/hsu/hsu.h #define HSU_CH_DxTSR_MASK	GENMASK(15, 0)
GENMASK            15 drivers/dma/mcf-edma.c #define EDMA_MASK_CH(x)		((x) & GENMASK(5, 0))
GENMASK            63 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_MAX_LEN		GENMASK(27, 0)
GENMASK            64 drivers/dma/mediatek/mtk-cqdma.c #define MTK_CQDMA_ADDR_LIMIT		GENMASK(31, 0)
GENMASK            68 drivers/dma/owl-dma.c #define OWL_DMA_MODE_TS(x)			(((x) & GENMASK(5, 0)) << 0)
GENMASK            69 drivers/dma/owl-dma.c #define OWL_DMA_MODE_ST(x)			(((x) & GENMASK(1, 0)) << 8)
GENMASK            73 drivers/dma/owl-dma.c #define OWL_DMA_MODE_DT(x)			(((x) & GENMASK(1, 0)) << 10)
GENMASK            77 drivers/dma/owl-dma.c #define OWL_DMA_MODE_SAM(x)			(((x) & GENMASK(1, 0)) << 16)
GENMASK            81 drivers/dma/owl-dma.c #define OWL_DMA_MODE_DAM(x)			(((x) & GENMASK(1, 0)) << 18)
GENMASK            85 drivers/dma/owl-dma.c #define OWL_DMA_MODE_PW(x)			(((x) & GENMASK(2, 0)) << 20)
GENMASK            95 drivers/dma/owl-dma.c #define OWL_DMA_LLC_SAV(x)			(((x) & GENMASK(1, 0)) << 8)
GENMASK            99 drivers/dma/owl-dma.c #define OWL_DMA_LLC_DAV(x)			(((x) & GENMASK(1, 0)) << 10)
GENMASK            47 drivers/dma/qcom/hidma_ll.c #define HIDMA_EVRE_ERRINFO_MASK		GENMASK(3, 0)
GENMASK            48 drivers/dma/qcom/hidma_ll.c #define HIDMA_EVRE_CODE_MASK			GENMASK(3, 0)
GENMASK            50 drivers/dma/qcom/hidma_ll.c #define HIDMA_CH_CONTROL_MASK			GENMASK(7, 0)
GENMASK            51 drivers/dma/qcom/hidma_ll.c #define HIDMA_CH_STATE_MASK			GENMASK(7, 0)
GENMASK           619 drivers/dma/qcom/hidma_ll.c 	tre_local[HIDMA_TRE_CFG_IDX] &= ~GENMASK(7, 0);
GENMASK            31 drivers/dma/qcom/hidma_mgmt.c #define HIDMA_MAX_WR_XACTIONS_MASK	GENMASK(4, 0)
GENMASK            32 drivers/dma/qcom/hidma_mgmt.c #define HIDMA_MAX_RD_XACTIONS_MASK	GENMASK(4, 0)
GENMASK            33 drivers/dma/qcom/hidma_mgmt.c #define HIDMA_WEIGHT_MASK		GENMASK(6, 0)
GENMASK            34 drivers/dma/qcom/hidma_mgmt.c #define HIDMA_MAX_BUS_REQ_LEN_MASK	GENMASK(15, 0)
GENMASK            35 drivers/dma/qcom/hidma_mgmt.c #define HIDMA_CHRESET_TIMEOUT_MASK	GENMASK(19, 0)
GENMASK          1803 drivers/dma/sh/rcar-dmac.c 	dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
GENMASK            64 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_CHN_INT_MASK	GENMASK(23, 20)
GENMASK            72 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_DEST_CHN_MASK	GENMASK(13, 8)
GENMASK            74 drivers/dma/sprd-dma.c #define SPRD_DMA_GLB_SRC_CHN_MASK	GENMASK(5, 0)
GENMASK            77 drivers/dma/sprd-dma.c #define SPRD_DMA_INT_MASK		GENMASK(4, 0)
GENMASK           100 drivers/dma/sprd-dma.c #define SPRD_DMA_HIGH_ADDR_MASK		GENMASK(31, 28)
GENMASK           101 drivers/dma/sprd-dma.c #define SPRD_DMA_LOW_ADDR_MASK		GENMASK(31, 0)
GENMASK           120 drivers/dma/sprd-dma.c #define SPRD_DMA_REQ_MODE_MASK		GENMASK(1, 0)
GENMASK           124 drivers/dma/sprd-dma.c #define SPRD_DMA_FRG_LEN_MASK		GENMASK(16, 0)
GENMASK           127 drivers/dma/sprd-dma.c #define SPRD_DMA_BLK_LEN_MASK		GENMASK(16, 0)
GENMASK           130 drivers/dma/sprd-dma.c #define SPRD_DMA_TRSC_LEN_MASK		GENMASK(27, 0)
GENMASK           135 drivers/dma/sprd-dma.c #define SPRD_DMA_TRSF_STEP_MASK		GENMASK(15, 0)
GENMASK           138 drivers/dma/sprd-dma.c #define SPRD_DMA_LLIST_HIGH_MASK	GENMASK(31, 28)
GENMASK           142 drivers/dma/sprd-dma.c #define SPRD_DMA_CHN_MODE_MASK		GENMASK(7, 0)
GENMASK           143 drivers/dma/sprd-dma.c #define SPRD_DMA_TRG_MODE_MASK		GENMASK(7, 0)
GENMASK           144 drivers/dma/sprd-dma.c #define SPRD_DMA_INT_TYPE_MASK		GENMASK(7, 0)
GENMASK            63 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_REQ_MAP_MASK	GENMASK(4, 0)
GENMASK            67 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_SRC_MASK		GENMASK(6, 5)
GENMASK            70 drivers/dma/st_fdma.h #define FDMA_NODE_CTRL_DST_MASK		GENMASK(8, 7)
GENMASK           174 drivers/dma/st_fdma.h #define FDMA_CH_CMD_STA_MASK		GENMASK(1, 0)
GENMASK           179 drivers/dma/st_fdma.h #define FDMA_CH_CMD_ERR_MASK		GENMASK(4, 2)
GENMASK           183 drivers/dma/st_fdma.h #define FDMA_CH_CMD_DATA_MASK		GENMASK(31, 5)
GENMASK           219 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_NUM_OPS_MASK	GENMASK(31, 24)
GENMASK           228 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_OPCODE_MASK	GENMASK(7, 4)
GENMASK           236 drivers/dma/st_fdma.h #define FDMA_REQ_CTRL_HOLDOFF_MASK	GENMASK(2, 0)
GENMASK            49 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_MBURST_MASK	GENMASK(24, 23)
GENMASK            51 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PBURST_MASK	GENMASK(22, 21)
GENMASK            53 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PL_MASK		GENMASK(17, 16)
GENMASK            55 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_MSIZE_MASK	GENMASK(14, 13)
GENMASK            57 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_PSIZE_MASK	GENMASK(12, 11)
GENMASK            60 drivers/dma/stm32-dma.c #define STM32_DMA_SCR_DIR_MASK		GENMASK(7, 6)
GENMASK            96 drivers/dma/stm32-dma.c #define STM32_DMA_SFCR_FTH_MASK		GENMASK(1, 0)
GENMASK           136 drivers/dma/stm32-dma.c #define STM32_DMA_THRESHOLD_FTR_MASK	GENMASK(1, 0)
GENMASK            74 drivers/dma/stm32-mdma.c #define STM32_MDMA_CESR_TEA_MASK	GENMASK(6, 0)
GENMASK            82 drivers/dma/stm32-mdma.c #define STM32_MDMA_CCR_PL_MASK		GENMASK(7, 6)
GENMASK           101 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_TRGM_MSK	GENMASK(29, 28)
GENMASK           106 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_PAM_MASK	GENMASK(27, 26)
GENMASK           110 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_TLEN_MSK	GENMASK(24, 18)
GENMASK           115 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_LEN2_MSK	GENMASK(25, 18)
GENMASK           120 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_DBURST_MASK	GENMASK(17, 15)
GENMASK           123 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_SBURST_MASK	GENMASK(14, 12)
GENMASK           126 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_DINCOS_MASK	GENMASK(11, 10)
GENMASK           129 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_SINCOS_MASK	GENMASK(9, 8)
GENMASK           132 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_DSIZE_MASK	GENMASK(7, 6)
GENMASK           135 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_SSIZE_MASK	GENMASK(5, 4)
GENMASK           138 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_DINC_MASK	GENMASK(3, 2)
GENMASK           141 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTCR_SINC_MASK	GENMASK(1, 0)
GENMASK           153 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBNDTR_BRC_MK	GENMASK(31, 20)
GENMASK           161 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBNDTR_BNDT_MASK	GENMASK(16, 0)
GENMASK           173 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBRUR_DUV_MASK	GENMASK(31, 16)
GENMASK           176 drivers/dma/stm32-mdma.c #define STM32_MDMA_CBRUR_SUV_MASK	GENMASK(15, 0)
GENMASK           187 drivers/dma/stm32-mdma.c #define STM32_MDMA_CTBR_TSEL_MASK	GENMASK(7, 0)
GENMASK            70 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_FSYNCSRC_MASK		GENMASK(6, 5)
GENMASK            71 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_DELAY_MASK		GENMASK(31, 24)
GENMASK            72 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_FRAME_COUNT_MASK	GENMASK(23, 16)
GENMASK            73 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMACR_MASTER_MASK		GENMASK(11, 8)
GENMASK            91 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_DELAY_MASK		GENMASK(31, 24)
GENMASK            92 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_DMASR_FRAME_COUNT_MASK	GENMASK(23, 16)
GENMASK           102 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_PARK_PTR_WR_REF_MASK		GENMASK(12, 8)
GENMASK           104 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_PARK_PTR_RD_REF_MASK		GENMASK(4, 0)
GENMASK           167 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_CR_COALESCE_MAX	GENMASK(23, 16)
GENMASK           181 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_HSIZE_MASK	GENMASK(15, 0)
GENMASK           182 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_STRIDE_MASK	GENMASK(15, 0)
GENMASK           183 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_VSIZE_MASK	GENMASK(31, 19)
GENMASK           184 drivers/dma/xilinx/xilinx_dma.c #define XILINX_DMA_BD_TDEST_MASK	GENMASK(4, 0)
GENMASK          2648 drivers/dma/xilinx/xilinx_dma.c 	xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
GENMASK          2662 drivers/dma/xilinx/xilinx_dma.c 					GENMASK(len_width - 1, 0);
GENMASK            71 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_SRC_ISSUE		GENMASK(4, 0)
GENMASK            74 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_ARBURST		GENMASK(27, 26)
GENMASK            75 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_ARCACHE		GENMASK(25, 22)
GENMASK            77 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_ARQOS		GENMASK(21, 18)
GENMASK            79 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_ARLEN		GENMASK(17, 14)
GENMASK            81 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AWBURST		GENMASK(13, 12)
GENMASK            82 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AWCACHE		GENMASK(11, 8)
GENMASK            84 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AWQOS		GENMASK(7, 4)
GENMASK            86 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AWLEN		GENMASK(3, 0)
GENMASK            91 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXCACHE		GENMASK(7, 4)
GENMASK            93 drivers/dma/xilinx/zynqmp_dma.c #define ZYNQMP_DMA_AXQOS		GENMASK(3, 0)
GENMASK          2589 drivers/edac/amd64_edac.c 	return (m->ipid & GENMASK(31, 0)) >> 20;
GENMASK          2622 drivers/edac/amd64_edac.c 			err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
GENMASK            33 drivers/edac/aspeed_edac.c #define ASPEED_MCR_INTR_CTRL_CNT_REC   GENMASK(23, 16)
GENMASK            34 drivers/edac/aspeed_edac.c #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
GENMASK            25 drivers/edac/bluefield_edac.c #define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)
GENMASK            26 drivers/edac/bluefield_edac.c #define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)
GENMASK            42 drivers/edac/bluefield_edac.c #define MLXBF_SYNDROM__SYN GENMASK(25, 16)
GENMASK            45 drivers/edac/bluefield_edac.c #define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)
GENMASK            25 drivers/edac/qcom_edac.c #define LLCC_LB_CNT_MASK                GENMASK(31, 28)
GENMASK            49 drivers/edac/qcom_edac.c #define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
GENMASK            50 drivers/edac/qcom_edac.c #define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
GENMASK            53 drivers/edac/qcom_edac.c #define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
GENMASK            55 drivers/edac/qcom_edac.c #define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
GENMASK            60 drivers/edac/qcom_edac.c #define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
GENMASK            61 drivers/edac/qcom_edac.c #define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
GENMASK            30 drivers/edac/thunderx_edac.c #define THUNDERX_NODE		GENMASK(45, 44)
GENMASK           154 drivers/edac/thunderx_edac.c #define LMC_INT_ENA_ALL			GENMASK(5, 0)
GENMASK           842 drivers/edac/thunderx_edac.c #define OCX_COM_RX_LANE			GENMASK(23, 0)
GENMASK          1033 drivers/edac/thunderx_edac.c #define OCX_LNE_INT_ENA_ALL		(GENMASK(9, 8) | GENMASK(6, 0))
GENMASK          1034 drivers/edac/thunderx_edac.c #define OCX_COM_INT_ENA_ALL		(GENMASK(54, 50) | GENMASK(23, 0))
GENMASK          1035 drivers/edac/thunderx_edac.c #define OCX_COM_LINKX_INT_ENA_ALL	(GENMASK(13, 12) | \
GENMASK          1036 drivers/edac/thunderx_edac.c 					 GENMASK(9, 7) | GENMASK(5, 0))
GENMASK            42 drivers/edac/ti_edac.c #define SDRAM_TYPE_MASK			GENMASK(31, 29)
GENMASK            45 drivers/edac/ti_edac.c #define SDRAM_NARROW_MODE_MASK		GENMASK(15, 14)
GENMASK            47 drivers/edac/ti_edac.c #define SDRAM_K2_NARROW_MODE_MASK	GENMASK(13, 12)
GENMASK            49 drivers/edac/ti_edac.c #define SDRAM_ROWSIZE_MASK		GENMASK(9, 7)
GENMASK            51 drivers/edac/ti_edac.c #define SDRAM_IBANK_MASK		GENMASK(6, 4)
GENMASK            53 drivers/edac/ti_edac.c #define SDRAM_K2_IBANK_MASK		GENMASK(6, 5)
GENMASK            57 drivers/edac/ti_edac.c #define SDRAM_PAGESIZE_MASK		GENMASK(2, 0)
GENMASK            59 drivers/edac/ti_edac.c #define SDRAM_K2_PAGESIZE_MASK		GENMASK(1, 0)
GENMASK           142 drivers/extcon/extcon-axp288.c 	bits = val & GENMASK(ARRAY_SIZE(axp288_pwr_up_down_info) - 1, 0);
GENMASK            45 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_USBSRC_STS_MASK		GENMASK(1, 0)
GENMASK            49 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_USBSRC_TYPE_MASK		GENMASK(5, 2)
GENMASK            74 drivers/extcon/extcon-intel-cht-wc.c #define CHT_WC_PWRSRC_USBID_MASK	GENMASK(4, 3)
GENMASK            27 drivers/extcon/extcon-intel-mrfld.c #define BCOVE_USBIDSTS_RARBRC_MASK	GENMASK(2, 1)
GENMASK            20 drivers/firmware/arm_scmi/common.h #define PROTOCOL_REV_MINOR_MASK	GENMASK(15, 0)
GENMASK            21 drivers/firmware/arm_scmi/common.h #define PROTOCOL_REV_MAJOR_MASK	GENMASK(31, 16)
GENMASK            32 drivers/firmware/arm_scmi/driver.c #define MSG_ID_MASK		GENMASK(7, 0)
GENMASK            34 drivers/firmware/arm_scmi/driver.c #define MSG_TYPE_MASK		GENMASK(9, 8)
GENMASK            39 drivers/firmware/arm_scmi/driver.c #define MSG_PROTOCOL_ID_MASK	GENMASK(17, 10)
GENMASK            41 drivers/firmware/arm_scmi/driver.c #define MSG_TOKEN_ID_MASK	GENMASK(27, 18)
GENMASK           103 drivers/firmware/arm_scmi/perf.c #define DOORBELL_REG_WIDTH(x)		FIELD_GET(GENMASK(2, 1), (x))
GENMASK            38 drivers/firmware/arm_scmi/sensors.c #define SENSOR_SCALE_EXTEND	GENMASK(7, 5)
GENMASK            38 drivers/firmware/arm_scpi.c #define CMD_ID_MASK		GENMASK(6, 0)
GENMASK            39 drivers/firmware/arm_scpi.c #define CMD_TOKEN_ID_MASK	GENMASK(15, 8)
GENMASK            40 drivers/firmware/arm_scpi.c #define CMD_DATA_SIZE_MASK	GENMASK(24, 16)
GENMASK            41 drivers/firmware/arm_scpi.c #define CMD_LEGACY_DATA_SIZE_MASK	GENMASK(28, 20)
GENMASK            58 drivers/firmware/arm_scpi.c #define PROTO_REV_MAJOR_MASK	GENMASK(31, 16)
GENMASK            59 drivers/firmware/arm_scpi.c #define PROTO_REV_MINOR_MASK	GENMASK(15, 0)
GENMASK            61 drivers/firmware/arm_scpi.c #define FW_REV_MAJOR_MASK	GENMASK(31, 24)
GENMASK            62 drivers/firmware/arm_scpi.c #define FW_REV_MINOR_MASK	GENMASK(23, 16)
GENMASK            63 drivers/firmware/arm_scpi.c #define FW_REV_PATCH_MASK	GENMASK(15, 0)
GENMASK           567 drivers/firmware/ti_sci.h #define MSG_RM_RESOURCE_TYPE_MASK	GENMASK(9, 0)
GENMASK           568 drivers/firmware/ti_sci.h #define MSG_RM_RESOURCE_SUBTYPE_MASK	GENMASK(5, 0)
GENMASK            40 drivers/fpga/altera-cvp.c #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK	GENMASK(15, 8)
GENMASK            46 drivers/fpga/altera-cvp.c #define VSE_CVP_PROG_CTRL_MASK		GENMASK(1, 0)
GENMASK            96 drivers/fpga/zynq-fpga.c #define DMA_INVALID_ADDRESS		GENMASK(31, 0)
GENMASK            30 drivers/fsi/fsi-core.c #define FSI_SLAVE_CONF_NEXT_MASK	GENMASK(31, 31)
GENMASK            31 drivers/fsi/fsi-core.c #define FSI_SLAVE_CONF_SLOTS_MASK	GENMASK(23, 16)
GENMASK            33 drivers/fsi/fsi-core.c #define FSI_SLAVE_CONF_VERSION_MASK	GENMASK(15, 12)
GENMASK            35 drivers/fsi/fsi-core.c #define FSI_SLAVE_CONF_TYPE_MASK	GENMASK(11, 4)
GENMASK            38 drivers/fsi/fsi-core.c #define FSI_SLAVE_CONF_CRC_MASK		GENMASK(3, 0)
GENMASK           189 drivers/gpio/gpio-104-dio-48e.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK            95 drivers/gpio/gpio-104-idi-48.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK            91 drivers/gpio/gpio-104-idio-16.c 	if (*mask & GENMASK(23, 16))
GENMASK            93 drivers/gpio/gpio-104-idio-16.c 	if (*mask & GENMASK(31, 24))
GENMASK           178 drivers/gpio/gpio-cadence.c 	iowrite32(GENMASK(num_gpios - 1, 0),
GENMASK           251 drivers/gpio/gpio-cadence.c 	iowrite32(GENMASK(num_gpios - 1, 0),
GENMASK            46 drivers/gpio/gpio-creg-snps.c 	reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);
GENMASK            68 drivers/gpio/gpio-creg-snps.c 	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])
GENMASK            72 drivers/gpio/gpio-creg-snps.c 	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])
GENMASK           563 drivers/gpio/gpio-davinci.c 		binten = GENMASK(pdata->gpio_unbanked / 16, 0);
GENMASK            58 drivers/gpio/gpio-eic-sprd.c #define SPRD_EIC_DATA_MASK		GENMASK(7, 0)
GENMASK            60 drivers/gpio/gpio-eic-sprd.c #define SPRD_EIC_DBNC_MASK		GENMASK(11, 0)
GENMASK           178 drivers/gpio/gpio-gpio-mm.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK            42 drivers/gpio/gpio-ixp4xx.c #define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)
GENMASK            23 drivers/gpio/gpio-moxtet.c 		.in_mask = GENMASK(2, 0),
GENMASK            24 drivers/gpio/gpio-moxtet.c 		.out_mask = GENMASK(5, 4),
GENMASK            32 drivers/gpio/gpio-pca953x.c #define REG_ADDR_MASK		GENMASK(5, 0)
GENMASK            59 drivers/gpio/gpio-pca953x.c #define PCA_GPIO_MASK		GENMASK(7, 0)
GENMASK            61 drivers/gpio/gpio-pca953x.c #define PCAL_GPIO_MASK		GENMASK(4, 0)
GENMASK            62 drivers/gpio/gpio-pca953x.c #define PCAL_PINCTRL_MASK	GENMASK(6, 5)
GENMASK            69 drivers/gpio/gpio-pca953x.c #define PCA_TYPE_MASK		GENMASK(15, 12)
GENMASK           109 drivers/gpio/gpio-pci-idio-16.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK           207 drivers/gpio/gpio-pcie-idio-24.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK           301 drivers/gpio/gpio-pcie-idio-24.c 	const unsigned long port_mask = GENMASK(gpio_reg_size, 0);
GENMASK            32 drivers/gpio/gpio-pmic-eic-sprd.c #define SPRD_PMIC_EIC_DATA_MASK		GENMASK(15, 0)
GENMASK            34 drivers/gpio/gpio-pmic-eic-sprd.c #define SPRD_PMIC_EIC_DBNC_MASK		GENMASK(11, 0)
GENMASK           320 drivers/gpio/gpio-rcar.c 	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
GENMASK            32 drivers/gpio/gpio-sprd.c #define SPRD_GPIO_BANK_MASK	GENMASK(15, 0)
GENMASK            30 drivers/gpio/gpio-thunderx.c #define  GPIO_BIT_CFG_FIL_MASK		GENMASK(11, 4)
GENMASK            34 drivers/gpio/gpio-thunderx.c #define  GPIO_BIT_CFG_PIN_SEL_MASK	GENMASK(25, 16)
GENMASK            19 drivers/gpio/gpio-uniphier.c 				GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)
GENMASK            46 drivers/gpio/gpio-wcove.c #define GPIO_IRQ0_MASK		GENMASK(6, 0)
GENMASK            47 drivers/gpio/gpio-wcove.c #define GPIO_IRQ1_MASK		GENMASK(5, 0)
GENMASK            32 drivers/gpio/gpio-winbond.c #define WB_SIO_CHIP_ID_W83627UHG_MASK	GENMASK(15, 4)
GENMASK            59 drivers/gpio/gpio-winbond.c #define WB_SIO_REG_G1MF_FS_MASK	GENMASK(1, 0)
GENMASK           616 drivers/gpio/gpio-winbond.c 	gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,
GENMASK           136 drivers/gpio/gpio-ws16c48.c 	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
GENMASK            24 drivers/gpio/sgpio-aspeed.c #define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
GENMASK            25 drivers/gpio/sgpio-aspeed.c #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
GENMASK            53 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
GENMASK            46 drivers/gpu/drm/arm/malidp_drv.c 	const u32 gamma_write_mask = GENMASK(18, 16);
GENMASK            68 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_COLOR_MASK		GENMASK(9, 7)
GENMASK            77 drivers/gpu/drm/aspeed/aspeed_gfx.h #define CRT_CTRL_VBLANK_LINE_MASK	GENMASK(20, 31)
GENMASK           242 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c #define ATMEL_HLCDC_OUTPUT_MODE_MASK	GENMASK(3, 0)
GENMASK            45 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK		GENMASK(5, 4)
GENMASK           110 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h 	GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
GENMASK            30 drivers/gpu/drm/bridge/cdns-dsi.c #define SP_HS_FIFO_DEPTH(x)		(((x) & GENMASK(30, 26)) >> 26)
GENMASK            31 drivers/gpu/drm/bridge/cdns-dsi.c #define SP_LP_FIFO_DEPTH(x)		(((x) & GENMASK(25, 21)) >> 21)
GENMASK            32 drivers/gpu/drm/bridge/cdns-dsi.c #define VRS_FIFO_DEPTH(x)		(((x) & GENMASK(20, 16)) >> 16)
GENMASK            33 drivers/gpu/drm/bridge/cdns-dsi.c #define DIRCMD_FIFO_DEPTH(x)		(((x) & GENMASK(15, 13)) >> 13)
GENMASK            38 drivers/gpu/drm/bridge/cdns-dsi.c #define INTERNAL_DATAPATH_SIZE		((x) & GENMASK(11, 10))
GENMASK            39 drivers/gpu/drm/bridge/cdns-dsi.c #define NUM_IFACE(x)			((((x) & GENMASK(9, 8)) >> 8) + 1)
GENMASK            40 drivers/gpu/drm/bridge/cdns-dsi.c #define MAX_LANE_NB(x)			(((x) & GENMASK(7, 6)) >> 6)
GENMASK            41 drivers/gpu/drm/bridge/cdns-dsi.c #define RX_FIFO_DEPTH(x)		((x) & GENMASK(5, 0))
GENMASK            57 drivers/gpu/drm/bridge/cdns-dsi.c #define IF_VID_SELECT_MASK		GENMASK(3, 2)
GENMASK            85 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_D_RSTB(x)			GENMASK(15 + (x), 16)
GENMASK            89 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_D_PDN(x)			GENMASK(3 + (x), 4)
GENMASK            90 drivers/gpu/drm/bridge/cdns-dsi.c #define DPHY_ALL_D_PDN			GENMASK(7, 4)
GENMASK            96 drivers/gpu/drm/bridge/cdns-dsi.c #define HSTX_TIMEOUT_MAX		GENMASK(17, 0)
GENMASK            98 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_DIV_MAX			GENMASK(3, 0)
GENMASK           148 drivers/gpu/drm/bridge/cdns-dsi.c #define PPI_D_RX_ULPS_ESC(x)		(((x) & GENMASK(15, 12)) >> 12)
GENMASK           155 drivers/gpu/drm/bridge/cdns-dsi.c 	(((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
GENMASK           157 drivers/gpu/drm/bridge/cdns-dsi.c #define CLK_LANE_STATE(val)		((val) & GENMASK(1, 0))
GENMASK           212 drivers/gpu/drm/bridge/cdns-dsi.c #define RCVD_TRIGGER_VAL(val)		(((val) & GENMASK(14, 11)) >> 11)
GENMASK           235 drivers/gpu/drm/bridge/cdns-dsi.c #define RD_VCHAN_ID(val)		(((val) >> 16) & GENMASK(1, 0))
GENMASK           236 drivers/gpu/drm/bridge/cdns-dsi.c #define RD_SIZE(val)			((val) & GENMASK(15, 0))
GENMASK           268 drivers/gpu/drm/bridge/cdns-dsi.c #define VID_PIXEL_MODE_MASK		GENMASK(17, 14)
GENMASK           324 drivers/gpu/drm/bridge/cdns-dsi.c #define LINE_VAL(val)			(((val) & GENMASK(14, 2)) >> 2)
GENMASK           325 drivers/gpu/drm/bridge/cdns-dsi.c #define LINE_POS(val)			((val) & GENMASK(1, 0))
GENMASK           328 drivers/gpu/drm/bridge/cdns-dsi.c #define HORIZ_VAL(val)			(((val) & GENMASK(17, 3)) >> 3)
GENMASK           329 drivers/gpu/drm/bridge/cdns-dsi.c #define HORIZ_POS(val)			((val) & GENMASK(2, 0))
GENMASK           357 drivers/gpu/drm/bridge/cdns-dsi.c #define TVG_MODE_MASK			GENMASK(4, 3)
GENMASK           361 drivers/gpu/drm/bridge/cdns-dsi.c #define TVG_STOPMODE_MASK		GENMASK(2, 1)
GENMASK           403 drivers/gpu/drm/bridge/cdns-dsi.c #define DPI_CFG_FIFO_LEVEL(x)		((x) & GENMASK(15, 0))
GENMASK           410 drivers/gpu/drm/bridge/cdns-dsi.c #define REV_VENDOR_ID(x)		(((x) & GENMASK(31, 20)) >> 20)
GENMASK           411 drivers/gpu/drm/bridge/cdns-dsi.c #define REV_PRODUCT_ID(x)		(((x) & GENMASK(19, 12)) >> 12)
GENMASK           412 drivers/gpu/drm/bridge/cdns-dsi.c #define REV_HW(x)			(((x) & GENMASK(11, 8)) >> 8)
GENMASK           413 drivers/gpu/drm/bridge/cdns-dsi.c #define REV_MAJOR(x)			(((x) & GENMASK(7, 4)) >> 4)
GENMASK           414 drivers/gpu/drm/bridge/cdns-dsi.c #define REV_MINOR(x)			((x) & GENMASK(3, 0))
GENMASK            68 drivers/gpu/drm/bridge/sii902x.c #define SII902X_AVI_POWER_STATE_MSK		GENMASK(1, 0)
GENMASK            35 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c #define VERSION				GENMASK(31, 8)
GENMASK            51 drivers/gpu/drm/bridge/tc358767.c #define VSDELAY			GENMASK(31, 20)
GENMASK            59 drivers/gpu/drm/bridge/tc358767.c #define HPW			GENMASK(8, 0)
GENMASK            60 drivers/gpu/drm/bridge/tc358767.c #define HBPR			GENMASK(24, 16)
GENMASK            62 drivers/gpu/drm/bridge/tc358767.c #define HDISPR			GENMASK(10, 0)
GENMASK            63 drivers/gpu/drm/bridge/tc358767.c #define HFPR			GENMASK(24, 16)
GENMASK            65 drivers/gpu/drm/bridge/tc358767.c #define VSPR			GENMASK(7, 0)
GENMASK            66 drivers/gpu/drm/bridge/tc358767.c #define VBPR			GENMASK(23, 16)
GENMASK            68 drivers/gpu/drm/bridge/tc358767.c #define VFPR			GENMASK(23, 16)
GENMASK            69 drivers/gpu/drm/bridge/tc358767.c #define VDISPR			GENMASK(10, 0)
GENMASK           119 drivers/gpu/drm/bridge/tc358767.c #define VID_SYNC_DLY		GENMASK(15, 0)
GENMASK           120 drivers/gpu/drm/bridge/tc358767.c #define THRESH_DLY		GENMASK(31, 16)
GENMASK           123 drivers/gpu/drm/bridge/tc358767.c #define H_TOTAL			GENMASK(15, 0)
GENMASK           124 drivers/gpu/drm/bridge/tc358767.c #define V_TOTAL			GENMASK(31, 16)
GENMASK           126 drivers/gpu/drm/bridge/tc358767.c #define H_START			GENMASK(15, 0)
GENMASK           127 drivers/gpu/drm/bridge/tc358767.c #define V_START			GENMASK(31, 16)
GENMASK           129 drivers/gpu/drm/bridge/tc358767.c #define H_ACT			GENMASK(15, 0)
GENMASK           130 drivers/gpu/drm/bridge/tc358767.c #define V_ACT			GENMASK(31, 16)
GENMASK           133 drivers/gpu/drm/bridge/tc358767.c #define VS_WIDTH		GENMASK(30, 16)
GENMASK           134 drivers/gpu/drm/bridge/tc358767.c #define HS_WIDTH		GENMASK(14, 0)
GENMASK           139 drivers/gpu/drm/bridge/tc358767.c #define MAX_TU_SYMBOL		GENMASK(28, 23)
GENMASK           140 drivers/gpu/drm/bridge/tc358767.c #define TU_SIZE			GENMASK(21, 16)
GENMASK           146 drivers/gpu/drm/bridge/tc358767.c #define DP0_AUXCFG0_BSIZE	GENMASK(11, 8)
GENMASK           155 drivers/gpu/drm/bridge/tc358767.c #define AUX_BYTES		GENMASK(15, 8)
GENMASK           156 drivers/gpu/drm/bridge/tc358767.c #define AUX_STATUS		GENMASK(7, 4)
GENMASK           219 drivers/gpu/drm/bridge/tc358767.c #define COLOR_R			GENMASK(31, 24)
GENMASK           220 drivers/gpu/drm/bridge/tc358767.c #define COLOR_G			GENMASK(23, 16)
GENMASK           221 drivers/gpu/drm/bridge/tc358767.c #define COLOR_B			GENMASK(15, 8)
GENMASK           223 drivers/gpu/drm/bridge/tc358767.c #define COLOR_BAR_MODE		GENMASK(1, 0)
GENMASK            30 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define  REFCLK_FREQ_MASK			GENMASK(3, 1)
GENMASK            35 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define  CHA_DSI_LANES_MASK			GENMASK(4, 3)
GENMASK            65 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define  DP_NUM_LANES_MASK			GENMASK(5, 4)
GENMASK            68 drivers/gpu/drm/bridge/ti-sn65dsi86.c #define  DP_DATARATE_MASK			GENMASK(7, 5)
GENMASK           534 drivers/gpu/drm/drm_client_modeset.c 	mask = GENMASK(count - 1, 0);
GENMASK           120 drivers/gpu/drm/exynos/regs-decon5433.h #define SHADOWCON_PROTECT_MASK		GENMASK(14, 10)
GENMASK          2037 drivers/gpu/drm/i915/gem/i915_gem_context.c 	BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) !=
GENMASK           408 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
GENMASK           171 drivers/gpu/drm/i915/gt/intel_lrc.c #define GEN12_CSB_SW_CTX_ID_MASK		GENMASK(25, 15)
GENMASK           164 drivers/gpu/drm/i915/gvt/cfg_space.c 	start &= ~GENMASK(3, 0);
GENMASK           378 drivers/gpu/drm/i915/gvt/cmd_parser.c 	FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
GENMASK           950 drivers/gpu/drm/i915/gvt/cmd_parser.c 	(cmd_val(s, i) & GENMASK(22, 2))
GENMASK           953 drivers/gpu/drm/i915/gvt/cmd_parser.c 	(cmd_val(s, i) & GENMASK(22, 18))
GENMASK           956 drivers/gpu/drm/i915/gvt/cmd_parser.c 	(cmd_val(s, i) & GENMASK(31, 2))
GENMASK           959 drivers/gpu/drm/i915/gvt/cmd_parser.c 	(cmd_val(s, i) & GENMASK(15, 0))
GENMASK          1131 drivers/gpu/drm/i915/gvt/cmd_parser.c 				gma = cmd_val(s, 2) & GENMASK(31, 3);
GENMASK          1230 drivers/gpu/drm/i915/gvt/cmd_parser.c 	v = (dword0 & GENMASK(21, 19)) >> 19;
GENMASK          1237 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
GENMASK          1239 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
GENMASK          1240 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
GENMASK          1265 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
GENMASK          1304 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
GENMASK          1305 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->tile_val = (dword1 & GENMASK(2, 0));
GENMASK          1306 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
GENMASK          1307 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
GENMASK          1326 drivers/gpu/drm/i915/gvt/cmd_parser.c 		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
GENMASK          1328 drivers/gpu/drm/i915/gvt/cmd_parser.c 				GENMASK(12, 10)) >> 10;
GENMASK          1331 drivers/gpu/drm/i915/gvt/cmd_parser.c 				GENMASK(15, 6)) >> 6;
GENMASK          1351 drivers/gpu/drm/i915/gvt/cmd_parser.c 	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
GENMASK          1354 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
GENMASK          1356 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
GENMASK          1359 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
GENMASK          1361 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
GENMASK          1552 drivers/gpu/drm/i915/gvt/cmd_parser.c 	gma = cmd_val(s, 2) & GENMASK(31, 2);
GENMASK          1555 drivers/gpu/drm/i915/gvt/cmd_parser.c 		gma_low = cmd_val(s, 1) & GENMASK(31, 2);
GENMASK          1556 drivers/gpu/drm/i915/gvt/cmd_parser.c 		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
GENMASK          1591 drivers/gpu/drm/i915/gvt/cmd_parser.c 	int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
GENMASK          1608 drivers/gpu/drm/i915/gvt/cmd_parser.c 	gma = cmd_val(s, 1) & GENMASK(31, 2);
GENMASK          1610 drivers/gpu/drm/i915/gvt/cmd_parser.c 		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
GENMASK          1658 drivers/gpu/drm/i915/gvt/cmd_parser.c 		gma = cmd_val(s, 1) & GENMASK(31, 3);
GENMASK          1660 drivers/gpu/drm/i915/gvt/cmd_parser.c 			gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
GENMASK           472 drivers/gpu/drm/i915/gvt/gvt.h 		*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
GENMASK           158 drivers/gpu/drm/i915/gvt/handlers.c 	offset &= ~GENMASK(11, 0);
GENMASK           273 drivers/gpu/drm/i915/gvt/handlers.c 	(((new) & GENMASK(31, 16)) \
GENMASK           274 drivers/gpu/drm/i915/gvt/handlers.c 	 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
GENMASK           307 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
GENMASK           697 drivers/gpu/drm/i915/gvt/handlers.c 	data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
GENMASK           712 drivers/gpu/drm/i915/gvt/handlers.c 	sticky_mask = GENMASK(27, 26) | (1 << 24);
GENMASK           131 drivers/gpu/drm/i915/gvt/mpt.h 	if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
GENMASK           491 drivers/gpu/drm/i915/i915_cmd_parser.c #define MI_BB_START_OPERAND_MASK   GENMASK(SMI-1, 0)
GENMASK          1832 drivers/gpu/drm/i915/i915_drv.h 	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
GENMASK          1848 drivers/gpu/drm/i915/i915_drv.h 	GENMASK((e) - 1, (s) - 1))
GENMASK          2073 drivers/gpu/drm/i915/i915_drv.h 	 GENMASK(first__ + count__ - 1, first__)) >> first__;		\
GENMASK           142 drivers/gpu/drm/i915/i915_reg.h 	((u32)(GENMASK(__high, __low) +					\
GENMASK          7478 drivers/gpu/drm/i915/i915_reg.h #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
GENMASK          7479 drivers/gpu/drm/i915/i915_reg.h #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
GENMASK           484 drivers/gpu/drm/i915/intel_device_info.c 	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
GENMASK            29 drivers/gpu/drm/mediatek/mtk_disp_rdma.c #define RDMA_MATRIX_INT_MTX_SEL				GENMASK(23, 20)
GENMASK            89 drivers/gpu/drm/meson/meson_crtc.c 	writel(FIELD_PREP(GENMASK(11, 0), 2303),
GENMASK           129 drivers/gpu/drm/meson/meson_crtc.c 	writel(FIELD_PREP(GENMASK(11, 0), 2303),
GENMASK            27 drivers/gpu/drm/meson/meson_overlay.c #define VD_HOLD_LINES(lines)		FIELD_PREP(GENMASK(24, 19), lines)
GENMASK            29 drivers/gpu/drm/meson/meson_overlay.c #define VD_BYTES_PER_PIXEL(val)		FIELD_PREP(GENMASK(15, 14), val)
GENMASK            36 drivers/gpu/drm/meson/meson_overlay.c #define CANVAS_ADDR2(addr)		FIELD_PREP(GENMASK(23, 16), addr)
GENMASK            37 drivers/gpu/drm/meson/meson_overlay.c #define CANVAS_ADDR1(addr)		FIELD_PREP(GENMASK(15, 8), addr)
GENMASK            38 drivers/gpu/drm/meson/meson_overlay.c #define CANVAS_ADDR0(addr)		FIELD_PREP(GENMASK(7, 0), addr)
GENMASK            41 drivers/gpu/drm/meson/meson_overlay.c #define VD_X_START(value)		FIELD_PREP(GENMASK(14, 0), value)
GENMASK            42 drivers/gpu/drm/meson/meson_overlay.c #define VD_X_END(value)			FIELD_PREP(GENMASK(30, 16), value)
GENMASK            45 drivers/gpu/drm/meson/meson_overlay.c #define VD_Y_START(value)		FIELD_PREP(GENMASK(12, 0), value)
GENMASK            46 drivers/gpu/drm/meson/meson_overlay.c #define VD_Y_END(value)			FIELD_PREP(GENMASK(28, 16), value)
GENMASK            49 drivers/gpu/drm/meson/meson_overlay.c #define VD_COLOR_MAP(value)		FIELD_PREP(GENMASK(1, 0), value)
GENMASK            52 drivers/gpu/drm/meson/meson_overlay.c #define VD_HORZ_Y_C_RATIO(value)	FIELD_PREP(GENMASK(22, 21), value)
GENMASK            55 drivers/gpu/drm/meson/meson_overlay.c #define VD_VERT_INITIAL_PHASE(value)	FIELD_PREP(GENMASK(11, 8), value)
GENMASK            56 drivers/gpu/drm/meson/meson_overlay.c #define VD_VERT_PHASE_STEP(value)	FIELD_PREP(GENMASK(7, 1), value)
GENMASK            60 drivers/gpu/drm/meson/meson_overlay.c #define VD_H_END(value)			FIELD_PREP(GENMASK(11, 0), value)
GENMASK            61 drivers/gpu/drm/meson/meson_overlay.c #define VD_H_START(value)		FIELD_PREP(GENMASK(27, 16), value)
GENMASK            64 drivers/gpu/drm/meson/meson_overlay.c #define VD_V_END(value)			FIELD_PREP(GENMASK(11, 0), value)
GENMASK            65 drivers/gpu/drm/meson/meson_overlay.c #define VD_V_START(value)		FIELD_PREP(GENMASK(27, 16), value)
GENMASK            68 drivers/gpu/drm/meson/meson_overlay.c #define VD2_V_END(value)		FIELD_PREP(GENMASK(11, 0), value)
GENMASK            69 drivers/gpu/drm/meson/meson_overlay.c #define VD2_V_START(value)		FIELD_PREP(GENMASK(27, 16), value)
GENMASK            72 drivers/gpu/drm/meson/meson_overlay.c #define VD_V_WIDTH(value)		FIELD_PREP(GENMASK(11, 0), value)
GENMASK            73 drivers/gpu/drm/meson/meson_overlay.c #define VD_H_WIDTH(value)		FIELD_PREP(GENMASK(27, 16), value)
GENMASK            76 drivers/gpu/drm/meson/meson_overlay.c #define VD_REGION24_START(value)	FIELD_PREP(GENMASK(11, 0), value)
GENMASK            77 drivers/gpu/drm/meson/meson_overlay.c #define VD_REGION13_END(value)		FIELD_PREP(GENMASK(27, 16), value)
GENMASK            28 drivers/gpu/drm/meson/meson_plane.c #define SCI_WH_M1_W(w)			FIELD_PREP(GENMASK(28, 16), w)
GENMASK            29 drivers/gpu/drm/meson/meson_plane.c #define SCI_WH_M1_H(h)			FIELD_PREP(GENMASK(12, 0), h)
GENMASK            33 drivers/gpu/drm/meson/meson_plane.c #define SCO_HV_START(start)		FIELD_PREP(GENMASK(27, 16), start)
GENMASK            34 drivers/gpu/drm/meson/meson_plane.c #define SCO_HV_END(end)			FIELD_PREP(GENMASK(11, 0), end)
GENMASK            41 drivers/gpu/drm/meson/meson_plane.c #define VSC_BANK_LEN(value)		FIELD_PREP(GENMASK(2, 0), value)
GENMASK            42 drivers/gpu/drm/meson/meson_plane.c #define VSC_TOP_INI_RCV_NUM(value)	FIELD_PREP(GENMASK(6, 3), value)
GENMASK            43 drivers/gpu/drm/meson/meson_plane.c #define VSC_TOP_RPT_L0_NUM(value)	FIELD_PREP(GENMASK(9, 8), value)
GENMASK            44 drivers/gpu/drm/meson/meson_plane.c #define VSC_BOT_INI_RCV_NUM(value)	FIELD_PREP(GENMASK(14, 11), value)
GENMASK            45 drivers/gpu/drm/meson/meson_plane.c #define VSC_BOT_RPT_L0_NUM(value)	FIELD_PREP(GENMASK(17, 16), value)
GENMASK            50 drivers/gpu/drm/meson/meson_plane.c #define VSC_INI_PHASE_BOT(bottom)	FIELD_PREP(GENMASK(31, 16), bottom)
GENMASK            51 drivers/gpu/drm/meson/meson_plane.c #define VSC_INI_PHASE_TOP(top)		FIELD_PREP(GENMASK(15, 0), top)
GENMASK            54 drivers/gpu/drm/meson/meson_plane.c #define HSC_BANK_LENGTH(value)		FIELD_PREP(GENMASK(2, 0), value)
GENMASK            55 drivers/gpu/drm/meson/meson_plane.c #define HSC_INI_RCV_NUM0(value)		FIELD_PREP(GENMASK(6, 3), value)
GENMASK            56 drivers/gpu/drm/meson/meson_plane.c #define HSC_RPT_P0_NUM0(value)		FIELD_PREP(GENMASK(9, 8), value)
GENMASK            61 drivers/gpu/drm/meson/meson_plane.c #define SC_PHASE_STEP(value)		FIELD_PREP(GENMASK(27, 0), value)
GENMASK           415 drivers/gpu/drm/meson/meson_registers.h #define		VPP_OFIFO_SIZE_MASK             GENMASK(13, 0)
GENMASK           201 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.reserved_state[0] = GENMASK(7, 0),	/* first 8 MMBs */
GENMASK           363 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.reserved_state[0] = GENMASK(23, 0),	/* first 24 MMBs */
GENMASK           100 drivers/gpu/drm/nouveau/dispnv50/base907c.c 		return ret & GENMASK(18, 0);
GENMASK            58 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_LINESET_LINEDELTA		GENMASK(1, 0)
GENMASK            61 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_INVSEL_DEFAULT		GENMASK(5, 4)
GENMASK            62 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_INVSEL_NLINV		GENMASK(2, 0)
GENMASK            63 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_INVSEL_RTNI			GENMASK(2, 1)
GENMASK            72 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_CMD2_BK1_VGHSS_SET		GENMASK(2, 0)
GENMASK            75 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_VGLS_SEL			GENMASK(2, 0)
GENMASK            86 drivers/gpu/drm/panel/panel-sitronix-st7701.c #define DSI_CMD2_BK1_SPD1_SET		(GENMASK(6, 4) | DSI_SPD1_T2D)
GENMASK            30 drivers/gpu/drm/panel/panel-tpo-tpg110.c #define TPG110_RES_MASK			GENMASK(2, 0)
GENMASK           295 drivers/gpu/drm/panfrost/panfrost_perfcnt.c 		nl2c = ((pfdev->features.mem_features >> 8) & GENMASK(3, 0)) + 1;
GENMASK            93 drivers/gpu/drm/pl111/pl111_versatile.c #define INTEGRATOR_CLCD_MASK		GENMASK(19, 8)
GENMASK           680 drivers/gpu/drm/rcar-du/rcar_du_kms.c 				   & GENMASK(1, 0);
GENMASK            27 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define VERSION				GENMASK(31, 8)
GENMASK            33 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WCFGR_COLMUX	GENMASK(3, 1)	/* COLor MUltipleXing */
GENMASK            43 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WPCR0_UIX4	GENMASK(5, 0)	/* Unit Interval X 4 */
GENMASK            48 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_NDIV	GENMASK(8, 2)	/* pll loop DIVision Factor */
GENMASK            49 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_IDF	GENMASK(14, 11)	/* pll Input Division Factor */
GENMASK            50 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c #define WRPCR_ODF	GENMASK(17, 16)	/* pll Output Division Factor */
GENMASK            40 drivers/gpu/drm/stm/ltdc.c #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
GENMASK           103 drivers/gpu/drm/stm/ltdc.c #define SSCR_VSH	GENMASK(10, 0)	/* Vertical Synchronization Height */
GENMASK           104 drivers/gpu/drm/stm/ltdc.c #define SSCR_HSW	GENMASK(27, 16)	/* Horizontal Synchronization Width */
GENMASK           106 drivers/gpu/drm/stm/ltdc.c #define BPCR_AVBP	GENMASK(10, 0)	/* Accumulated Vertical Back Porch */
GENMASK           107 drivers/gpu/drm/stm/ltdc.c #define BPCR_AHBP	GENMASK(27, 16)	/* Accumulated Horizontal Back Porch */
GENMASK           109 drivers/gpu/drm/stm/ltdc.c #define AWCR_AAH	GENMASK(10, 0)	/* Accumulated Active Height */
GENMASK           110 drivers/gpu/drm/stm/ltdc.c #define AWCR_AAW	GENMASK(27, 16)	/* Accumulated Active Width */
GENMASK           112 drivers/gpu/drm/stm/ltdc.c #define TWCR_TOTALH	GENMASK(10, 0)	/* TOTAL Height */
GENMASK           113 drivers/gpu/drm/stm/ltdc.c #define TWCR_TOTALW	GENMASK(27, 16)	/* TOTAL Width */
GENMASK           122 drivers/gpu/drm/stm/ltdc.c #define GC1R_WBCH	GENMASK(3, 0)	/* Width of Blue CHannel output */
GENMASK           123 drivers/gpu/drm/stm/ltdc.c #define GC1R_WGCH	GENMASK(7, 4)	/* Width of Green Channel output */
GENMASK           124 drivers/gpu/drm/stm/ltdc.c #define GC1R_WRCH	GENMASK(11, 8)	/* Width of Red Channel output */
GENMASK           126 drivers/gpu/drm/stm/ltdc.c #define GC1R_DT		GENMASK(15, 14)	/* Dithering Technique */
GENMASK           127 drivers/gpu/drm/stm/ltdc.c #define GC1R_GCT	GENMASK(19, 17)	/* Gamma Correction Technique */
GENMASK           143 drivers/gpu/drm/stm/ltdc.c #define GC2R_BW		GENMASK(6, 4)	/* Bus Width (log2 of nb of bytes) */
GENMASK           150 drivers/gpu/drm/stm/ltdc.c #define BCCR_BCBLUE	GENMASK(7, 0)	/* Background Color BLUE */
GENMASK           151 drivers/gpu/drm/stm/ltdc.c #define BCCR_BCGREEN	GENMASK(15, 8)	/* Background Color GREEN */
GENMASK           152 drivers/gpu/drm/stm/ltdc.c #define BCCR_BCRED	GENMASK(23, 16)	/* Background Color RED */
GENMASK           153 drivers/gpu/drm/stm/ltdc.c #define BCCR_BCWHITE	GENMASK(23, 0)	/* Background Color WHITE */
GENMASK           160 drivers/gpu/drm/stm/ltdc.c #define CPSR_CYPOS	GENMASK(15, 0)	/* Current Y position */
GENMASK           171 drivers/gpu/drm/stm/ltdc.c #define LXWHPCR_WHSTPOS	GENMASK(11, 0)	/* Window Horizontal StarT POSition */
GENMASK           172 drivers/gpu/drm/stm/ltdc.c #define LXWHPCR_WHSPPOS	GENMASK(27, 16)	/* Window Horizontal StoP POSition */
GENMASK           174 drivers/gpu/drm/stm/ltdc.c #define LXWVPCR_WVSTPOS	GENMASK(10, 0)	/* Window Vertical StarT POSition */
GENMASK           175 drivers/gpu/drm/stm/ltdc.c #define LXWVPCR_WVSPPOS	GENMASK(26, 16)	/* Window Vertical StoP POSition */
GENMASK           177 drivers/gpu/drm/stm/ltdc.c #define LXPFCR_PF	GENMASK(2, 0)	/* Pixel Format */
GENMASK           179 drivers/gpu/drm/stm/ltdc.c #define LXCACR_CONSTA	GENMASK(7, 0)	/* CONSTant Alpha */
GENMASK           181 drivers/gpu/drm/stm/ltdc.c #define LXBFCR_BF2	GENMASK(2, 0)	/* Blending Factor 2 */
GENMASK           182 drivers/gpu/drm/stm/ltdc.c #define LXBFCR_BF1	GENMASK(10, 8)	/* Blending Factor 1 */
GENMASK           184 drivers/gpu/drm/stm/ltdc.c #define LXCFBLR_CFBLL	GENMASK(12, 0)	/* Color Frame Buffer Line Length */
GENMASK           185 drivers/gpu/drm/stm/ltdc.c #define LXCFBLR_CFBP	GENMASK(28, 16)	/* Color Frame Buffer Pitch in bytes */
GENMASK           187 drivers/gpu/drm/stm/ltdc.c #define LXCFBLNR_CFBLN	GENMASK(10, 0)	/* Color Frame Buffer Line Number */
GENMASK            23 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_MODCTL_OUT_SEL			GENMASK(22, 20)
GENMASK            56 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l)		GENMASK(3 + ((l) * 8), (l) * 8)
GENMASK            67 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK	GENMASK(31, 24)
GENMASK            71 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK	GENMASK(11, 10)
GENMASK            78 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT		GENMASK(15, 14)
GENMASK            79 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT		GENMASK(13, 12)
GENMASK            80 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT		GENMASK(11, 8)
GENMASK           115 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_IYUVCTL_FBFMT_MASK		GENMASK(14, 12)
GENMASK           121 drivers/gpu/drm/sun4i/sun4i_backend.h #define SUN4I_BACKEND_IYUVCTL_FBPS_MASK			GENMASK(9, 8)
GENMASK           122 drivers/gpu/drm/sun4i/sun4i_dotclock.c 				  GENMASK(6, 0), div);
GENMASK           146 drivers/gpu/drm/sun4i/sun4i_dotclock.c 			   GENMASK(29, 28),
GENMASK            37 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_TIMING_X(x)		((((x) - 1) & GENMASK(11, 0)))
GENMASK            38 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_VID_TIMING_Y(y)		((((y) - 1) & GENMASK(11, 0)) << 16)
GENMASK            88 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_PLL_CTRL_DIV_MASK		GENMASK(7, 4)
GENMASK           134 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK	GENMASK(7, 4)
GENMASK           137 drivers/gpu/drm/sun4i/sun4i_hdmi.h #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK	GENMASK(3, 0)
GENMASK           318 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c #define SUN4I_HDMI_PAD_CTRL1_MASK	(GENMASK(24, 7) | GENMASK(5, 0))
GENMASK           319 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c #define SUN4I_HDMI_PLL_CTRL_MASK	(GENMASK(31, 8) | GENMASK(3, 0))
GENMASK           371 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon_div &= GENMASK(6, 0);
GENMASK            54 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CTL_IF_MASK				GENMASK(25, 24)
GENMASK            56 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
GENMASK            58 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CTL_SRC_SEL_MASK			GENMASK(2, 0)
GENMASK            84 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_CPU_IF_MODE_MASK			GENMASK(31, 28)
GENMASK           109 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK		GENMASK(3, 0)
GENMASK           122 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins)	GENMASK(pins, 0)
GENMASK           127 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON1_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
GENMASK           129 drivers/gpu/drm/sun4i/sun4i_tcon.h #define SUN4I_TCON1_CTL_SRC_SEL_MASK			GENMASK(1, 0)
GENMASK            28 drivers/gpu/drm/sun4i/sun4i_tv.c #define SUN4I_TVE_EN_DAC_MAP_MASK		GENMASK(19, 4)
GENMASK           332 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 	u8 lanes_mask = GENMASK(device->lanes - 1, 0);
GENMASK            19 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK	GENMASK(15, 8)
GENMASK            22 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK	GENMASK(23, 16)
GENMASK            49 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK	GENMASK(15, 12)
GENMASK           113 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK	GENMASK(5, 0)
GENMASK           134 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK	GENMASK(3, 0)
GENMASK           143 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK	GENMASK(16, 11)
GENMASK           145 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h #define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK	GENMASK(5, 0)
GENMASK            59 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK	GENMASK(12, 8)
GENMASK            15 drivers/gpu/drm/sun4i/sun8i_tcon_top.h #define TCON_TOP_PORT_DE0_MSK			GENMASK(1, 0)
GENMASK            16 drivers/gpu/drm/sun4i/sun8i_tcon_top.h #define TCON_TOP_PORT_DE1_MSK			GENMASK(5, 4)
GENMASK            19 drivers/gpu/drm/sun4i/sun8i_tcon_top.h #define TCON_TOP_HDMI_SRC_MSK			GENMASK(29, 28)
GENMASK            39 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK	GENMASK(2, 1)
GENMASK            40 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK	GENMASK(12, 8)
GENMASK            42 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK	GENMASK(31, 24)
GENMASK            36 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK	GENMASK(12, 8)
GENMASK            37 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK	GENMASK(31, 24)
GENMASK            66 drivers/gpu/drm/tve200/tve200_drm.h #define TVE200_CTRL_RETRYCNT_MASK	GENMASK(23, 16)
GENMASK             9 drivers/gpu/drm/v3d/v3d_regs.h #define V3D_MASK(high, low) ((u32)GENMASK(high, low))
GENMASK           869 drivers/gpu/drm/vc4/vc4_hdmi.c 	channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
GENMASK           104 drivers/gpu/drm/vc4/vc4_kms.c 		r |= GENMASK(8, 0);
GENMASK           107 drivers/gpu/drm/vc4/vc4_kms.c 		r |= (in >> 23) & GENMASK(8, 0);
GENMASK            41 drivers/gpu/drm/vc4/vc4_perfmon.c 	mask = GENMASK(perfmon->ncounters - 1, 0);
GENMASK            11 drivers/gpu/drm/vc4/vc4_regs.h #define VC4_MASK(high, low) ((u32)GENMASK(high, low))
GENMASK            57 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_HEIGHT_MASK		GENMASK(31, 16)
GENMASK            59 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_WIDTH_MASK			GENMASK(15, 0)
GENMASK            64 drivers/gpu/drm/vc4/vc4_txp.c #define TXP_PILOT_MASK			GENMASK(31, 24)
GENMASK            67 drivers/gpu/drm/vc4/vc4_txp.c #define TXP_VERSION_MASK		GENMASK(23, 22)
GENMASK            81 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_BYTE_ENABLE_MASK		GENMASK(19, 16)
GENMASK           102 drivers/gpu/drm/vc4/vc4_txp.c # define TXP_FORMAT_MASK		GENMASK(11, 8)
GENMASK           256 drivers/gpu/drm/vc4/vc4_txp.c 	if (fb->pitches[0] & GENMASK(3, 0))
GENMASK            43 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_YDEL_MASK		GENMASK(28, 26)
GENMASK            45 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CDEL_MASK		GENMASK(25, 24)
GENMASK            48 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CHROMA_GAIN_MASK	GENMASK(17, 16)
GENMASK            53 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_CBURST_GAIN_MASK	GENMASK(14, 13)
GENMASK            67 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG0_STD_MASK		GENMASK(1, 0)
GENMASK            84 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG1_OUTPUT_MODE_MASK	GENMASK(12, 10)
GENMASK           105 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_SYNC_ADJ_MASK	GENMASK(14, 12)
GENMASK           110 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CONFIG2_TMUX_MASK		GENMASK(3, 2)
GENMASK           130 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_CFG_SG_MODE_MASK		GENMASK(6, 5)
GENMASK           146 drivers/gpu/drm/vc4/vc4_vec.c #define VEC_DAC_MISC_VCD_CTRL_MASK	GENMASK(31, 16)
GENMASK            27 drivers/gpu/drm/zte/zx_vga_regs.h #define VGA_RXF_COUNT_MASK		GENMASK(7, 2)
GENMASK            99 drivers/hid/hid-logitech-dj.c #define HIDPP_DEVICE_TYPE_MASK			GENMASK(3, 0)
GENMASK           109 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_ISH_FWSTS_MASK		GENMASK(15, 12)
GENMASK            49 drivers/hid/intel-ish-hid/ishtp-fw-loader.c #define	CMD_MASK				GENMASK(6, 0)
GENMASK            24 drivers/hwmon/as370-hwmon.c #define  BN_MASK	GENMASK(11, 0)
GENMASK            77 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK		GENMASK(31, 16)
GENMASK            82 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
GENMASK            93 drivers/hwmon/aspeed-pwm-tacho.c #define DUTY_CTRL_PWM2_RISE_FALL_MASK	GENMASK(31, 16)
GENMASK            96 drivers/hwmon/aspeed-pwm-tacho.c #define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
GENMASK            99 drivers/hwmon/aspeed-pwm-tacho.c #define TYPE_CTRL_FAN_MASK		(GENMASK(5, 1) | GENMASK(31, 16))
GENMASK           100 drivers/hwmon/aspeed-pwm-tacho.c #define TYPE_CTRL_FAN1_MASK		GENMASK(31, 0)
GENMASK           141 drivers/hwmon/aspeed-pwm-tacho.c #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
GENMASK            36 drivers/hwmon/ina3221.c #define INA3221_CONFIG_MODE_MASK	GENMASK(2, 0)
GENMASK            42 drivers/hwmon/ina3221.c #define INA3221_CONFIG_VSH_CT_MASK	GENMASK(5, 3)
GENMASK            43 drivers/hwmon/ina3221.c #define INA3221_CONFIG_VSH_CT(x)	(((x) & GENMASK(5, 3)) >> 3)
GENMASK            45 drivers/hwmon/ina3221.c #define INA3221_CONFIG_VBUS_CT_MASK	GENMASK(8, 6)
GENMASK            46 drivers/hwmon/ina3221.c #define INA3221_CONFIG_VBUS_CT(x)	(((x) & GENMASK(8, 6)) >> 6)
GENMASK            48 drivers/hwmon/ina3221.c #define INA3221_CONFIG_AVG_MASK		GENMASK(11, 9)
GENMASK            49 drivers/hwmon/ina3221.c #define INA3221_CONFIG_AVG(x)		(((x) & GENMASK(11, 9)) >> 9)
GENMASK            50 drivers/hwmon/ina3221.c #define INA3221_CONFIG_CHs_EN_MASK	GENMASK(14, 12)
GENMASK            39 drivers/hwmon/ltc2990.c #define LTC2990_ALL	GENMASK(9, 0)
GENMASK            42 drivers/hwmon/ltc2990.c #define LTC2990_MODE0_MASK	GENMASK(2, 0)
GENMASK            44 drivers/hwmon/ltc2990.c #define LTC2990_MODE1_MASK	GENMASK(1, 0)
GENMASK            53 drivers/hwmon/max6621.c #define MAX6621_ENABLE_TEMP_ALL		GENMASK(MAX6621_ENABLE_S3D1_BIT, \
GENMASK           108 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TICLR_CLEAR_ALL	GENMASK(5, 0)
GENMASK           116 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_TIEN_ENABLE_ALL	GENMASK(5, 0)
GENMASK            75 drivers/hwmon/pmbus/adm1275.c #define ADM1275_VI_AVG_MASK		GENMASK(ADM1275_VI_AVG_SHIFT + 2, \
GENMASK            80 drivers/hwmon/pmbus/adm1275.c #define ADM1278_PWR_AVG_MASK		GENMASK(ADM1278_PWR_AVG_SHIFT + 2, \
GENMASK            83 drivers/hwmon/pmbus/adm1275.c #define ADM1278_VI_AVG_MASK		GENMASK(ADM1278_VI_AVG_SHIFT + 2, \
GENMASK            31 drivers/hwmon/pmbus/pxe1610.c 		vout_mode = ret & GENMASK(4, 0);
GENMASK            34 drivers/hwmon/pmbus/tps53679.c 	vout_params = ret & GENMASK(4, 0);
GENMASK            42 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPCSR_ARM_INST_MASK		GENMASK(31, 2)
GENMASK            43 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDPCSR_THUMB_INST_MASK		GENMASK(31, 1)
GENMASK            58 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDVIDSR_VMID			GENMASK(7, 0)
GENMASK            72 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDDEVID1_PCSR_OFFSET_MASK	GENMASK(3, 0)
GENMASK            77 drivers/hwtracing/coresight/coresight-cpu-debug.c #define EDDEVID_PCSAMPLE_MODE		GENMASK(3, 0)
GENMASK           125 drivers/hwtracing/coresight/coresight-etm.h #define PORT_SIZE_MASK		(GENMASK(21, 21) | GENMASK(6, 4))
GENMASK           701 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c 	config->bb_ctrl = val & GENMASK(8, 0);
GENMASK          1588 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c 	config->res_ctrl[idx] = val & GENMASK(21, 0);
GENMASK           173 drivers/hwtracing/coresight/coresight-etm4x.h #define ETMv4_MODE_ALL			(GENMASK(27, 0) | \
GENMASK            37 drivers/hwtracing/coresight/coresight-priv.h #define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
GENMASK            91 drivers/hwtracing/coresight/coresight-tmc.c 		mask = GENMASK(31, 4);
GENMASK            94 drivers/hwtracing/coresight/coresight-tmc.c 		mask = GENMASK(31, 5);
GENMASK            94 drivers/hwtracing/coresight/coresight-tmc.h #define TMC_AUTH_NSID_MASK	GENMASK(1, 0)
GENMASK            54 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_TBUF_MASK			GENMASK(31, 28)
GENMASK            55 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_THDSTA_MASK			GENMASK(27, 24)
GENMASK            56 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_TACST_MASK			GENMASK(23, 20)
GENMASK            58 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_SCL_HIGH_MASK			GENMASK(19, 16)
GENMASK            60 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_SCL_LOW_MASK			GENMASK(15, 12)
GENMASK            61 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK		GENMASK(3, 0)
GENMASK            62 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_TIME_SCL_REG_MAX			GENMASK(3, 0)
GENMASK           119 drivers/i2c/busses/i2c-aspeed.c #define ASPEED_I2CD_DEV_ADDR_MASK			GENMASK(6, 0)
GENMASK           866 drivers/i2c/busses/i2c-aspeed.c 	return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
GENMASK           875 drivers/i2c/busses/i2c-aspeed.c 	return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
GENMASK            36 drivers/i2c/busses/i2c-brcmstb.c #define BSC_CNT_REG1_MASK(nb)	(nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
GENMASK            36 drivers/i2c/busses/i2c-cht-wc.c #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK	((u8)GENMASK(3, 1))
GENMASK           107 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_SDA_HOLD_RX_MASK		GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
GENMASK           114 drivers/i2c/busses/i2c-designware-core.h #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK	GENMASK(3, 2)
GENMASK            59 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_ADDR		GENMASK(23, 17)
GENMASK            61 drivers/i2c/busses/i2c-fsi.c #define I2C_CMD_LEN		GENMASK(15, 0)
GENMASK            64 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_CLKDIV		GENMASK(31, 16)
GENMASK            65 drivers/i2c/busses/i2c-fsi.c #define I2C_MODE_PORT		GENMASK(15, 10)
GENMASK            72 drivers/i2c/busses/i2c-fsi.c #define I2C_WATERMARK_HI	GENMASK(15, 12)
GENMASK            73 drivers/i2c/busses/i2c-fsi.c #define I2C_WATERMARK_LO	GENMASK(7, 4)
GENMASK           101 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_MAX_PORT	GENMASK(19, 16)
GENMASK           107 drivers/i2c/busses/i2c-fsi.c #define I2C_STAT_FIFO_COUNT	GENMASK(7, 0)
GENMASK           121 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_FIFO_SZ	GENMASK(31, 24)
GENMASK           132 drivers/i2c/busses/i2c-fsi.c #define I2C_ESTAT_VERSION	GENMASK(4, 0)
GENMASK            36 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_CLKDIV_MASK	GENMASK(21, 12)
GENMASK            38 drivers/i2c/busses/i2c-meson.c #define REG_CTRL_CLKDIVEXT_MASK	GENMASK(29, 28)
GENMASK           144 drivers/i2c/busses/i2c-meson.c 			   (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
GENMASK            49 drivers/i2c/busses/i2c-mlxcpld.c #define MLXCPLD_I2C_DATA_SZ_MASK	GENMASK(6, 5)
GENMASK            28 drivers/i2c/busses/i2c-nvidia-gpu.c #define I2C_MST_CNTL_STATUS			GENMASK(30, 29)
GENMASK            82 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOSTAT_TFD	GENMASK(23, 16)
GENMASK            83 drivers/i2c/busses/i2c-owl.c #define OWL_I2C_FIFOSTAT_RFD	GENMASK(15, 8)
GENMASK            43 drivers/i2c/busses/i2c-qcom-geni.c #define SLV_ADDR_MSK		GENMASK(15, 9)
GENMASK            46 drivers/i2c/busses/i2c-qcom-geni.c #define HIGH_COUNTER_MSK	GENMASK(29, 20)
GENMASK            48 drivers/i2c/busses/i2c-qcom-geni.c #define LOW_COUNTER_MSK		GENMASK(19, 10)
GENMASK            50 drivers/i2c/busses/i2c-qcom-geni.c #define CYCLE_COUNTER_MSK	GENMASK(9, 0)
GENMASK           111 drivers/i2c/busses/i2c-rcar.c #define ID_P_MASK		GENMASK(31, 29)
GENMASK            36 drivers/i2c/busses/i2c-sprd.c #define FIFO_AF_LVL_MASK	GENMASK(19, 16)
GENMASK            38 drivers/i2c/busses/i2c-sprd.c #define FIFO_AE_LVL_MASK	GENMASK(15, 12)
GENMASK            69 drivers/i2c/busses/i2c-sprd.c 	((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
GENMASK            71 drivers/i2c/busses/i2c-sprd.c 	(((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
GENMASK            51 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CR2_FREQ_MASK	GENMASK(5, 0)
GENMASK            82 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_CCR_CCR_MASK	GENMASK(11, 0)
GENMASK            88 drivers/i2c/busses/i2c-stm32f4.c #define STM32F4_I2C_TRISE_VALUE_MASK	GENMASK(5, 0)
GENMASK            79 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_NBYTES_MASK		GENMASK(23, 16)
GENMASK            87 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_SADD10_MASK		GENMASK(9, 0)
GENMASK            90 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_CR2_SADD7_MASK		GENMASK(7, 1)
GENMASK            96 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR1_OA1_10_MASK		GENMASK(9, 0)
GENMASK            99 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR1_OA1_7_MASK		GENMASK(7, 1)
GENMASK           108 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR2_OA2MSK_MASK		GENMASK(10, 8)
GENMASK           110 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_OAR2_OA2_7_MASK		GENMASK(7, 1)
GENMASK           117 drivers/i2c/busses/i2c-stm32f7.c #define STM32F7_I2C_ISR_ADDCODE_MASK		GENMASK(23, 17)
GENMASK            34 drivers/i2c/busses/i2c-zx2967.c #define I2C_ADDR_LOW_MASK		GENMASK(6, 0)
GENMASK            36 drivers/i2c/busses/i2c-zx2967.c #define I2C_ADDR_HI_MASK		GENMASK(2, 0)
GENMASK            43 drivers/i2c/busses/i2c-zx2967.c #define I2C_INT_MASK			GENMASK(6, 0)
GENMASK            40 drivers/i2c/i2c-slave-eeprom.c #define I2C_SLAVE_BYTELEN GENMASK(15, 0)
GENMASK            32 drivers/i3c/master/dw-i3c-master.c #define DEV_ADDR_DYNAMIC(x)		(((x) << 16) & GENMASK(22, 16))
GENMASK            40 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SPEED(x)		(((x) << 21) & GENMASK(23, 21))
GENMASK            41 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_DEV_INDEX(x)	(((x) << 16) & GENMASK(20, 16))
GENMASK            43 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_CMD(x)		(((x) << 7) & GENMASK(14, 7))
GENMASK            44 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_TID(x)		(((x) << 3) & GENMASK(6, 3))
GENMASK            46 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_ARG_DATA_LEN(x)	(((x) << 16) & GENMASK(31, 16))
GENMASK            50 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_DATA_BYTE_3(x)	(((x) << 24) & GENMASK(31, 24))
GENMASK            51 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_DATA_BYTE_2(x)	(((x) << 16) & GENMASK(23, 16))
GENMASK            52 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_SDA_DATA_BYTE_1(x)	(((x) << 8) & GENMASK(15, 8))
GENMASK            58 drivers/i3c/master/dw-i3c-master.c #define COMMAND_PORT_DEV_COUNT(x)	(((x) << 21) & GENMASK(25, 21))
GENMASK            62 drivers/i3c/master/dw-i3c-master.c #define RESPONSE_PORT_ERR_STATUS(x)	(((x) & GENMASK(31, 28)) >> 28)
GENMASK            72 drivers/i3c/master/dw-i3c-master.c #define RESPONSE_PORT_TID(x)		(((x) & GENMASK(27, 24)) >> 24)
GENMASK            73 drivers/i3c/master/dw-i3c-master.c #define RESPONSE_PORT_DATA_LEN(x)	((x) & GENMASK(15, 0))
GENMASK            78 drivers/i3c/master/dw-i3c-master.c #define QUEUE_THLD_CTRL_RESP_BUF_MASK	GENMASK(15, 8)
GENMASK            82 drivers/i3c/master/dw-i3c-master.c #define DATA_BUFFER_THLD_CTRL_RX_BUF	GENMASK(11, 8)
GENMASK            87 drivers/i3c/master/dw-i3c-master.c #define IBI_REQ_REJECT_ALL		GENMASK(31, 0)
GENMASK           133 drivers/i3c/master/dw-i3c-master.c #define QUEUE_STATUS_IBI_STATUS_CNT(x)	(((x) & GENMASK(28, 24)) >> 24)
GENMASK           134 drivers/i3c/master/dw-i3c-master.c #define QUEUE_STATUS_IBI_BUF_BLR(x)	(((x) & GENMASK(23, 16)) >> 16)
GENMASK           135 drivers/i3c/master/dw-i3c-master.c #define QUEUE_STATUS_LEVEL_RESP(x)	(((x) & GENMASK(15, 8)) >> 8)
GENMASK           136 drivers/i3c/master/dw-i3c-master.c #define QUEUE_STATUS_LEVEL_CMD(x)	((x) & GENMASK(7, 0))
GENMASK           139 drivers/i3c/master/dw-i3c-master.c #define DATA_BUFFER_STATUS_LEVEL_TX(x)	((x) & GENMASK(7, 0))
GENMASK           144 drivers/i3c/master/dw-i3c-master.c #define DEVICE_ADDR_TABLE_DEPTH(x)	(((x) & GENMASK(31, 16)) >> 16)
GENMASK           145 drivers/i3c/master/dw-i3c-master.c #define DEVICE_ADDR_TABLE_ADDR(x)	((x) & GENMASK(7, 0))
GENMASK           159 drivers/i3c/master/dw-i3c-master.c #define SCL_I3C_TIMING_HCNT(x)		(((x) << 16) & GENMASK(23, 16))
GENMASK           160 drivers/i3c/master/dw-i3c-master.c #define SCL_I3C_TIMING_LCNT(x)		((x) & GENMASK(7, 0))
GENMASK           164 drivers/i3c/master/dw-i3c-master.c #define SCL_I2C_FM_TIMING_HCNT(x)	(((x) << 16) & GENMASK(31, 16))
GENMASK           165 drivers/i3c/master/dw-i3c-master.c #define SCL_I2C_FM_TIMING_LCNT(x)	((x) & GENMASK(15, 0))
GENMASK           168 drivers/i3c/master/dw-i3c-master.c #define SCL_I2C_FMP_TIMING_HCNT(x)	(((x) << 16) & GENMASK(23, 16))
GENMASK           169 drivers/i3c/master/dw-i3c-master.c #define SCL_I2C_FMP_TIMING_LCNT(x)	((x) & GENMASK(15, 0))
GENMASK           172 drivers/i3c/master/dw-i3c-master.c #define SCL_EXT_LCNT_4(x)		(((x) << 24) & GENMASK(31, 24))
GENMASK           173 drivers/i3c/master/dw-i3c-master.c #define SCL_EXT_LCNT_3(x)		(((x) << 16) & GENMASK(23, 16))
GENMASK           174 drivers/i3c/master/dw-i3c-master.c #define SCL_EXT_LCNT_2(x)		(((x) << 8) & GENMASK(15, 8))
GENMASK           175 drivers/i3c/master/dw-i3c-master.c #define SCL_EXT_LCNT_1(x)		((x) & GENMASK(7, 0))
GENMASK           179 drivers/i3c/master/dw-i3c-master.c #define BUS_I3C_MST_FREE(x)		((x) & GENMASK(15, 0))
GENMASK           188 drivers/i3c/master/dw-i3c-master.c #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)	(((x) << 16) & GENMASK(23, 16))
GENMASK           189 drivers/i3c/master/dw-i3c-master.c #define DEV_ADDR_TABLE_STATIC_ADDR(x)	((x) & GENMASK(6, 0))
GENMASK           327 drivers/i3c/master/dw-i3c-master.c 	if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
GENMASK           809 drivers/i3c/master/dw-i3c-master.c 	newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
GENMASK          1153 drivers/i3c/master/dw-i3c-master.c 	master->free_pos = GENMASK(master->maxdevs - 1, 0);
GENMASK            30 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_CMDR_DEPTH(x)	(4 << (((x) & GENMASK(31, 29)) >> 29))
GENMASK            36 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_GPO_NUM(x)		(((x) & GENMASK(23, 16)) >> 16)
GENMASK            37 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_GPI_NUM(x)		(((x) & GENMASK(15, 8)) >> 8)
GENMASK            38 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_IBIR_DEPTH(x)	(4 << (((x) & GENMASK(7, 6)) >> 7))
GENMASK            41 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS0_DEVS_NUM(x)	((x) & GENMASK(3, 0))
GENMASK            44 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_IBI_HW_RES(x)	((((x) & GENMASK(31, 28)) >> 28) + 1)
GENMASK            45 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_CMD_DEPTH(x)	(4 << (((x) & GENMASK(27, 26)) >> 26))
GENMASK            46 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_SLVDDR_RX_DEPTH(x)	(8 << (((x) & GENMASK(25, 21)) >> 21))
GENMASK            47 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_SLVDDR_TX_DEPTH(x)	(8 << (((x) & GENMASK(20, 16)) >> 16))
GENMASK            48 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_IBI_DEPTH(x)	(2 << (((x) & GENMASK(12, 10)) >> 10))
GENMASK            49 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_RX_DEPTH(x)	(8 << (((x) & GENMASK(9, 5)) >> 5))
GENMASK            50 drivers/i3c/master/i3c-master-cdns.c #define CONF_STATUS1_TX_DEPTH(x)	(8 << ((x) & GENMASK(4, 0)))
GENMASK            53 drivers/i3c/master/i3c-master-cdns.c #define REV_ID_VID(id)			(((id) & GENMASK(31, 20)) >> 20)
GENMASK            54 drivers/i3c/master/i3c-master-cdns.c #define REV_ID_PID(id)			(((id) & GENMASK(19, 8)) >> 8)
GENMASK            55 drivers/i3c/master/i3c-master-cdns.c #define REV_ID_REV_MAJOR(id)		(((id) & GENMASK(7, 4)) >> 4)
GENMASK            56 drivers/i3c/master/i3c-master-cdns.c #define REV_ID_REV_MINOR(id)		((id) & GENMASK(3, 0))
GENMASK            72 drivers/i3c/master/i3c-master-cdns.c #define CTRL_BUS_MODE_MASK		GENMASK(1, 0)
GENMASK            77 drivers/i3c/master/i3c-master-cdns.c #define PRESCL_CTRL0_MAX		GENMASK(9, 0)
GENMASK            80 drivers/i3c/master/i3c-master-cdns.c #define PRESCL_CTRL1_PP_LOW_MASK	GENMASK(15, 8)
GENMASK            82 drivers/i3c/master/i3c-master-cdns.c #define PRESCL_CTRL1_OD_LOW_MASK	GENMASK(7, 0)
GENMASK           139 drivers/i3c/master/i3c-master-cdns.c #define CMDR_ERROR(x)			(((x) & GENMASK(27, 24)) >> 24)
GENMASK           140 drivers/i3c/master/i3c-master-cdns.c #define CMDR_XFER_BYTES(x)		(((x) & GENMASK(19, 8)) >> 8)
GENMASK           143 drivers/i3c/master/i3c-master-cdns.c #define CMDR_CMDID(x)			((x) & GENMASK(7, 0))
GENMASK           147 drivers/i3c/master/i3c-master-cdns.c #define IBIR_SLVID(x)			(((x) & GENMASK(11, 8)) >> 8)
GENMASK           149 drivers/i3c/master/i3c-master-cdns.c #define IBIR_XFER_BYTES(x)		(((x) & GENMASK(6, 2)) >> 2)
GENMASK           153 drivers/i3c/master/i3c-master-cdns.c #define IBIR_TYPE(x)			((x) & GENMASK(1, 0))
GENMASK           183 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS0_REG_ADDR(s)		(((s) & GENMASK(23, 16)) >> 16)
GENMASK           184 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS0_XFRD_BYTES(s)	((s) & GENMASK(15, 0))
GENMASK           187 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_AS(s)		(((s) & GENMASK(21, 20)) >> 20)
GENMASK           192 drivers/i3c/master/i3c-master-cdns.c #define SLV_STATUS1_DA(x)		(((s) & GENMASK(15, 9)) >> 9)
GENMASK           276 drivers/i3c/master/i3c-master-cdns.c #define DEVS_CTRL_DEV_CLR_ALL		GENMASK(31, 16)
GENMASK           279 drivers/i3c/master/i3c-master-cdns.c #define DEVS_CTRL_DEVS_ACTIVE_MASK	GENMASK(15, 0)
GENMASK           286 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_DEV_ADDR_MASK	(GENMASK(6, 0) | GENMASK(15, 13))
GENMASK           287 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_SET_DEV_ADDR(a)	(((a) & GENMASK(6, 0)) |	\
GENMASK           288 drivers/i3c/master/i3c-master-cdns.c 					 (((a) & GENMASK(9, 7)) << 6))
GENMASK           289 drivers/i3c/master/i3c-master-cdns.c #define DEV_ID_RR0_GET_DEV_ADDR(x)	((((x) >> 1) & GENMASK(6, 0)) |	\
GENMASK           290 drivers/i3c/master/i3c-master-cdns.c 					 (((x) >> 6) & GENMASK(9, 7)))
GENMASK           304 drivers/i3c/master/i3c-master-cdns.c #define SIR_MAP_DEV_CONF_MASK(d)	(GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
GENMASK           311 drivers/i3c/master/i3c-master-cdns.c #define SIR_MAP_PL_MAX			GENMASK(4, 0)
GENMASK           317 drivers/i3c/master/i3c-master-cdns.c 	(((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
GENMASK           321 drivers/i3c/master/i3c-master-cdns.c 	(((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
GENMASK           339 drivers/i3c/master/i3c-master-cdns.c #define ASF_SRAM_CORR_FAULT_ADDR(x)	((x) & GENMASK(23, 0))
GENMASK           343 drivers/i3c/master/i3c-master-cdns.c #define ASF_SRAM_FAULT_CORR_STATS(x)	((x) & GENMASK(15, 0))
GENMASK           878 drivers/i3c/master/i3c-master-cdns.c 	ret |= (addr & GENMASK(6, 0)) << 1;
GENMASK           881 drivers/i3c/master/i3c-master-cdns.c 	ret |= (addr & GENMASK(9, 7)) << 6;
GENMASK          1582 drivers/i3c/master/i3c-master-cdns.c 	master->free_rr_slots = GENMASK(master->maxdevs, 1);
GENMASK           194 drivers/iio/accel/adis16201.c 		m = GENMASK(11, 0);
GENMASK           197 drivers/iio/accel/adis16201.c 		m = GENMASK(8, 0);
GENMASK           122 drivers/iio/accel/adis16209.c 		m = GENMASK(13, 0);
GENMASK            32 drivers/iio/accel/adxl345_core.c #define ADXL345_BW_RATE			GENMASK(3, 0)
GENMASK           100 drivers/iio/accel/adxl372.c #define ADXL372_FIFO_CTL_FORMAT_MSK		GENMASK(5, 3)
GENMASK           102 drivers/iio/accel/adxl372.c #define ADXL372_FIFO_CTL_MODE_MSK		GENMASK(2, 1)
GENMASK           104 drivers/iio/accel/bma180.c #define BMA250_RANGE_MASK	GENMASK(3, 0) /* Range of accel values */
GENMASK           105 drivers/iio/accel/bma180.c #define BMA250_BW_MASK		GENMASK(4, 0) /* Accel bandwidth */
GENMASK            44 drivers/iio/accel/mma8452.c #define  MMA8452_DATA_CFG_FS_MASK		GENMASK(1, 0)
GENMASK            50 drivers/iio/accel/mma8452.c #define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK	GENMASK(1, 0)
GENMASK            71 drivers/iio/accel/mma8452.c #define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
GENMASK            76 drivers/iio/accel/mma8452.c #define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
GENMASK            34 drivers/iio/accel/mma9551.c #define MMA9551_TILT_ANG_THRESH_MASK	GENMASK(3, 0)
GENMASK            25 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_WORD			GENMASK(15, 0)
GENMASK            31 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_STEPLEN		GENMASK(7, 0)
GENMASK            34 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_HEIGHT		GENMASK(15, 8)
GENMASK            35 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_WEIGHT		GENMASK(7, 0)
GENMASK            38 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_FILTSTEP		GENMASK(15, 8)
GENMASK            40 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_FILTTIME		GENMASK(6, 0)
GENMASK            43 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_SPDPRD		GENMASK(15, 8)
GENMASK            44 drivers/iio/accel/mma9553.c #define MMA9553_MASK_CONF_STEPCOALESCE		GENMASK(7, 0)
GENMASK            47 drivers/iio/accel/mma9553.c #define MMA9553_MAX_ACTTHD			GENMASK(15, 0)
GENMASK            56 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_ACTIVITY		GENMASK(10, 8)
GENMASK            57 drivers/iio/accel/mma9553.c #define MMA9553_MASK_STATUS_VERSION		GENMASK(7, 0)
GENMASK            37 drivers/iio/accel/mxc4005.c #define MXC4005_REG_CONTROL_MASK_FSR	GENMASK(6, 5)
GENMASK            29 drivers/iio/accel/sca3000.c #define   SCA3000_REG_REVID_MAJOR_MASK			GENMASK(8, 4)
GENMASK            30 drivers/iio/accel/sca3000.c #define   SCA3000_REG_REVID_MINOR_MASK			GENMASK(3, 0)
GENMASK            42 drivers/iio/accel/stk8312.c #define STK8312_RNG_MASK		GENMASK(7, 6)
GENMASK            43 drivers/iio/accel/stk8312.c #define STK8312_SR_MASK			GENMASK(2, 0)
GENMASK            45 drivers/iio/accel/stk8312.c #define STK8312_ALL_CHANNEL_MASK	GENMASK(2, 0)
GENMASK            44 drivers/iio/adc/ad7124.c #define AD7124_ADC_CTRL_PWR_MSK	GENMASK(7, 6)
GENMASK            46 drivers/iio/adc/ad7124.c #define AD7124_ADC_CTRL_MODE_MSK	GENMASK(5, 2)
GENMASK            52 drivers/iio/adc/ad7124.c #define AD7124_CHANNEL_SETUP_MSK	GENMASK(14, 12)
GENMASK            54 drivers/iio/adc/ad7124.c #define AD7124_CHANNEL_AINP_MSK	GENMASK(9, 5)
GENMASK            56 drivers/iio/adc/ad7124.c #define AD7124_CHANNEL_AINM_MSK	GENMASK(4, 0)
GENMASK            62 drivers/iio/adc/ad7124.c #define AD7124_CONFIG_REF_SEL_MSK	GENMASK(4, 3)
GENMASK            64 drivers/iio/adc/ad7124.c #define AD7124_CONFIG_PGA_MSK		GENMASK(2, 0)
GENMASK            66 drivers/iio/adc/ad7124.c #define AD7124_CONFIG_IN_BUFF_MSK	GENMASK(7, 6)
GENMASK            70 drivers/iio/adc/ad7124.c #define AD7124_FILTER_FS_MSK		GENMASK(10, 0)
GENMASK            62 drivers/iio/adc/ad7291.c #define AD7291_VOLTAGE_MASK		GENMASK(15, 8)
GENMASK            68 drivers/iio/adc/ad7291.c #define AD7291_VALUE_MASK		GENMASK(11, 0)
GENMASK           256 drivers/iio/adc/ad7298.c 			*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK           124 drivers/iio/adc/ad7476.c 			GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
GENMASK            19 drivers/iio/adc/ad7606_spi.c #define AD7616_OS_MASK			GENMASK(4, 2)
GENMASK            42 drivers/iio/adc/ad7606_spi.c #define AD7606_RANGE_CH_MSK(ch)		(GENMASK(3, 0) << (4 * ((ch) & 0x1)))
GENMASK            44 drivers/iio/adc/ad7606_spi.c 	((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1)))
GENMASK            64 drivers/iio/adc/ad7768-1.c #define AD7768_PWR_MCLK_DIV_MSK		GENMASK(5, 4)
GENMASK            66 drivers/iio/adc/ad7768-1.c #define AD7768_PWR_PWRMODE_MSK		GENMASK(1, 0)
GENMASK            70 drivers/iio/adc/ad7768-1.c #define AD7768_DIG_FIL_FIL_MSK		GENMASK(6, 4)
GENMASK            72 drivers/iio/adc/ad7768-1.c #define AD7768_DIG_FIL_DEC_MSK		GENMASK(2, 0)
GENMASK            76 drivers/iio/adc/ad7768-1.c #define AD7768_CONV_MODE_MSK		GENMASK(2, 0)
GENMASK            41 drivers/iio/adc/ad7780.c #define AD7780_PATTERN_MASK	GENMASK(1, 0)
GENMASK            44 drivers/iio/adc/ad7780.c #define AD7170_PATTERN_MASK	GENMASK(2, 0)
GENMASK           167 drivers/iio/adc/ad7887.c 		*val &= GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK            15 drivers/iio/adc/ad7949.c #define AD7949_MASK_CHANNEL_SEL		GENMASK(9, 7)
GENMASK            16 drivers/iio/adc/ad7949.c #define AD7949_MASK_TOTAL		GENMASK(13, 0)
GENMASK            94 drivers/iio/adc/ad7949.c 	int mask = GENMASK(ad7949_adc->resolution, 0);
GENMASK            69 drivers/iio/adc/ad799x.c #define AD7998_CYC_MASK				GENMASK(2, 0)
GENMASK           236 drivers/iio/adc/ad799x.c 		st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);
GENMASK           290 drivers/iio/adc/ad799x.c 			GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK           441 drivers/iio/adc/ad799x.c 	if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
GENMASK           470 drivers/iio/adc/ad799x.c 		GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK           250 drivers/iio/adc/aspeed_adc.c 	adc_engine_control_reg_val = GENMASK(31, 16) |
GENMASK            68 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_PRESCAL_MASK	GENMASK(15, 8)
GENMASK            71 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_MR_STARTUP_MASK	GENMASK(19, 16)
GENMASK           127 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_EMR_OSR_MASK		GENMASK(17, 16)
GENMASK           148 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_ACR_PENDETSENS_MASK        GENMASK(1, 0)
GENMASK           161 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TSMR_TSAV_MASK             GENMASK(5, 4)
GENMASK           165 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TSMR_TSFREQ_MASK           GENMASK(11, 8)
GENMASK           169 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TSMR_PENDBC_MASK           GENMASK(31, 28)
GENMASK           188 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
GENMASK           200 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_TRGR_TRGPER_MASK           GENMASK(31, 16)
GENMASK           233 drivers/iio/adc/at91-sama5d2_adc.c #define AT91_SAMA5D2_XYZ_MASK		GENMASK(11, 0)
GENMASK           361 drivers/iio/adc/at91_adc.c 	if (status & GENMASK(st->num_channels - 1, 0))
GENMASK           428 drivers/iio/adc/at91_adc.c 	if (status & GENMASK(st->num_channels - 1, 0))
GENMASK            24 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_EN1_MASK			GENMASK(7, 0)
GENMASK            26 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_EN2_MASK			(GENMASK(3, 2) | BIT(7))
GENMASK            27 drivers/iio/adc/axp20x_adc.c #define AXP22X_ADC_EN1_MASK			(GENMASK(7, 5) | BIT(0))
GENMASK            34 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_RATE_MASK			GENMASK(7, 6)
GENMASK            35 drivers/iio/adc/axp20x_adc.c #define AXP813_V_I_ADC_RATE_MASK		GENMASK(5, 4)
GENMASK            29 drivers/iio/adc/axp288_adc.c #define AXP288_ADC_TS_BIAS_MASK				GENMASK(5, 4)
GENMASK            34 drivers/iio/adc/axp288_adc.c #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK		GENMASK(1, 0)
GENMASK            30 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_CTRL_ADC_SEL_MASK		GENMASK(8, 5)
GENMASK            36 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_CTRL_ADC_CLKSEL_MASK	GENMASK(11, 10)
GENMASK            53 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_ADC_MASK			GENMASK(9, 0)
GENMASK            56 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK	GENMASK(15, 0)
GENMASK            58 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_ADC_STATUS_INT_EN_MASK	GENMASK(31, 16)
GENMASK            63 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_TSEN_MASK			GENMASK(9, 0)
GENMASK            70 drivers/iio/adc/berlin2-adc.c #define  BERLIN2_SM_TSEN_CTRL_TRIM_MASK		GENMASK(25, 22)
GENMASK            40 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_DATA_MASK		GENMASK(9, 0)
GENMASK            42 drivers/iio/adc/cc10001_adc.c #define CC10001_ADC_CH_MASK		GENMASK(2, 0)
GENMASK           324 drivers/iio/adc/cc10001_adc.c 	channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
GENMASK            66 drivers/iio/adc/ina2xx-adc.c #define INA2XX_MODE_MASK	GENMASK(3, 0)
GENMASK            69 drivers/iio/adc/ina2xx-adc.c #define INA219_PGA_MASK		GENMASK(12, 11)
GENMASK            77 drivers/iio/adc/ina2xx-adc.c #define INA226_AVG_MASK		GENMASK(11, 9)
GENMASK            81 drivers/iio/adc/ina2xx-adc.c #define INA219_ITB_MASK		GENMASK(10, 7)
GENMASK            83 drivers/iio/adc/ina2xx-adc.c #define INA226_ITB_MASK		GENMASK(8, 6)
GENMASK            87 drivers/iio/adc/ina2xx-adc.c #define INA219_ITS_MASK		GENMASK(6, 3)
GENMASK            89 drivers/iio/adc/ina2xx-adc.c #define INA226_ITS_MASK		GENMASK(5, 3)
GENMASK            37 drivers/iio/adc/max9611.c #define MAX9611_MUX_MASK		GENMASK(3, 0)
GENMASK            86 drivers/iio/adc/max9611.c #define MAX9611_TEMP_MASK		GENMASK(15, 7)
GENMASK           183 drivers/iio/adc/mcp320x.c 			raw |= GENMASK(31, 22); /* underrange or negative */
GENMASK            27 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_BUSY_MASK			GENMASK(30, 28)
GENMASK            33 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK		GENMASK(25, 21)
GENMASK            34 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK		GENMASK(20, 19)
GENMASK            35 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK		GENMASK(18, 16)
GENMASK            38 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK		GENMASK(13, 12)
GENMASK            41 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK		GENMASK(8, 4)
GENMASK            48 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK		GENMASK(26, 24)
GENMASK            50 drivers/iio/adc/meson_saradc.c 					(GENMASK(2, 0) << ((_chan) * 3))
GENMASK            56 drivers/iio/adc/meson_saradc.c 					(GENMASK(17, 16) << ((_chan) * 2))
GENMASK            60 drivers/iio/adc/meson_saradc.c 					(GENMASK(1, 0) << ((_chan) * 2))
GENMASK            68 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK	GENMASK(25, 23)
GENMASK            71 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK	GENMASK(20, 18)
GENMASK            72 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK	GENMASK(17, 16)
GENMASK            75 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK		GENMASK(9, 8)
GENMASK            76 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK		GENMASK(7, 0)
GENMASK            79 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK		GENMASK(25, 24)
GENMASK            82 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK		GENMASK(23, 16)
GENMASK            83 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK		GENMASK(9, 8)
GENMASK            84 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK		GENMASK(7, 0)
GENMASK            87 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK	GENMASK(23, 16)
GENMASK            88 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK	GENMASK(9, 0)
GENMASK            91 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK		GENMASK(14, 12)
GENMASK            92 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK		GENMASK(11, 0)
GENMASK           106 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK	GENMASK(25, 23)
GENMASK           114 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK	GENMASK(9, 7)
GENMASK           125 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK	GENMASK(25, 23)
GENMASK           133 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK	GENMASK(9, 7)
GENMASK           145 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK	GENMASK(25, 16)
GENMASK           147 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELTA_10_TS_C_MASK		GENMASK(14, 11)
GENMASK           149 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK	GENMASK(9, 0)
GENMASK           160 drivers/iio/adc/meson_saradc.c 	#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK	GENMASK(13, 8)
GENMASK           169 drivers/iio/adc/meson_saradc.c #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL			GENMASK(6, 0)
GENMASK           371 drivers/iio/adc/meson_saradc.c 	fifo_val &= GENMASK(priv->param->resolution - 1, 0);
GENMASK            45 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_CH_MASK		GENMASK(27, 24)
GENMASK            48 drivers/iio/adc/npcm_adc.c #define NPCM_ADCCON_DIV_MASK		GENMASK(8, 1)
GENMASK            49 drivers/iio/adc/npcm_adc.c #define NPCM_ADC_DATA_MASK(x)		((x) & GENMASK(9, 0))
GENMASK           107 drivers/iio/adc/rockchip_saradc.c 	info->last_val &= GENMASK(info->data->num_bits - 1, 0);
GENMASK            34 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_RUN_NUM_MASK		GENMASK(7, 4)
GENMASK            38 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_CHN_ID_MASK		GENMASK(4, 0)
GENMASK            39 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_SCALE_MASK		GENMASK(10, 8)
GENMASK            52 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_DATA_MASK		GENMASK(11, 0)
GENMASK            68 drivers/iio/adc/sc27xx_adc.c #define SC27XX_RATIO_DENOMINATOR_MASK	GENMASK(15, 0)
GENMASK            59 drivers/iio/adc/stm32-adc-core.h #define STM32F4_RES_MASK		GENMASK(25, 24)
GENMASK            66 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EXTEN_MASK		GENMASK(29, 28)
GENMASK            68 drivers/iio/adc/stm32-adc-core.h #define STM32F4_EXTSEL_MASK		GENMASK(27, 24)
GENMASK            81 drivers/iio/adc/stm32-adc-core.h #define STM32F4_ADC_ADCPRE_MASK		GENMASK(17, 16)
GENMASK           132 drivers/iio/adc/stm32-adc-core.h #define STM32H7_EXTEN_MASK		GENMASK(11, 10)
GENMASK           134 drivers/iio/adc/stm32-adc-core.h #define STM32H7_EXTSEL_MASK		GENMASK(9, 5)
GENMASK           136 drivers/iio/adc/stm32-adc-core.h #define STM32H7_RES_MASK		GENMASK(4, 2)
GENMASK           138 drivers/iio/adc/stm32-adc-core.h #define STM32H7_DMNGT_MASK		GENMASK(1, 0)
GENMASK           149 drivers/iio/adc/stm32-adc-core.h #define STM32H7_CALFACT_D_MASK		GENMASK(26, 16)
GENMASK           151 drivers/iio/adc/stm32-adc-core.h #define STM32H7_CALFACT_S_MASK		GENMASK(10, 0)
GENMASK           155 drivers/iio/adc/stm32-adc-core.h #define STM32H7_LINCALFACT_MASK		GENMASK(29, 0)
GENMASK           163 drivers/iio/adc/stm32-adc-core.h #define STM32H7_PRESC_MASK		GENMASK(21, 18)
GENMASK           165 drivers/iio/adc/stm32-adc-core.h #define STM32H7_CKMODE_MASK		GENMASK(17, 16)
GENMASK           264 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
GENMASK           266 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
GENMASK           267 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
GENMASK           268 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
GENMASK           269 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
GENMASK           270 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
GENMASK           271 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
GENMASK           272 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
GENMASK           273 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
GENMASK           274 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
GENMASK           275 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
GENMASK           276 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
GENMASK           277 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
GENMASK           278 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
GENMASK           279 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
GENMASK           280 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
GENMASK           281 drivers/iio/adc/stm32-adc.c 	{ STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
GENMASK           310 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(2, 0), 0 },
GENMASK           311 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(5, 3), 3 },
GENMASK           312 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(8, 6), 6 },
GENMASK           313 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(11, 9), 9 },
GENMASK           314 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(14, 12), 12 },
GENMASK           315 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(17, 15), 15 },
GENMASK           316 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(20, 18), 18 },
GENMASK           317 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(23, 21), 21 },
GENMASK           318 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(26, 24), 24 },
GENMASK           319 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(29, 27), 27 },
GENMASK           321 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(2, 0), 0 },
GENMASK           322 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(5, 3), 3 },
GENMASK           323 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(8, 6), 6 },
GENMASK           324 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(11, 9), 9 },
GENMASK           325 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(14, 12), 12 },
GENMASK           326 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(17, 15), 15 },
GENMASK           327 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(20, 18), 18 },
GENMASK           328 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(23, 21), 21 },
GENMASK           329 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(26, 24), 24 },
GENMASK           352 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
GENMASK           354 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
GENMASK           355 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
GENMASK           356 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
GENMASK           357 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
GENMASK           358 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
GENMASK           359 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
GENMASK           360 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
GENMASK           361 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
GENMASK           362 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
GENMASK           363 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
GENMASK           364 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
GENMASK           365 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
GENMASK           366 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
GENMASK           367 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
GENMASK           368 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
GENMASK           369 drivers/iio/adc/stm32-adc.c 	{ STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
GENMASK           401 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(2, 0), 0 },
GENMASK           402 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(5, 3), 3 },
GENMASK           403 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(8, 6), 6 },
GENMASK           404 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(11, 9), 9 },
GENMASK           405 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(14, 12), 12 },
GENMASK           406 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(17, 15), 15 },
GENMASK           407 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(20, 18), 18 },
GENMASK           408 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(23, 21), 21 },
GENMASK           409 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(26, 24), 24 },
GENMASK           410 drivers/iio/adc/stm32-adc.c 	{ 0, GENMASK(29, 27), 27 },
GENMASK           412 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(2, 0), 0 },
GENMASK           413 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(5, 3), 3 },
GENMASK           414 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(8, 6), 6 },
GENMASK           415 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(11, 9), 9 },
GENMASK           416 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(14, 12), 12 },
GENMASK           417 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(17, 15), 15 },
GENMASK           418 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(20, 18), 18 },
GENMASK           419 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(23, 21), 21 },
GENMASK           420 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(26, 24), 24 },
GENMASK           421 drivers/iio/adc/stm32-adc.c 	{ 1, GENMASK(29, 27), 27 },
GENMASK            47 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_SITP_MASK     GENMASK(1, 0)
GENMASK            49 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
GENMASK            59 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_DATMPX_MASK   GENMASK(13, 12)
GENMASK            61 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_DATPACK_MASK  GENMASK(15, 14)
GENMASK            63 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
GENMASK            71 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR2_DTRBS_MASK    GENMASK(7, 3)
GENMASK            73 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CHCFGR2_OFFSET_MASK   GENMASK(31, 8)
GENMASK            77 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSCDR_SCDT_MASK    GENMASK(7, 0)
GENMASK            79 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSCDR_BKSCD_MASK   GENMASK(15, 12)
GENMASK            81 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSCDR_AWFOSR_MASK  GENMASK(20, 16)
GENMASK            83 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSCDR_AWFORD_MASK  GENMASK(23, 22)
GENMASK           120 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JEXTSEL_MASK	GENMASK(12, 8)
GENMASK           122 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_JEXTEN_MASK	GENMASK(14, 13)
GENMASK           132 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR1_RCH_MASK	GENMASK(26, 24)
GENMASK           140 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_IE_MASK	GENMASK(6, 0)
GENMASK           156 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_EXCH_MASK	GENMASK(15, 8)
GENMASK           158 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_CR2_AWDCH_MASK	GENMASK(23, 16)
GENMASK           176 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_CKABF_MASK	GENMASK(23, 16)
GENMASK           178 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ISR_SCDF_MASK	GENMASK(31, 24)
GENMASK           186 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRCKABF_MASK	      GENMASK(23, 16)
GENMASK           191 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_ICR_CLRSCDF_MASK	      GENMASK(31, 24)
GENMASK           198 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_FCR_IOSR_MASK	GENMASK(7, 0)
GENMASK           200 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_FCR_FOSR_MASK	GENMASK(25, 16)
GENMASK           202 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_FCR_FORD_MASK	GENMASK(31, 29)
GENMASK           206 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_DATAR_CH_MASK	GENMASK(2, 0)
GENMASK           208 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_DATAR_DATA_MASK	GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
GENMASK           211 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWLTR_BKAWL_MASK	GENMASK(3, 0)
GENMASK           213 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWLTR_AWLT_MASK	GENMASK(31, 8)
GENMASK           217 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWHTR_BKAWH_MASK	GENMASK(3, 0)
GENMASK           219 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWHTR_AWHT_MASK	GENMASK(31, 8)
GENMASK           223 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSR_AWLTF_MASK	GENMASK(7, 0)
GENMASK           225 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWSR_AWHTF_MASK	GENMASK(15, 8)
GENMASK           229 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWCFR_AWLTF_MASK	GENMASK(7, 0)
GENMASK           231 drivers/iio/adc/stm32-dfsdm.h #define DFSDM_AWCFR_AWHTF_MASK	GENMASK(15, 8)
GENMASK            56 drivers/iio/adc/ti-adc108s102.c #define ADC108S102_RES_DATA(res)	((u16)res & GENMASK(11, 0))
GENMASK            50 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_COMP_QUE_MASK	GENMASK(1, 0)
GENMASK            54 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_DR_MASK	GENMASK(7, 5)
GENMASK            56 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_PGA_MASK	GENMASK(11, 9)
GENMASK            57 drivers/iio/adc/ti-ads1015.c #define ADS1015_CFG_MUX_MASK	GENMASK(14, 12)
GENMASK           142 drivers/iio/adc/ti-tlc4541.c 		*val &= GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK            19 drivers/iio/chemical/bme680.h #define   BME680_GAS_RANGE_MASK			GENMASK(3, 0)
GENMASK            22 drivers/iio/chemical/bme680.h #define   BME680_OSRS_HUMIDITY_MASK		GENMASK(2, 0)
GENMASK            25 drivers/iio/chemical/bme680.h #define   BME680_OSRS_TEMP_MASK			GENMASK(7, 5)
GENMASK            26 drivers/iio/chemical/bme680.h #define   BME680_OSRS_PRESS_MASK		GENMASK(4, 2)
GENMASK            27 drivers/iio/chemical/bme680.h #define   BME680_MODE_MASK			GENMASK(1, 0)
GENMASK            32 drivers/iio/chemical/bme680.h #define   BME680_FILTER_MASK			GENMASK(4, 2)
GENMASK            40 drivers/iio/chemical/bme680.h #define BME680_BIT_H1_DATA_MASK			GENMASK(3, 0)
GENMASK            43 drivers/iio/chemical/bme680.h #define   BME680_RHRANGE_MASK			GENMASK(5, 4)
GENMASK            46 drivers/iio/chemical/bme680.h #define   BME680_RSERROR_MASK			GENMASK(7, 4)
GENMASK            54 drivers/iio/chemical/bme680.h #define   BME680_NB_CONV_MASK			GENMASK(3, 0)
GENMASK           163 drivers/iio/chemical/sps30.c 	int mantissa = val & GENMASK(22, 0);
GENMASK           184 drivers/iio/chemical/sps30.c 	fraction = mantissa & GENMASK(shift - 1, 0);
GENMASK           250 drivers/iio/chemical/vz89x.c 		*val = le32_to_cpup((__le32 *) tmp) & GENMASK(23, 0);
GENMASK            24 drivers/iio/dac/ad5504.c #define AD5504_RES_MASK			GENMASK(11, 0)
GENMASK           400 drivers/iio/dac/ad5592r-base.c 			read_val &= GENMASK(11, 0);
GENMASK           136 drivers/iio/dac/ad5686.c 			GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK            52 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_RANGE_MSK		GENMASK(3, 0)
GENMASK            60 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_SR_CLOCK_MSK		GENMASK(12, 9)
GENMASK            62 drivers/iio/dac/ad5758.c #define AD5758_DAC_CONFIG_SR_STEP_MSK		GENMASK(15, 13)
GENMASK            73 drivers/iio/dac/ad5758.c #define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK	GENMASK(4, 0)
GENMASK            75 drivers/iio/dac/ad5758.c #define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK	GENMASK(6, 5)
GENMASK            79 drivers/iio/dac/ad5758.c #define AD5758_DCDC_CONFIG2_ILIMIT_MSK		GENMASK(3, 1)
GENMASK            24 drivers/iio/dac/ad5791.c #define AD5791_DAC_MASK			GENMASK(19, 0)
GENMASK           329 drivers/iio/dac/ad5791.c 		val &= GENMASK(chan->scan_type.realbits - 1, 0);
GENMASK            90 drivers/iio/dac/ltc1660.c 		if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
GENMASK            94 drivers/iio/dac/mcp4922.c 		if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
GENMASK            31 drivers/iio/frequency/adf4371.c #define ADF4371_FRAC2WORD_L_MSK		GENMASK(7, 1)
GENMASK            37 drivers/iio/frequency/adf4371.c #define ADF4371_FRAC2WORD_H_MSK		GENMASK(6, 0)
GENMASK            41 drivers/iio/frequency/adf4371.c #define ADF4371_MOD2WORD_MSK		GENMASK(5, 0)
GENMASK            45 drivers/iio/frequency/adf4371.c #define ADF4371_RF_DIV_SEL_MSK		GENMASK(6, 4)
GENMASK            53 drivers/iio/frequency/adf4371.c #define ADF4371_TIMEOUT_MSK		GENMASK(1, 0)
GENMASK            57 drivers/iio/frequency/adf4371.c #define ADF4371_VCO_ALC_TOUT_MSK	GENMASK(4, 0)
GENMASK           220 drivers/iio/gyro/st_gyro_core.c 			.mask = GENMASK(7, 6),
GENMASK           240 drivers/iio/gyro/st_gyro_core.c 			.mask = GENMASK(5, 4),
GENMASK           275 drivers/iio/gyro/st_gyro_core.c 				.mask = GENMASK(2, 0),
GENMASK            77 drivers/iio/health/afe440x.h #define AFE440X_CONTROL3_CLKDIV		GENMASK(2, 0)
GENMASK            74 drivers/iio/health/max30102.c #define MAX30102_REG_MODE_CONFIG_MODE_MASK	GENMASK(2, 0)
GENMASK            79 drivers/iio/health/max30102.c #define MAX30102_REG_MODE_CONTROL_SLOT_MASK	(GENMASK(6, 4) | GENMASK(2, 0))
GENMASK            29 drivers/iio/humidity/am2315.c #define AM2315_ALL_CHANNEL_MASK			GENMASK(1, 0)
GENMASK           116 drivers/iio/imu/adis16480.c #define ADIS16480_DRDY_SEL_MSK		GENMASK(1, 0)
GENMASK           122 drivers/iio/imu/adis16480.c #define ADIS16480_SYNC_SEL_MSK		GENMASK(5, 4)
GENMASK            39 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_ACCEL_CONFIG_ODR_MASK	GENMASK(3, 0)
GENMASK            40 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_ACCEL_CONFIG_BWP_MASK	GENMASK(6, 4)
GENMASK            49 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_GYRO_CONFIG_ODR_MASK	GENMASK(3, 0)
GENMASK            50 drivers/iio/imu/bmi160/bmi160_core.c #define BMI160_GYRO_CONFIG_BWP_MASK	GENMASK(5, 4)
GENMASK            50 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c #define ST_LSM6DSX_FIFO_MODE_MASK		GENMASK(2, 0)
GENMASK            51 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c #define ST_LSM6DSX_FIFO_ODR_MASK		GENMASK(6, 3)
GENMASK           116 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 5),
GENMASK           128 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 5),
GENMASK           142 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(4, 3),
GENMASK           153 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(4, 3),
GENMASK           189 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           201 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           215 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           226 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           238 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(2, 0),
GENMASK           242 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           250 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(11, 0),
GENMASK           254 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(11, 0),
GENMASK           273 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           303 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           315 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           329 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           340 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           352 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(2, 0),
GENMASK           356 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           364 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(11, 0),
GENMASK           368 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(11, 0),
GENMASK           387 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           426 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           438 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           452 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           463 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           475 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(2, 0),
GENMASK           479 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           487 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(10, 0),
GENMASK           491 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(10, 0),
GENMASK           510 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(5, 3),
GENMASK           543 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           555 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           569 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           580 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           592 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(3, 0),
GENMASK           596 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 4),
GENMASK           604 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(8, 0),
GENMASK           608 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(9, 0),
GENMASK           619 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 6),
GENMASK           637 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(1, 0),
GENMASK           675 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           687 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           701 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           712 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           724 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(3, 0),
GENMASK           728 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 4),
GENMASK           736 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(8, 0),
GENMASK           740 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(9, 0),
GENMASK           751 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 6),
GENMASK           784 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           796 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(7, 4),
GENMASK           810 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           821 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 					.mask = GENMASK(3, 2),
GENMASK           833 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(3, 0),
GENMASK           837 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 4),
GENMASK           845 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(8, 0),
GENMASK           849 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(9, 0),
GENMASK           860 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(7, 6),
GENMASK           878 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c 				.mask = GENMASK(1, 0),
GENMASK            38 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c #define ST_LS6DSX_READ_OP_MASK			GENMASK(2, 0)
GENMASK            52 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 				.mask = GENMASK(3, 2),
GENMASK            73 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c 				.mask = GENMASK(1, 0),
GENMASK            29 drivers/iio/light/bh1780.c #define BH1780_REVMASK		GENMASK(3,0)
GENMASK            30 drivers/iio/light/bh1780.c #define BH1780_POWMASK		GENMASK(1,0)
GENMASK            29 drivers/iio/light/cm3323.c #define CM3323_CONF_IT_MASK	GENMASK(6, 4)
GENMASK            37 drivers/iio/light/isl29125.c #define ISL29125_MODE_MASK GENMASK(2, 0)
GENMASK            38 drivers/iio/light/max44009.c #define MAX44009_CFG_TIM_MASK GENMASK(2, 0)
GENMASK            37 drivers/iio/light/pa12203001.c #define PA12203001_PX_NORMAL_MODE_MASK		GENMASK(7, 6)
GENMASK            38 drivers/iio/light/pa12203001.c #define PA12203001_AFSR_MASK		GENMASK(5, 4)
GENMASK            40 drivers/iio/light/rpr0521.c #define RPR0521_MODE_MEAS_TIME_MASK	GENMASK(3, 0)
GENMASK            41 drivers/iio/light/rpr0521.c #define RPR0521_ALS_DATA0_GAIN_MASK	GENMASK(5, 4)
GENMASK            43 drivers/iio/light/rpr0521.c #define RPR0521_ALS_DATA1_GAIN_MASK	GENMASK(3, 2)
GENMASK            45 drivers/iio/light/rpr0521.c #define RPR0521_PXS_GAIN_MASK		GENMASK(5, 4)
GENMASK            47 drivers/iio/light/rpr0521.c #define RPR0521_PXS_PERSISTENCE_MASK	GENMASK(3, 0)
GENMASK            67 drivers/iio/light/si1133.c #define SI1133_ADCPOST_POSTSHIFT_BITQTY(x) (x & GENMASK(2, 0)) << 3
GENMASK            43 drivers/iio/light/tcs3414.c #define TCS3414_INTEG_MASK GENMASK(1, 0)
GENMASK            48 drivers/iio/light/tcs3414.c #define TCS3414_GAIN_MASK GENMASK(5, 4)
GENMASK            79 drivers/iio/light/us5182d.c #define US5182D_OPMODE_MASK			GENMASK(5, 4)
GENMASK            41 drivers/iio/light/vcnl4035.c #define VCNL4035_ALS_IT_MASK		GENMASK(7, 5)
GENMASK            42 drivers/iio/light/vcnl4035.c #define VCNL4035_ALS_PERS_MASK		GENMASK(3, 2)
GENMASK            27 drivers/iio/light/veml6070.c #define VEML6070_COMMAND_IT	GENMASK(3, 2) /* bit mask integration time */
GENMASK            55 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_OPMODE			GENMASK(2, 1)
GENMASK            60 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_MASK_ODR			GENMASK(5, 3)
GENMASK            80 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_REG_REP_DATAMASK		GENMASK(7, 0)
GENMASK            41 drivers/iio/magnetometer/mag3110.c #define MAG3110_SYSMOD_MODE_MASK GENMASK(1, 0)
GENMASK            35 drivers/iio/pressure/dps310.c #define  DPS310_PRS_RATE_BITS	GENMASK(6, 4)
GENMASK            36 drivers/iio/pressure/dps310.c #define  DPS310_PRS_PRC_BITS	GENMASK(3, 0)
GENMASK            38 drivers/iio/pressure/dps310.c #define  DPS310_TMP_RATE_BITS	GENMASK(6, 4)
GENMASK            39 drivers/iio/pressure/dps310.c #define  DPS310_TMP_PRC_BITS	GENMASK(3, 0)
GENMASK            42 drivers/iio/pressure/dps310.c #define  DPS310_MEAS_CTRL_BITS	GENMASK(2, 0)
GENMASK           130 drivers/iio/pressure/dps310.c 	c1 = ((coef[1] & GENMASK(3, 0)) << 8) | coef[2];
GENMASK           141 drivers/iio/pressure/dps310.c 	c10 = ((coef[5] & GENMASK(3, 0)) << 16) | (coef[6] << 8) | coef[7];
GENMASK           171 drivers/iio/pressure/dps310.c 	return BIT(val & GENMASK(2, 0));
GENMASK           187 drivers/iio/pressure/dps310.c 	return BIT(val & GENMASK(2, 0));
GENMASK            38 drivers/iio/proximity/rfd77402.c #define RFD77402_STATUS_PM_MASK	GENMASK(4, 0)
GENMASK            44 drivers/iio/proximity/rfd77402.c #define RFD77402_RESULT_DIST_MASK	GENMASK(12, 2)
GENMASK            45 drivers/iio/proximity/rfd77402.c #define RFD77402_RESULT_ERR_MASK	GENMASK(14, 13)
GENMASK            62 drivers/iio/proximity/sx9500.c #define SX9500_SCAN_PERIOD_MASK		GENMASK(6, 4)
GENMASK            74 drivers/iio/proximity/sx9500.c #define SX9500_COMPSTAT_MASK		GENMASK(3, 0)
GENMASK            77 drivers/iio/proximity/sx9500.c #define SX9500_CHAN_MASK		GENMASK(SX9500_NUM_CHANNELS - 1, 0)
GENMASK            25 drivers/iio/proximity/vl53l0x-i2c.c #define VL_REG_SYSRANGE_MODE_MASK			GENMASK(3, 0)
GENMASK            25 drivers/iio/temperature/max31856.c #define MAX31856_CR0_OCFAULT_MASK  GENMASK(5, 4)
GENMASK            26 drivers/iio/temperature/max31856.c #define MAX31856_TC_TYPE_MASK      GENMASK(3, 0)
GENMASK            60 drivers/iio/temperature/mlx90632.c #define   MLX90632_CFG_PWR_MASK		GENMASK(2, 1) /* PowerMode Mask */
GENMASK            73 drivers/iio/temperature/mlx90632.c #define   MLX90632_STAT_CYCLE_POS	GENMASK(6, 2) /* Data position */
GENMASK            85 drivers/iio/temperature/mlx90632.c #define MLX90632_DSP_MASK	GENMASK(7, 0) /* DSP version in EE_VERSION */
GENMASK            36 drivers/iio/temperature/tmp006.c #define TMP006_CONFIG_MOD_MASK GENMASK(14, 12)
GENMASK            38 drivers/iio/temperature/tmp006.c #define TMP006_CONFIG_CR_MASK GENMASK(11, 9)
GENMASK            45 drivers/iio/temperature/tmp007.c #define TMP007_CONFIG_CR_MASK GENMASK(11, 9)
GENMASK           155 drivers/infiniband/core/umem.c 	if (WARN_ON(!(pgsz_bitmap & GENMASK(PAGE_SHIFT, 0))))
GENMASK           779 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK      GENMASK(4, 0)
GENMASK           789 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK    GENMASK(4, 0)
GENMASK           792 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h #define EFA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
GENMASK           122 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
GENMASK           130 drivers/infiniband/hw/efa/efa_admin_defs.h #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
GENMASK           906 drivers/infiniband/hw/efa/efa_com.c 	addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0);
GENMASK           907 drivers/infiniband/hw/efa/efa_com.c 	addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0);
GENMASK            17 drivers/infiniband/hw/efa/efa_verbs.c #define EFA_MMAP_PAGE_MASK GENMASK(EFA_MMAP_FLAG_SHIFT - 1, 0)
GENMASK           171 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_V1_CONS_IDX_M GENMASK(15, 0)
GENMASK           174 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_CEQE_CEQE_COMP_CQN_M GENMASK(31, 16)
GENMASK           177 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M GENMASK(23, 16)
GENMASK           180 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M GENMASK(30, 24)
GENMASK           185 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M GENMASK(23, 0)
GENMASK           188 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M GENMASK(27, 25)
GENMASK           191 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M GENMASK(15, 0)
GENMASK           194 drivers/infiniband/hw/hns/hns_roce_hw_v1.h #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)
GENMASK           292 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
GENMASK           303 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
GENMASK           306 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
GENMASK           309 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
GENMASK           312 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
GENMASK           315 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
GENMASK           318 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
GENMASK           321 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
GENMASK           324 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
GENMASK           327 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
GENMASK           330 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
GENMASK           333 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
GENMASK           336 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
GENMASK           339 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
GENMASK           342 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
GENMASK           347 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define	V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
GENMASK           350 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define	V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
GENMASK           353 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
GENMASK           356 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
GENMASK           359 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define	V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
GENMASK           381 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
GENMASK           384 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
GENMASK           387 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
GENMASK           390 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
GENMASK           393 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
GENMASK           396 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
GENMASK           399 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
GENMASK           402 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
GENMASK           405 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
GENMASK           408 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
GENMASK           411 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
GENMASK           414 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
GENMASK           417 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
GENMASK           420 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
GENMASK           423 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
GENMASK           426 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
GENMASK           429 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
GENMASK           432 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
GENMASK           435 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
GENMASK           438 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
GENMASK           443 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
GENMASK           526 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
GENMASK           529 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
GENMASK           532 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_4_SQPN_M  GENMASK(31, 8)
GENMASK           535 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
GENMASK           538 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
GENMASK           543 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
GENMASK           546 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
GENMASK           549 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
GENMASK           552 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
GENMASK           555 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
GENMASK           558 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
GENMASK           561 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
GENMASK           564 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
GENMASK           567 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
GENMASK           570 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
GENMASK           573 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
GENMASK           576 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
GENMASK           579 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
GENMASK           582 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
GENMASK           585 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
GENMASK           588 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
GENMASK           597 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
GENMASK           600 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
GENMASK           603 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
GENMASK           606 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
GENMASK           614 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
GENMASK           617 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
GENMASK           620 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
GENMASK           627 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
GENMASK           632 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
GENMASK           635 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
GENMASK           649 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
GENMASK           652 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
GENMASK           655 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
GENMASK           658 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
GENMASK           661 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
GENMASK           664 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
GENMASK           667 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
GENMASK           670 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
GENMASK           673 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
GENMASK           680 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
GENMASK           685 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
GENMASK           688 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
GENMASK           691 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
GENMASK           694 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
GENMASK           697 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
GENMASK           700 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
GENMASK           705 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
GENMASK           708 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
GENMASK           711 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
GENMASK           714 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
GENMASK           719 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
GENMASK           722 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
GENMASK           725 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
GENMASK           728 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
GENMASK           731 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
GENMASK           734 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
GENMASK           737 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
GENMASK           740 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
GENMASK           747 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
GENMASK           754 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
GENMASK           757 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
GENMASK           764 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
GENMASK           767 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
GENMASK           770 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
GENMASK           773 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
GENMASK           776 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
GENMASK           779 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
GENMASK           782 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
GENMASK           785 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
GENMASK           788 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
GENMASK           791 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
GENMASK           794 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
GENMASK           797 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
GENMASK           806 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
GENMASK           809 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
GENMASK           812 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
GENMASK           815 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
GENMASK           818 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
GENMASK           821 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
GENMASK           824 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
GENMASK           827 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
GENMASK           830 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
GENMASK           833 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
GENMASK           836 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
GENMASK           843 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
GENMASK           846 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
GENMASK           849 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
GENMASK           852 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
GENMASK           855 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
GENMASK           858 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
GENMASK           864 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
GENMASK           869 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
GENMASK           878 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
GENMASK           883 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
GENMASK           886 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
GENMASK           889 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
GENMASK           910 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
GENMASK           919 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
GENMASK           922 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
GENMASK           925 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
GENMASK           928 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
GENMASK           931 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
GENMASK           934 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_28_SMAC_4_M	GENMASK(7, 0)
GENMASK           937 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_28_SMAC_5_M	GENMASK(15, 8)
GENMASK           940 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
GENMASK           943 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
GENMASK           948 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
GENMASK           951 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
GENMASK           954 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
GENMASK           980 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
GENMASK           983 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
GENMASK           986 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
GENMASK           989 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
GENMASK          1008 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
GENMASK          1023 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
GENMASK          1026 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
GENMASK          1031 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
GENMASK          1034 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
GENMASK          1037 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
GENMASK          1040 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
GENMASK          1043 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
GENMASK          1046 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
GENMASK          1049 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
GENMASK          1057 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
GENMASK          1060 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
GENMASK          1063 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
GENMASK          1066 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
GENMASK          1087 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
GENMASK          1096 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
GENMASK          1099 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
GENMASK          1102 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
GENMASK          1105 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
GENMASK          1108 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
GENMASK          1111 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
GENMASK          1114 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
GENMASK          1117 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
GENMASK          1120 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
GENMASK          1123 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
GENMASK          1126 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
GENMASK          1133 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
GENMASK          1136 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
GENMASK          1139 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
GENMASK          1142 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
GENMASK          1145 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
GENMASK          1148 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
GENMASK          1151 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
GENMASK          1154 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
GENMASK          1170 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
GENMASK          1195 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
GENMASK          1198 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
GENMASK          1201 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
GENMASK          1209 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M	GENMASK(7, 4)
GENMASK          1261 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
GENMASK          1264 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
GENMASK          1267 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
GENMASK          1270 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
GENMASK          1280 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
GENMASK          1283 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
GENMASK          1291 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
GENMASK          1294 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
GENMASK          1306 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
GENMASK          1309 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
GENMASK          1312 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
GENMASK          1315 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
GENMASK          1318 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
GENMASK          1321 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
GENMASK          1324 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
GENMASK          1327 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
GENMASK          1330 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
GENMASK          1333 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
GENMASK          1345 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
GENMASK          1348 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
GENMASK          1351 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
GENMASK          1354 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
GENMASK          1357 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
GENMASK          1360 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
GENMASK          1363 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
GENMASK          1366 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
GENMASK          1376 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
GENMASK          1379 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
GENMASK          1382 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
GENMASK          1385 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
GENMASK          1397 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
GENMASK          1400 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
GENMASK          1403 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
GENMASK          1406 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
GENMASK          1409 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
GENMASK          1412 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
GENMASK          1415 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
GENMASK          1418 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
GENMASK          1421 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
GENMASK          1424 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
GENMASK          1436 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
GENMASK          1439 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
GENMASK          1442 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
GENMASK          1445 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
GENMASK          1448 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
GENMASK          1451 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
GENMASK          1454 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
GENMASK          1457 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
GENMASK          1460 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
GENMASK          1472 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
GENMASK          1502 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
GENMASK          1505 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
GENMASK          1508 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
GENMASK          1511 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
GENMASK          1514 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
GENMASK          1517 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
GENMASK          1520 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
GENMASK          1523 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
GENMASK          1526 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
GENMASK          1529 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
GENMASK          1532 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
GENMASK          1535 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
GENMASK          1538 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
GENMASK          1541 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
GENMASK          1544 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
GENMASK          1555 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
GENMASK          1558 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
GENMASK          1567 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
GENMASK          1570 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
GENMASK          1623 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
GENMASK          1626 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
GENMASK          1698 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
GENMASK          1700 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
GENMASK          1703 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
GENMASK          1704 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
GENMASK          1705 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
GENMASK          1706 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
GENMASK          1710 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
GENMASK          1713 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
GENMASK          1716 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
GENMASK          1719 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
GENMASK          1722 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
GENMASK          1725 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
GENMASK          1728 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
GENMASK          1732 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
GENMASK          1735 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
GENMASK          1738 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
GENMASK          1742 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
GENMASK          1745 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
GENMASK          1749 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
GENMASK          1753 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
GENMASK          1757 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
GENMASK          1761 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
GENMASK          1764 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
GENMASK          1767 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
GENMASK          1771 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
GENMASK          1775 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
GENMASK          1778 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
GENMASK          1782 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
GENMASK          1786 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
GENMASK          1789 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
GENMASK          1792 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
GENMASK          1795 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
GENMASK          1798 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_EQ_DB_CMD_M	GENMASK(17, 16)
GENMASK          1801 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_EQ_DB_TAG_M	GENMASK(7, 0)
GENMASK          1804 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
GENMASK          1807 drivers/infiniband/hw/hns/hns_roce_hw_v2.h #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
GENMASK            33 drivers/input/keyboard/tm2-touchkey.c #define TM2_TOUCHKEY_BIT_KEYCODE	GENMASK(2, 0)
GENMASK            13 drivers/input/misc/sc27xx-vibra.c #define CUR_DRV_CAL_SEL		GENMASK(13, 12)
GENMASK           765 drivers/input/mouse/synaptics.c 	unsigned int ext_mask = GENMASK(ext_bits - 1, 0);
GENMASK            35 drivers/input/mouse/synaptics.h #define SYN_MODEL_SENSOR(m)		(((m) & GENMASK(21, 16)) >> 16)
GENMASK            36 drivers/input/mouse/synaptics.h #define SYN_MODEL_HARDWARE(m)		(((m) & GENMASK(15, 9)) >> 9)
GENMASK            40 drivers/input/mouse/synaptics.h #define SYN_MODEL_GEOMETRY(m)		((m) & GENMASK(3, 0))
GENMASK            50 drivers/input/mouse/synaptics.h #define SYN_CAP_SUBMODEL_ID(c)		(((c) & GENMASK(15, 8)) >> 8)
GENMASK            51 drivers/input/mouse/synaptics.h #define SYN_EXT_CAP_REQUESTS(c)		(((c) & GENMASK(22, 20)) >> 20)
GENMASK            52 drivers/input/mouse/synaptics.h #define SYN_CAP_MB_MASK			GENMASK(15, 12)
GENMASK            54 drivers/input/mouse/synaptics.h #define SYN_CAP_PRODUCT_ID(ec)		(((ec) & GENMASK(23, 16)) >> 16)
GENMASK           126 drivers/input/mouse/synaptics.h #define SYN_ID_MODEL(i)			(((i) & GENMASK(7, 4)) >> 4)
GENMASK           127 drivers/input/mouse/synaptics.h #define SYN_ID_MAJOR(i)			(((i) & GENMASK(3, 0)) >> 0)
GENMASK           128 drivers/input/mouse/synaptics.h #define SYN_ID_MINOR(i)			(((i) & GENMASK(23, 16)) >> 16)
GENMASK           130 drivers/input/mouse/synaptics.h #define SYN_ID_IS_SYNAPTICS(i)		(((i) & GENMASK(15, 8)) == 0x004700U)
GENMASK            23 drivers/input/touchscreen/resistive-adc-touch.c #define GRTS_MAX_POS_MASK				GENMASK(11, 0)
GENMASK            39 drivers/iommu/arm-smmu-v3.c #define IDR0_ST_LVL			GENMASK(28, 27)
GENMASK            41 drivers/iommu/arm-smmu-v3.c #define IDR0_STALL_MODEL		GENMASK(25, 24)
GENMASK            44 drivers/iommu/arm-smmu-v3.c #define IDR0_TTENDIAN			GENMASK(22, 21)
GENMASK            57 drivers/iommu/arm-smmu-v3.c #define IDR0_TTF			GENMASK(3, 2)
GENMASK            67 drivers/iommu/arm-smmu-v3.c #define IDR1_CMDQS			GENMASK(25, 21)
GENMASK            68 drivers/iommu/arm-smmu-v3.c #define IDR1_EVTQS			GENMASK(20, 16)
GENMASK            69 drivers/iommu/arm-smmu-v3.c #define IDR1_PRIQS			GENMASK(15, 11)
GENMASK            70 drivers/iommu/arm-smmu-v3.c #define IDR1_SSIDSIZE			GENMASK(10, 6)
GENMASK            71 drivers/iommu/arm-smmu-v3.c #define IDR1_SIDSIZE			GENMASK(5, 0)
GENMASK            74 drivers/iommu/arm-smmu-v3.c #define IDR5_STALL_MAX			GENMASK(31, 16)
GENMASK            78 drivers/iommu/arm-smmu-v3.c #define IDR5_OAS			GENMASK(2, 0)
GENMASK            86 drivers/iommu/arm-smmu-v3.c #define IDR5_VAX			GENMASK(11, 10)
GENMASK            99 drivers/iommu/arm-smmu-v3.c #define CR1_TABLE_SH			GENMASK(11, 10)
GENMASK           100 drivers/iommu/arm-smmu-v3.c #define CR1_TABLE_OC			GENMASK(9, 8)
GENMASK           101 drivers/iommu/arm-smmu-v3.c #define CR1_TABLE_IC			GENMASK(7, 6)
GENMASK           102 drivers/iommu/arm-smmu-v3.c #define CR1_QUEUE_SH			GENMASK(5, 4)
GENMASK           103 drivers/iommu/arm-smmu-v3.c #define CR1_QUEUE_OC			GENMASK(3, 2)
GENMASK           104 drivers/iommu/arm-smmu-v3.c #define CR1_QUEUE_IC			GENMASK(1, 0)
GENMASK           148 drivers/iommu/arm-smmu-v3.c #define STRTAB_BASE_CFG_FMT		GENMASK(17, 16)
GENMASK           151 drivers/iommu/arm-smmu-v3.c #define STRTAB_BASE_CFG_SPLIT		GENMASK(10, 6)
GENMASK           152 drivers/iommu/arm-smmu-v3.c #define STRTAB_BASE_CFG_LOG2SIZE	GENMASK(5, 0)
GENMASK           174 drivers/iommu/arm-smmu-v3.c #define MSI_CFG2_SH			GENMASK(5, 4)
GENMASK           175 drivers/iommu/arm-smmu-v3.c #define MSI_CFG2_MEMATTR		GENMASK(3, 0)
GENMASK           194 drivers/iommu/arm-smmu-v3.c #define Q_BASE_LOG2SIZE			GENMASK(4, 0)
GENMASK           304 drivers/iommu/arm-smmu-v3.c #define CMDQ_CONS_ERR			GENMASK(30, 24)
GENMASK          1119 drivers/iommu/arm-smmu-v3.c 		mask = GENMASK(limit - 1, sbidx);
GENMASK            27 drivers/iommu/arm-smmu.h #define sCR0_BSU			GENMASK(15, 14)
GENMASK            51 drivers/iommu/arm-smmu.h #define ID0_NUMIRPT			GENMASK(23, 16)
GENMASK            53 drivers/iommu/arm-smmu.h #define ID0_NUMSIDB			GENMASK(12, 9)
GENMASK            55 drivers/iommu/arm-smmu.h #define ID0_NUMSMRG			GENMASK(7, 0)
GENMASK            59 drivers/iommu/arm-smmu.h #define ID1_NUMPAGENDXB			GENMASK(30, 28)
GENMASK            60 drivers/iommu/arm-smmu.h #define ID1_NUMS2CB			GENMASK(23, 16)
GENMASK            61 drivers/iommu/arm-smmu.h #define ID1_NUMCB			GENMASK(7, 0)
GENMASK            68 drivers/iommu/arm-smmu.h #define ID2_UBS				GENMASK(11, 8)
GENMASK            69 drivers/iommu/arm-smmu.h #define ID2_OAS				GENMASK(7, 4)
GENMASK            70 drivers/iommu/arm-smmu.h #define ID2_IAS				GENMASK(3, 0)
GENMASK            78 drivers/iommu/arm-smmu.h #define ID7_MAJOR			GENMASK(7, 4)
GENMASK            79 drivers/iommu/arm-smmu.h #define ID7_MINOR			GENMASK(3, 0)
GENMASK            98 drivers/iommu/arm-smmu.h #define SMR_MASK			GENMASK(31, 16)
GENMASK            99 drivers/iommu/arm-smmu.h #define SMR_ID				GENMASK(15, 0)
GENMASK           102 drivers/iommu/arm-smmu.h #define S2CR_PRIVCFG			GENMASK(25, 24)
GENMASK           109 drivers/iommu/arm-smmu.h #define S2CR_TYPE			GENMASK(17, 16)
GENMASK           116 drivers/iommu/arm-smmu.h #define S2CR_CBNDX			GENMASK(7, 0)
GENMASK           120 drivers/iommu/arm-smmu.h #define CBAR_IRPTNDX			GENMASK(31, 24)
GENMASK           121 drivers/iommu/arm-smmu.h #define CBAR_TYPE			GENMASK(17, 16)
GENMASK           128 drivers/iommu/arm-smmu.h #define CBAR_S1_MEMATTR			GENMASK(15, 12)
GENMASK           130 drivers/iommu/arm-smmu.h #define CBAR_S1_BPSHCFG			GENMASK(9, 8)
GENMASK           132 drivers/iommu/arm-smmu.h #define CBAR_VMID			GENMASK(7, 0)
GENMASK           137 drivers/iommu/arm-smmu.h #define CBA2R_VMID16			GENMASK(31, 16)
GENMASK           156 drivers/iommu/arm-smmu.h #define TCR2_SEP			GENMASK(17, 15)
GENMASK            31 drivers/iommu/mtk_iommu.c #define MMU_PT_ADDR_MASK			GENMASK(31, 7)
GENMASK            79 drivers/iommu/mtk_iommu.c #define F_REG_MMU0_FAULT_MASK			GENMASK(6, 0)
GENMASK            80 drivers/iommu/mtk_iommu.c #define F_REG_MMU1_FAULT_MASK			GENMASK(13, 7)
GENMASK            31 drivers/iommu/tegra-gart.c #define GART_PAGE_MASK		GENMASK(30, GART_PAGE_SHIFT)
GENMASK            27 drivers/irqchip/irq-atmel-aic-common.c #define AT91_AIC_PRIOR			GENMASK(2, 0)
GENMASK            31 drivers/irqchip/irq-atmel-aic-common.c #define AT91_AIC_SRCTYPE		GENMASK(6, 5)
GENMASK            38 drivers/irqchip/irq-davinci-cp-intc.c #define DAVINCI_CP_INTC_PRI_INDX_MASK		GENMASK(9, 0)
GENMASK          3513 drivers/irqchip/irq-gic-v3-its.c 	devid = GENMASK(its->device_ids - 1, 0);
GENMASK           124 drivers/irqchip/irq-gic-v3.c 	case 8192 ... GENMASK(23, 0):
GENMASK          1457 drivers/irqchip/irq-gic-v3.c 		d->rdists.gicd_typer &= ~GENMASK(9, 8);
GENMASK            62 drivers/irqchip/irq-renesas-rza1.c 		writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
GENMASK            38 drivers/leds/leds-cr0014114.c #define CR_MAX_BRIGHTNESS	GENMASK(6, 0)
GENMASK           300 drivers/leds/leds-is31fl32xx.c 		    GENMASK(cdef->enable_bits_per_led_control_register-1, 0);
GENMASK            20 drivers/leds/leds-max77650.c #define MAX77650_LED_BR_MASK		GENMASK(4, 0)
GENMASK            21 drivers/leds/leds-max77650.c #define MAX77650_LED_EN_MASK		GENMASK(7, 6)
GENMASK            28 drivers/leds/leds-max77650.c #define MAX77650_LED_ENABLE		GENMASK(7, 6)
GENMASK            33 drivers/leds/leds-max77650.c #define MAX77650_LED_B_DEFAULT		GENMASK(3, 0)
GENMASK            25 drivers/leds/leds-mlxreg.c #define MLXREG_LED_CAPABILITY_CLEAR	GENMASK(31, 8) /* Clear mask */
GENMASK            31 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_DUTY_MASK	GENMASK(15, 0)
GENMASK            32 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_MOD_MASK		GENMASK(7, 0)
GENMASK            35 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_CURVE_L_MASK	GENMASK(7, 0)
GENMASK            36 drivers/leds/leds-sc27xx-bltc.c #define SC27XX_CURVE_H_MASK	GENMASK(15, 8)
GENMASK           483 drivers/mailbox/mtk-cmdq-mailbox.c 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
GENMASK            28 drivers/mailbox/stm32-ipcc.c #define IPCFGR_CHAN_MASK	GENMASK(7, 0)
GENMASK            31 drivers/mailbox/stm32-ipcc.c #define VER_MINREV_MASK		GENMASK(3, 0)
GENMASK            32 drivers/mailbox/stm32-ipcc.c #define VER_MAJREV_MASK		GENMASK(7, 4)
GENMASK            34 drivers/mailbox/stm32-ipcc.c #define RX_BIT_MASK		GENMASK(15, 0)
GENMASK            37 drivers/mailbox/stm32-ipcc.c #define TX_BIT_MASK		GENMASK(31, 16)
GENMASK            18 drivers/media/dvb-frontends/cxd2880/cxd2880_common.c 		return (int)(GENMASK(31, bitlen) | value);
GENMASK            20 drivers/media/dvb-frontends/cxd2880/cxd2880_common.c 		return (int)(GENMASK(bitlen - 1, 0) & value);
GENMASK            33 drivers/media/dvb-frontends/lnbh29.c #define LNBH29_VSEL_MASK      GENMASK(2, 0)
GENMASK            68 drivers/media/dvb-frontends/mn88443x.c #define   TSSET1_TSASEL_MASK                          GENMASK(4, 3)
GENMASK            72 drivers/media/dvb-frontends/mn88443x.c #define   TSSET1_TSBSEL_MASK                          GENMASK(2, 1)
GENMASK            78 drivers/media/dvb-frontends/mn88443x.c #define   TSSET3_INTASEL_MASK                         GENMASK(7, 6)
GENMASK            82 drivers/media/dvb-frontends/mn88443x.c #define   TSSET3_INTBSEL_MASK                         GENMASK(5, 4)
GENMASK            88 drivers/media/dvb-frontends/mn88443x.c #define   PWDSET_OFDMPD_MASK                          GENMASK(3, 2)
GENMASK            90 drivers/media/dvb-frontends/mn88443x.c #define   PWDSET_PSKPD_MASK                           GENMASK(1, 0)
GENMASK            94 drivers/media/dvb-frontends/mn88443x.c #define   MDSET_T_MDAUTO_MASK                         GENMASK(7, 4)
GENMASK            97 drivers/media/dvb-frontends/mn88443x.c #define   MDSET_T_FFTS_MASK                           GENMASK(3, 2)
GENMASK           101 drivers/media/dvb-frontends/mn88443x.c #define   MDSET_T_GI_MASK                             GENMASK(1, 0)
GENMASK           108 drivers/media/dvb-frontends/mn88443x.c #define   ADCSET1_T_REFSEL_MASK                       GENMASK(1, 0)
GENMASK           123 drivers/media/dvb-frontends/mn88443x.c #define   MDRD_T_SEGID_MASK                           GENMASK(5, 4)
GENMASK           127 drivers/media/dvb-frontends/mn88443x.c #define   MDRD_T_FFTS_MASK                            GENMASK(3, 2)
GENMASK           131 drivers/media/dvb-frontends/mn88443x.c #define   MDRD_T_GI_MASK                              GENMASK(1, 0)
GENMASK           137 drivers/media/dvb-frontends/mn88443x.c #define   SSEQRD_T_SSEQSTRD_MASK                      GENMASK(3, 0)
GENMASK           324 drivers/media/i2c/adv748x/adv748x.h #define ADV748X_SDP_FRP_MASK		GENMASK(3, 1)
GENMASK           312 drivers/media/i2c/max2175.c 	return (val & GENMASK(msb, lsb)) >> lsb;
GENMASK           355 drivers/media/i2c/max2175.c 	int ret = regmap_update_bits(ctx->regmap, idx, GENMASK(msb, lsb),
GENMASK           130 drivers/media/i2c/mt9m111.c #define MT9M111_TPG_SEL_MASK		GENMASK(2, 0)
GENMASK           131 drivers/media/i2c/mt9m111.c #define MT9M111_EFFECTS_MODE_MASK	GENMASK(2, 0)
GENMASK           133 drivers/media/i2c/mt9m111.c #define MT9M111_RM_SKIP2_MASK		GENMASK(3, 2)
GENMASK            70 drivers/media/i2c/mt9v111.c #define		MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_MASK	GENMASK(2, 0)
GENMASK            77 drivers/media/i2c/mt9v111.c #define MT9V111_IFP_DECIMATION_MASK			GENMASK(9, 0)
GENMASK            86 drivers/media/i2c/mt9v111.c #define		MT9V111_CORE_R05_MAX_HBLANK		GENMASK(9, 0)
GENMASK            90 drivers/media/i2c/mt9v111.c #define		MT9V111_CORE_R06_MAX_VBLANK		GENMASK(11, 0)
GENMASK            95 drivers/media/i2c/mt9v111.c #define		MT9V111_CORE_R09_PIXEL_INT_MASK		GENMASK(11, 0)
GENMASK           371 drivers/media/pci/tw686x/tw686x-video.c 	mask = GENMASK(max_fps - 1, 0);
GENMASK            68 drivers/media/platform/aspeed-video.c #define  VE_SEQ_CTRL_COMP_FMT		GENMASK(11, 10)
GENMASK            89 drivers/media/platform/aspeed-video.c #define  VE_CTRL_CAPTURE_FMT		GENMASK(7, 6)
GENMASK            92 drivers/media/platform/aspeed-video.c #define  VE_CTRL_CLK_DELAY		GENMASK(11, 9)
GENMASK            95 drivers/media/platform/aspeed-video.c #define  VE_CTRL_FRC			GENMASK(23, 16)
GENMASK            99 drivers/media/platform/aspeed-video.c #define  VE_TGS_FIRST			GENMASK(28, 16)
GENMASK           100 drivers/media/platform/aspeed-video.c #define  VE_TGS_LAST			GENMASK(12, 0)
GENMASK           119 drivers/media/platform/aspeed-video.c #define  VE_STREAM_BUF_SIZE_N_PACKETS	GENMASK(5, 3)
GENMASK           120 drivers/media/platform/aspeed-video.c #define  VE_STREAM_BUF_SIZE_P_SIZE	GENMASK(2, 0)
GENMASK           128 drivers/media/platform/aspeed-video.c #define  VE_COMP_CTRL_DCT_CHR		GENMASK(10, 6)
GENMASK           129 drivers/media/platform/aspeed-video.c #define  VE_COMP_CTRL_DCT_LUM		GENMASK(15, 11)
GENMASK           132 drivers/media/platform/aspeed-video.c #define  VE_COMP_CTRL_ENCODE		GENMASK(21, 20)
GENMASK           133 drivers/media/platform/aspeed-video.c #define  VE_COMP_CTRL_HQ_DCT_CHR	GENMASK(26, 22)
GENMASK           134 drivers/media/platform/aspeed-video.c #define  VE_COMP_CTRL_HQ_DCT_LUM	GENMASK(31, 27)
GENMASK           139 drivers/media/platform/aspeed-video.c #define  VE_SRC_LR_EDGE_DET_LEFT	GENMASK(11, 0)
GENMASK           145 drivers/media/platform/aspeed-video.c #define  VE_SRC_LR_EDGE_DET_RT		GENMASK(27, VE_SRC_LR_EDGE_DET_RT_SHF)
GENMASK           149 drivers/media/platform/aspeed-video.c #define  VE_SRC_TB_EDGE_DET_TOP		GENMASK(12, 0)
GENMASK           151 drivers/media/platform/aspeed-video.c #define  VE_SRC_TB_EDGE_DET_BOT		GENMASK(28, VE_SRC_TB_EDGE_DET_BOT_SHF)
GENMASK           154 drivers/media/platform/aspeed-video.c #define  VE_MODE_DETECT_H_PIXELS	GENMASK(11, 0)
GENMASK           156 drivers/media/platform/aspeed-video.c #define  VE_MODE_DETECT_V_LINES		GENMASK(27, VE_MODE_DETECT_V_LINES_SHF)
GENMASK           161 drivers/media/platform/aspeed-video.c #define  VE_SYNC_STATUS_HSYNC		GENMASK(11, 0)
GENMASK           163 drivers/media/platform/aspeed-video.c #define  VE_SYNC_STATUS_VSYNC		GENMASK(27, VE_SYNC_STATUS_VSYNC_SHF)
GENMASK            31 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
GENMASK            38 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG0_BPS_MASK   GENMASK(30, 28)
GENMASK            47 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG1_COLMIN_MASK	GENMASK(15, 0)
GENMASK            49 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG1_COLMAX_MASK	GENMASK(31, 16)
GENMASK            55 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG2_ROWMIN_MASK	GENMASK(15, 0)
GENMASK            57 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_PFE_CFG2_ROWMAX_MASK	GENMASK(31, 16)
GENMASK            74 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CLKCFG_DIV_MASK(n)  GENMASK(((n)*16 + 7), (n)*16)
GENMASK            76 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CLKCFG_SEL_MASK(n)  GENMASK(((n)*17 + 8), ((n)*16 + 8))
GENMASK           187 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CBC_BRIGHT_MASK	GENMASK(10, 0)
GENMASK           191 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)
GENMASK           215 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
GENMASK           247 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_DCFG_IMODE_MASK             GENMASK(2, 0)
GENMASK           253 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
GENMASK           259 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
GENMASK           267 drivers/media/platform/atmel/atmel-isc-regs.h #define ISC_DCTRL_DVIEW_MASK            GENMASK(2, 1)
GENMASK            31 drivers/media/platform/cadence/cdns-csi2rx.c #define CSI2RX_STATIC_CFG_LANES_MASK			GENMASK(11, 8)
GENMASK            24 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DEVICE_CONFIG_STREAMS_MASK	GENMASK(6, 4)
GENMASK            26 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DEVICE_CONFIG_LANES_MASK		GENMASK(2, 0)
GENMASK            35 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_DPHY_CFG_MODE_MASK		GENMASK(9, 8)
GENMASK            59 drivers/media/platform/cadence/cdns-csi2tx.c #define CSI2TX_V2_DPHY_CFG_MODE_MASK		GENMASK(9, 8)
GENMASK            33 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_N1		GENMASK(11, 0)
GENMASK            34 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_N2		GENMASK(23, 12)
GENMASK            41 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_M1		GENMASK(11, 0)
GENMASK            42 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CLK_CNTL_M2		GENMASK(23, 12)
GENMASK            67 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_GEN_CNTL_CLK_CTRL_MASK	GENMASK(2, 1)
GENMASK            73 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_GEN_CNTL_FILTER_TICK_SEL	GENMASK(9, 8)
GENMASK            74 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_GEN_CNTL_FILTER_DEL	GENMASK(14, 12)
GENMASK            86 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_RW_ADDR			GENMASK(7, 0)
GENMASK            87 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_RW_WR_DATA			GENMASK(15, 8)
GENMASK            90 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_RW_RD_DATA			GENMASK(31, 24)
GENMASK           118 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CTRL_TYPE		GENMASK(2, 1)
GENMASK           125 drivers/media/platform/meson/ao-cec-g12a.c #define CECB_CTRL2_RISE_DEL_MAX	GENMASK(4, 0)
GENMASK            41 drivers/media/platform/meson/ao-cec.c #define CEC_GEN_CNTL_CLK_CTRL_MASK	GENMASK(2, 1)
GENMASK            54 drivers/media/platform/meson/ao-cec.c #define CEC_RW_ADDR			GENMASK(7, 0)
GENMASK            55 drivers/media/platform/meson/ao-cec.c #define CEC_RW_WR_DATA			GENMASK(15, 8)
GENMASK            58 drivers/media/platform/meson/ao-cec.c #define CEC_RW_RD_DATA			GENMASK(31, 24)
GENMASK           103 drivers/media/platform/rcar_fdp1.c #define FD1_CTL_STATUS_VINT_CNT_MASK	GENMASK(31, 16)
GENMASK           129 drivers/media/platform/rcar_fdp1.c #define FD1_RPF_SIZE_MASK		GENMASK(12, 0)
GENMASK            34 drivers/media/platform/stm32/stm32-cec.c #define OAR		GENMASK(30, 16)
GENMASK            41 drivers/media/platform/stm32/stm32-cec.c #define SFT		GENMASK(2, 0)
GENMASK            34 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_IF_DATA_WIDTH_MASK		GENMASK(10, 8)
GENMASK            41 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_IF_CFG_CSI_IF_MASK			GENMASK(4, 0)
GENMASK            48 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CAP_CH0_CAP_MASK_MASK		GENMASK(5, 2)
GENMASK            61 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_INPUT_FMT_MASK		GENMASK(23, 20)
GENMASK            63 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_OUTPUT_FMT_MASK		GENMASK(19, 16)
GENMASK            67 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_FIELD_SEL_MASK		GENMASK(11, 10)
GENMASK            71 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_CFG_INPUT_SEQ_MASK		GENMASK(9, 8)
GENMASK           113 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_HSIZE_HOR_LEN_MASK		GENMASK(28, 16)
GENMASK           115 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_HSIZE_HOR_START_MASK		GENMASK(12, 0)
GENMASK           119 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_VSIZE_VER_LEN_MASK		GENMASK(28, 16)
GENMASK           121 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_VSIZE_VER_START_MASK		GENMASK(12, 0)
GENMASK           125 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_BUF_LEN_BUF_LEN_C_MASK		GENMASK(29, 16)
GENMASK           127 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_BUF_LEN_BUF_LEN_Y_MASK		GENMASK(13, 0)
GENMASK           131 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_FLIP_SIZE_VER_LEN_MASK		GENMASK(28, 16)
GENMASK           133 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h #define CSI_CH_FLIP_SIZE_VALID_LEN_MASK		GENMASK(12, 0)
GENMASK            91 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_MINOR_MASK		GENMASK(5, 0)
GENMASK            92 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_CUSTOM_MASK		GENMASK(7, 6)
GENMASK            93 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_MAJOR_MASK		GENMASK(10, 8)
GENMASK            94 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_RTL_MASK		GENMASK(15, 11)
GENMASK            95 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_FUNC_MASK		GENMASK(27, 16)
GENMASK            96 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_REVISION_SCHEME_MASK		GENMASK(31, 30)
GENMASK           100 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_WFIFO_MASK		GENMASK(3, 0)
GENMASK           101 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_RFIFO_MASK		GENMASK(7, 4)
GENMASK           102 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_PCTX_MASK			GENMASK(12, 8)
GENMASK           103 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_WCTX_MASK			GENMASK(18, 13)
GENMASK           104 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_VFIFO_MASK		GENMASK(22, 19)
GENMASK           105 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_NCPORT_MASK		GENMASK(27, 23)
GENMASK           106 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_NPPI_CTXS0_MASK		GENMASK(29, 28)
GENMASK           107 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_HWINFO_NPPI_CTXS1_MASK		GENMASK(31, 30)
GENMASK           118 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_HL_SYSCONFIG_IDLE_MASK		GENMASK(3, 2)
GENMASK           137 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_PIX_PROC_EXTRACT_MASK		GENMASK(4, 1)
GENMASK           149 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_PIX_PROC_DPCMD_MASK			GENMASK(9, 5)
GENMASK           164 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_PIX_PROC_DPCME_MASK			GENMASK(15, 11)
GENMASK           173 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_PIX_PROC_PACK_MASK			GENMASK(18, 16)
GENMASK           180 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_PIX_PROC_CPORT_MASK			GENMASK(23, 19)
GENMASK           185 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL_TAGCNT_MASK			GENMASK(4, 1)
GENMASK           186 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL_BURSTSIZE_MASK			GENMASK(6, 5)
GENMASK           191 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL_LL_FORCE_STATE_MASK		GENMASK(12, 7)
GENMASK           192 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL_MFLAGL_MASK			GENMASK(20, 13)
GENMASK           197 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL_MFLAGH_MASK			GENMASK(31, 24)
GENMASK           199 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL1_PPI_GROUPING_MASK		GENMASK(1, 0)
GENMASK           204 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL1_INTERLEAVE01_MASK		GENMASK(3, 2)
GENMASK           209 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CTRL1_INTERLEAVE23_MASK		GENMASK(5, 4)
GENMASK           215 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_LINE_NUMBER_EVT_CPORT_MASK		GENMASK(4, 0)
GENMASK           216 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_LINE_NUMBER_EVT_MASK		GENMASK(29, 16)
GENMASK           218 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_VPORT_CTRL1_PCLK_MASK		GENMASK(16, 0)
GENMASK           219 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_VPORT_CTRL1_XBLK_MASK		GENMASK(24, 17)
GENMASK           220 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_VPORT_CTRL1_YBLK_MASK		GENMASK(30, 25)
GENMASK           225 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_VPORT_CTRL2_CPORT_MASK		GENMASK(4, 0)
GENMASK           235 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_VPORT_CTRL2_RDY_THR_MASK		GENMASK(31, 18)
GENMASK           237 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_BYS_CTRL1_PCLK_MASK			GENMASK(16, 0)
GENMASK           238 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_BYS_CTRL1_XBLK_MASK			GENMASK(24, 17)
GENMASK           239 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_BYS_CTRL1_YBLK_MASK			GENMASK(30, 25)
GENMASK           242 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_BYS_CTRL2_CPORTIN_MASK		GENMASK(4, 0)
GENMASK           243 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_BYS_CTRL2_CPORTOUT_MASK		GENMASK(9, 5)
GENMASK           257 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK		GENMASK(10, 2)
GENMASK           258 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK	GENMASK(14, 11)
GENMASK           259 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL_PCLK_MASK		GENMASK(31, 15)
GENMASK           261 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_PIX_ADDR_MASK		GENMASK(31, 3)
GENMASK           263 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_PIX_OFST_MASK		GENMASK(31, 4)
GENMASK           265 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_XSIZE_MASK			GENMASK(31, 19)
GENMASK           267 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_YSIZE_MASK			GENMASK(29, 16)
GENMASK           269 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_INIT_ADDR_MASK		GENMASK(31, 3)
GENMASK           271 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_INIT_OFST_MASK		GENMASK(31, 3)
GENMASK           273 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK		GENMASK(2, 0)
GENMASK           281 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL2_PATTERN_MASK		GENMASK(5, 4)
GENMASK           289 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK		GENMASK(29, 16)
GENMASK           291 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_CTRL_MODE_MASK		GENMASK(2, 0)
GENMASK           298 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_CTRL_PATTERN_MASK		GENMASK(4, 3)
GENMASK           304 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_CTRL_DTAG_MASK		GENMASK(8, 6)
GENMASK           313 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_CTRL_CPORT_MASK		GENMASK(13, 9)
GENMASK           315 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_CTRL_YSIZE_MASK		GENMASK(31, 18)
GENMASK           317 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_ADDR_MASK			GENMASK(31, 4)
GENMASK           319 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_OFST_MASK			GENMASK(18, 4)
GENMASK           320 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_OFST_CIRC_MODE_MASK		GENMASK(23, 22)
GENMASK           325 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK		GENMASK(31, 24)
GENMASK           327 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_XSIZE_XSKIP_MASK		GENMASK(15, 3)
GENMASK           328 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_WR_DMA_XSIZE_MASK			GENMASK(31, 19)
GENMASK           336 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK	GENMASK(2, 0)
GENMASK           346 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK	GENMASK(6, 4)
GENMASK           348 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK	GENMASK(10, 8)
GENMASK           350 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK	GENMASK(14, 12)
GENMASK           352 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK	GENMASK(18, 16)
GENMASK           355 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK		GENMASK(26, 25)
GENMASK           359 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK		GENMASK(28, 27)
GENMASK           370 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_SHORT_PACKET_MASK	GENMASK(23, 0)
GENMASK           403 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK	GENMASK(12, 0)
GENMASK           433 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_CTX_DT_MASK		GENMASK(5, 0)
GENMASK           434 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_CTX_VC_MASK		GENMASK(7, 6)
GENMASK           435 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_CTX_CPORT_MASK		GENMASK(12, 8)
GENMASK           442 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_CTX_LINES_MASK		GENMASK(29, 16)
GENMASK           444 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_STATUS_FRAME_MASK	GENMASK(15, 0)
GENMASK           446 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK	GENMASK(7, 0)
GENMASK           447 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG0_THS_TERM_MASK		GENMASK(15, 8)
GENMASK           452 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK			GENMASK(7, 0)
GENMASK           453 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK		GENMASK(9, 8)
GENMASK           454 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK		GENMASK(17, 10)
GENMASK           455 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK			GENMASK(24, 18)
GENMASK           459 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK		GENMASK(29, 28)
GENMASK           461 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK		GENMASK(23, 0)
GENMASK           462 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK		GENMASK(25, 24)
GENMASK           463 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK		GENMASK(27, 26)
GENMASK           464 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK		GENMASK(29, 28)
GENMASK           465 drivers/media/platform/ti-vpe/cal_regs.h #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK		GENMASK(31, 30)
GENMASK           468 drivers/media/platform/ti-vpe/cal_regs.h #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK			GENMASK(2, 1)
GENMASK           469 drivers/media/platform/ti-vpe/cal_regs.h #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK			GENMASK(4, 3)
GENMASK           472 drivers/media/platform/ti-vpe/cal_regs.h #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK			GENMASK(12, 11)
GENMASK           473 drivers/media/platform/ti-vpe/cal_regs.h #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK			GENMASK(16, 13)
GENMASK            82 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_COMPONENTS_NUM_MSK	GENMASK(18, 16)
GENMASK            85 drivers/media/platform/vicodec/codec-fwht.h #define FWHT_FL_PIXENC_MSK	GENMASK(20, 19)
GENMASK          1616 drivers/media/platform/vivid/vivid-ctrls.c 		s64 hdmi_input_mask = GENMASK(dev->num_hdmi_inputs - 1, 0);
GENMASK          1643 drivers/media/platform/vivid/vivid-ctrls.c 		s64 hdmi_output_mask = GENMASK(dev->num_hdmi_outputs - 1, 0);
GENMASK           100 drivers/media/rc/ir-spi.c 	idata->pulse = GENMASK(bits, 0);
GENMASK            34 drivers/media/rc/meson-ir.c #define REG0_RATE_MASK		GENMASK(11, 0)
GENMASK            40 drivers/media/rc/meson-ir.c #define REG1_MODE_MASK		GENMASK(8, 7)
GENMASK            44 drivers/media/rc/meson-ir.c #define REG2_MODE_MASK		GENMASK(3, 0)
GENMASK            47 drivers/media/rc/meson-ir.c #define REG1_TIME_IV_MASK	GENMASK(28, 16)
GENMASK            49 drivers/media/rc/meson-ir.c #define REG1_IRQSEL_MASK	GENMASK(3, 2)
GENMASK            27 drivers/media/rc/mtk-cir.c #define MTK_OK_COUNT(x)		  (((x) & GENMASK(23, 16)) << 16)
GENMASK            36 drivers/media/rc/mtk-cir.c #define MTK_WIDTH_MASK		  (GENMASK(7, 0))
GENMASK            40 drivers/media/rc/mtk-cir.c #define MTK_DG_CNT_MASK		 (GENMASK(12, 8))
GENMASK           115 drivers/media/rc/mtk-cir.c 	[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
GENMASK           116 drivers/media/rc/mtk-cir.c 	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
GENMASK           120 drivers/media/rc/mtk-cir.c 	[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
GENMASK           121 drivers/media/rc/mtk-cir.c 	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
GENMASK            68 drivers/media/rc/sunxi-cir.c #define REG_CIR_NTHR(val)    (((val) << 2) & (GENMASK(7, 2)))
GENMASK            70 drivers/media/rc/sunxi-cir.c #define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))
GENMASK            22 drivers/media/rc/zx-irdec.c #define ZX_DEGL_MASK		GENMASK(21, 20)
GENMASK            24 drivers/media/rc/zx-irdec.c #define ZX_WDBEGIN_MASK		GENMASK(18, 8)
GENMASK            49 drivers/mfd/atmel-smc.c 	unsigned int lsbmask = GENMASK(msbpos - 1, 0);
GENMASK            50 drivers/mfd/atmel-smc.c 	unsigned int msbmask = GENMASK(msbwidth - 1, 0);
GENMASK           113 drivers/mfd/atmel-smc.c 	conf->timings &= ~GENMASK(shift + 3, shift);
GENMASK           152 drivers/mfd/atmel-smc.c 	conf->setup &= ~GENMASK(shift + 7, shift);
GENMASK           191 drivers/mfd/atmel-smc.c 	conf->pulse &= ~GENMASK(shift + 7, shift);
GENMASK           229 drivers/mfd/atmel-smc.c 	conf->cycle &= ~GENMASK(shift + 15, shift);
GENMASK            50 drivers/mfd/intel-lpss.c #define LPSS_PRIV_LTR_SCALE_MASK	GENMASK(11, 10)
GENMASK            53 drivers/mfd/intel-lpss.c #define LPSS_PRIV_LTR_VALUE_MASK	GENMASK(9, 0)
GENMASK            62 drivers/mfd/intel-lpss.c #define LPSS_PRIV_CAPS_TYPE_MASK	GENMASK(7, 4)
GENMASK            22 drivers/mfd/intel_soc_pmic_chtwc.c #define REG_OFFSET_MASK		GENMASK(7, 0)
GENMASK            23 drivers/mfd/intel_soc_pmic_chtwc.c #define REG_ADDR_MASK		GENMASK(15, 8)
GENMASK           251 drivers/mfd/qcom-pm8xxx.c 	if (master & GENMASK(7, 1))
GENMASK             9 drivers/misc/ocxl/config.c #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
GENMASK            11 drivers/misc/ocxl/config.c #define OCXL_DVSEC_AFU_IDX_MASK              GENMASK(5, 0)
GENMASK            12 drivers/misc/ocxl/config.c #define OCXL_DVSEC_ACTAG_MASK                GENMASK(11, 0)
GENMASK            13 drivers/misc/ocxl/config.c #define OCXL_DVSEC_PASID_MASK                GENMASK(19, 0)
GENMASK            14 drivers/misc/ocxl/config.c #define OCXL_DVSEC_PASID_LOG_MASK            GENMASK(4, 0)
GENMASK           759 drivers/misc/ocxl/config.c 	val = recv_cap & GENMASK(31, 0);
GENMASK           188 drivers/mmc/host/cavium.c 	*reg |= FIELD_PREP(GENMASK(61, 60), bus_id);
GENMASK            19 drivers/mmc/host/cqhci.h #define CQHCI_VER_MAJOR(x)		(((x) & GENMASK(11, 8)) >> 8)
GENMASK            20 drivers/mmc/host/cqhci.h #define CQHCI_VER_MINOR1(x)		(((x) & GENMASK(7, 4)) >> 4)
GENMASK            21 drivers/mmc/host/cqhci.h #define CQHCI_VER_MINOR2(x)		((x) & GENMASK(3, 0))
GENMASK            83 drivers/mmc/host/cqhci.h #define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
GENMASK            97 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_C_INDEX(x)		((x) & GENMASK(5, 0))
GENMASK            98 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_C_TASK(x)		(((x) & GENMASK(12, 8)) >> 8)
GENMASK           100 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_D_INDEX(x)		(((x) & GENMASK(21, 16)) >> 16)
GENMASK           101 drivers/mmc/host/cqhci.h #define CQHCI_TERRI_D_TASK(x)		(((x) & GENMASK(28, 24)) >> 24)
GENMASK            18 drivers/mmc/host/dw_mmc-bluefield.c #define UHS_REG_EXT_SAMPLE_MASK		GENMASK(22, 16)
GENMASK            19 drivers/mmc/host/dw_mmc-bluefield.c #define UHS_REG_EXT_DRIVE_MASK		GENMASK(29, 23)
GENMASK            39 drivers/mmc/host/dw_mmc-k3.c #define GPIO_CLK_DIV_MASK                 GENMASK(11, 8)
GENMASK            40 drivers/mmc/host/dw_mmc-k3.c #define GPIO_USE_SAMPLE_DLY_MASK          GENMASK(13, 13)
GENMASK            41 drivers/mmc/host/dw_mmc-k3.c #define UHS_REG_EXT_SAMPLE_PHASE_MASK     GENMASK(20, 16)
GENMASK            42 drivers/mmc/host/dw_mmc-k3.c #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
GENMASK            43 drivers/mmc/host/dw_mmc-k3.c #define UHS_REG_EXT_SAMPLE_DLY_MASK       GENMASK(30, 26)
GENMASK            34 drivers/mmc/host/meson-gx-mmc.c #define   CLK_DIV_MASK GENMASK(5, 0)
GENMASK            35 drivers/mmc/host/meson-gx-mmc.c #define   CLK_SRC_MASK GENMASK(7, 6)
GENMASK            36 drivers/mmc/host/meson-gx-mmc.c #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
GENMASK            37 drivers/mmc/host/meson-gx-mmc.c #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
GENMASK            38 drivers/mmc/host/meson-gx-mmc.c #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
GENMASK            41 drivers/mmc/host/meson-gx-mmc.c #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
GENMASK            42 drivers/mmc/host/meson-gx-mmc.c #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
GENMASK            45 drivers/mmc/host/meson-gx-mmc.c #define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
GENMASK            46 drivers/mmc/host/meson-gx-mmc.c #define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
GENMASK            55 drivers/mmc/host/meson-gx-mmc.c #define   ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
GENMASK            67 drivers/mmc/host/meson-gx-mmc.c #define   START_DESC_ADDR_MASK GENMASK(31, 2)
GENMASK            70 drivers/mmc/host/meson-gx-mmc.c #define   CFG_BUS_WIDTH_MASK GENMASK(1, 0)
GENMASK            75 drivers/mmc/host/meson-gx-mmc.c #define   CFG_BLK_LEN_MASK GENMASK(7, 4)
GENMASK            76 drivers/mmc/host/meson-gx-mmc.c #define   CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
GENMASK            77 drivers/mmc/host/meson-gx-mmc.c #define   CFG_RC_CC_MASK GENMASK(15, 12)
GENMASK            87 drivers/mmc/host/meson-gx-mmc.c #define   STATUS_DATI GENMASK(23, 16)
GENMASK            90 drivers/mmc/host/meson-gx-mmc.c #define   IRQ_RXD_ERR_MASK GENMASK(7, 0)
GENMASK           178 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
GENMASK           182 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
GENMASK           191 drivers/mmc/host/meson-gx-mmc.c #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
GENMASK           195 drivers/mmc/host/meson-gx-mmc.c #define CMD_DATA_MASK GENMASK(31, 2)
GENMASK           198 drivers/mmc/host/meson-gx-mmc.c #define CMD_RESP_MASK GENMASK(31, 1)
GENMASK            33 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK		GENMASK(7, 0)
GENMASK            34 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK		GENMASK(15, 8)
GENMASK            41 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK	GENMASK(31, 24)
GENMASK            48 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK	GENMASK(17, 12)
GENMASK            52 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_CONF_M_ENDIAN_MASK		GENMASK(22, 21)
GENMASK            53 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_CONF_WRITE_NWR_MASK		GENMASK(28, 23)
GENMASK            54 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK	GENMASK(31, 29)
GENMASK            57 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK	GENMASK(3, 0)
GENMASK            64 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK		GENMASK(15, 12)
GENMASK            68 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK	GENMASK(31, 19)
GENMASK            73 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK		GENMASK(7, 6)
GENMASK            76 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK		GENMASK(13, 10)
GENMASK            82 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_MULT_PORT_SEL_MASK		GENMASK(1, 0)
GENMASK            90 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK		GENMASK(15, 12)
GENMASK            95 drivers/mmc/host/meson-mx-sdio.c 	#define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK		GENMASK(29, 16)
GENMASK           263 drivers/mmc/host/mmci.c 	.stm32_idmabsize_mask	= GENMASK(12, 5),
GENMASK            59 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_CLKDIV_MSK	GENMASK(9, 0)
GENMASK            66 drivers/mmc/host/mmci.h #define MCI_STM32_CLK_SEL_MSK		GENMASK(21, 20)
GENMASK            96 drivers/mmc/host/mmci.h #define MCI_CPSM_STM32_WAITRESP_MASK	GENMASK(9, 8)
GENMASK           226 drivers/mmc/host/mmci.h #define MMCI_STM32_IDMABNDT_MASK	GENMASK(12, 5)
GENMASK           231 drivers/mmc/host/mmci.h #define MMCI_STM32_IDMALA_MASK	GENMASK(13, 0)
GENMASK            15 drivers/mmc/host/mmci_qcom_dml.c #define PRODUCER_CRCI_MSK		GENMASK(1, 0)
GENMASK            19 drivers/mmc/host/mmci_qcom_dml.c #define CONSUMER_CRCI_MSK		GENMASK(3, 2)
GENMASK            35 drivers/mmc/host/mmci_qcom_dml.c #define PRODUCER_PIPE_ID_MSK		GENMASK(4, 0)
GENMASK            37 drivers/mmc/host/mmci_qcom_dml.c #define CONSUMER_PIPE_ID_MSK		GENMASK(20, 16)
GENMASK           256 drivers/mmc/host/sdhci-acpi.c #define BYT_IOSF_OCP_TIMEOUT_BASE	GENMASK(10, 8)
GENMASK            23 drivers/mmc/host/sdhci-cadence.c #define   SDHCI_CDNS_HRS04_RDATA		GENMASK(23, 16)
GENMASK            24 drivers/mmc/host/sdhci-cadence.c #define   SDHCI_CDNS_HRS04_WDATA		GENMASK(15, 8)
GENMASK            25 drivers/mmc/host/sdhci-cadence.c #define   SDHCI_CDNS_HRS04_ADDR			GENMASK(5, 0)
GENMASK            29 drivers/mmc/host/sdhci-cadence.c #define   SDHCI_CDNS_HRS06_TUNE			GENMASK(13, 8)
GENMASK            30 drivers/mmc/host/sdhci-cadence.c #define   SDHCI_CDNS_HRS06_MODE			GENMASK(2, 0)
GENMASK           158 drivers/mmc/host/sdhci-of-arasan.c 				   HIWORD_UPDATE(val, GENMASK(width, 0),
GENMASK           162 drivers/mmc/host/sdhci-of-arasan.c 					 GENMASK(shift + width, shift),
GENMASK           460 drivers/mmc/host/sdhci-pci-core.c #define BYT_IOSF_OCP_TIMEOUT_BASE	GENMASK(10, 8)
GENMASK           863 drivers/mmc/host/sdhci-pci-core.c #define GLK_PATH_PLL	GENMASK(13, 8)
GENMASK           864 drivers/mmc/host/sdhci-pci-core.c #define GLK_DLY		GENMASK(6, 0)
GENMASK            25 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
GENMASK            26 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
GENMASK            35 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
GENMASK            40 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
GENMASK            46 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
GENMASK            58 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
GENMASK            63 drivers/mmc/host/sdhci-pci-gli.c #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
GENMASK            24 drivers/mmc/host/sdhci-sprd.c #define SDHCI_SPRD_ARG2_STUFF		GENMASK(31, 16)
GENMASK            20 drivers/mmc/host/sdhci_am654.c #define SLOTTYPE_MASK		GENMASK(31, 30)
GENMASK            38 drivers/mmc/host/sdhci_am654.c #define OTAPDLYSEL_MASK		GENMASK(15, 12)
GENMASK            40 drivers/mmc/host/sdhci_am654.c #define STRBSEL_4BIT_MASK	GENMASK(27, 24)
GENMASK            41 drivers/mmc/host/sdhci_am654.c #define STRBSEL_8BIT_MASK	GENMASK(31, 24)
GENMASK            47 drivers/mmc/host/sdhci_am654.c #define FREQSEL_MASK		GENMASK(10, 8)
GENMASK            49 drivers/mmc/host/sdhci_am654.c #define DLL_TRIM_ICP_MASK	GENMASK(7, 4)
GENMASK            51 drivers/mmc/host/sdhci_am654.c #define DR_TY_MASK		GENMASK(22, 20)
GENMASK            29 drivers/mmc/host/uniphier-sd.c #define   UNIPHIER_SD_VOLT_MASK			GENMASK(1, 0)
GENMASK            34 drivers/mmc/host/uniphier-sd.c #define   UNIPHIER_SD_DMA_MODE_DIR_MASK		GENMASK(17, 16)
GENMASK            37 drivers/mmc/host/uniphier-sd.c #define   UNIPHIER_SD_DMA_MODE_WIDTH_MASK	GENMASK(5, 4)
GENMASK            90 drivers/mtd/nand/bbt.c 	return status & GENMASK(bits_per_block - 1, 0);
GENMASK           114 drivers/mtd/nand/bbt.c 	unsigned long val = status & GENMASK(bits_per_block - 1, 0);
GENMASK           119 drivers/mtd/nand/bbt.c 	pos[0] &= ~GENMASK(offs + bits_per_block - 1, offs);
GENMASK           125 drivers/mtd/nand/bbt.c 		pos[1] &= ~GENMASK(rbits - 1, 0);
GENMASK            71 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK	GENMASK(30, 24)
GENMASK            73 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_DTO_MAX		GENMASK(22, 16)
GENMASK            78 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK	GENMASK(2, 0)
GENMASK            94 drivers/mtd/nand/raw/atmel/nand-controller.c #define ATMEL_HSMC_NFC_SR_CSID			GENMASK(14, 12)
GENMASK            72 drivers/mtd/nand/raw/atmel/pmecc.c #define PMECC_CFG_BCH_STRENGTH_MASK		GENMASK(2, 0)
GENMASK           129 drivers/mtd/nand/raw/atmel/pmecc.c #define PMERRLOC_ERR_NUM_MASK			GENMASK(12, 8)
GENMASK           481 drivers/mtd/nand/raw/brcmnand/brcmnand.c 	INTFC_FLASH_STATUS		= GENMASK(7, 0),
GENMASK           781 drivers/mtd/nand/raw/brcmnand/brcmnand.c 		return GENMASK(7, 0);
GENMASK           783 drivers/mtd/nand/raw/brcmnand/brcmnand.c 		return GENMASK(6, 0);
GENMASK           785 drivers/mtd/nand/raw/brcmnand/brcmnand.c 		return GENMASK(5, 0);
GENMASK          1407 drivers/mtd/nand/raw/brcmnand/brcmnand.c 	LLOP_DATA_MASK			= GENMASK(15, 0),
GENMASK           457 drivers/mtd/nand/raw/denali.c 		*uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
GENMASK          1316 drivers/mtd/nand/raw/denali.c 	iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED);
GENMASK            24 drivers/mtd/nand/raw/denali.h #define     LOAD_WAIT_CNT__VALUE			GENMASK(15, 0)
GENMASK            27 drivers/mtd/nand/raw/denali.h #define     PROGRAM_WAIT_CNT__VALUE			GENMASK(15, 0)
GENMASK            30 drivers/mtd/nand/raw/denali.h #define     ERASE_WAIT_CNT__VALUE			GENMASK(15, 0)
GENMASK            33 drivers/mtd/nand/raw/denali.h #define     INT_MON_CYCCNT__VALUE			GENMASK(15, 0)
GENMASK            55 drivers/mtd/nand/raw/denali.h #define     PREFETCH_MODE__PREFETCH_BURST_LENGTH	GENMASK(15, 4)
GENMASK            67 drivers/mtd/nand/raw/denali.h #define     TWHR2_AND_WE_2_RE__WE_2_RE			GENMASK(5, 0)
GENMASK            68 drivers/mtd/nand/raw/denali.h #define     TWHR2_AND_WE_2_RE__TWHR2			GENMASK(13, 8)
GENMASK            72 drivers/mtd/nand/raw/denali.h #define     TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA		GENMASK(6, 0)
GENMASK            73 drivers/mtd/nand/raw/denali.h #define     TCWAW_AND_ADDR_2_DATA__TCWAW		GENMASK(13, 8)
GENMASK            76 drivers/mtd/nand/raw/denali.h #define     RE_2_WE__VALUE				GENMASK(5, 0)
GENMASK            79 drivers/mtd/nand/raw/denali.h #define     ACC_CLKS__VALUE				GENMASK(3, 0)
GENMASK            82 drivers/mtd/nand/raw/denali.h #define     NUMBER_OF_PLANES__VALUE			GENMASK(2, 0)
GENMASK            85 drivers/mtd/nand/raw/denali.h #define     PAGES_PER_BLOCK__VALUE			GENMASK(15, 0)
GENMASK            88 drivers/mtd/nand/raw/denali.h #define     DEVICE_WIDTH__VALUE				GENMASK(1, 0)
GENMASK            91 drivers/mtd/nand/raw/denali.h #define     DEVICE_MAIN_AREA_SIZE__VALUE		GENMASK(15, 0)
GENMASK            94 drivers/mtd/nand/raw/denali.h #define     DEVICE_SPARE_AREA_SIZE__VALUE		GENMASK(15, 0)
GENMASK           103 drivers/mtd/nand/raw/denali.h #define     ECC_CORRECTION__VALUE			GENMASK(4, 0)
GENMASK           104 drivers/mtd/nand/raw/denali.h #define     ECC_CORRECTION__ERASE_THRESHOLD		GENMASK(31, 16)
GENMASK           107 drivers/mtd/nand/raw/denali.h #define     READ_MODE__VALUE				GENMASK(3, 0)
GENMASK           110 drivers/mtd/nand/raw/denali.h #define     WRITE_MODE__VALUE				GENMASK(3, 0)
GENMASK           113 drivers/mtd/nand/raw/denali.h #define     COPYBACK_MODE__VALUE			GENMASK(3, 0)
GENMASK           116 drivers/mtd/nand/raw/denali.h #define     RDWR_EN_LO_CNT__VALUE			GENMASK(4, 0)
GENMASK           119 drivers/mtd/nand/raw/denali.h #define     RDWR_EN_HI_CNT__VALUE			GENMASK(4, 0)
GENMASK           122 drivers/mtd/nand/raw/denali.h #define     MAX_RD_DELAY__VALUE				GENMASK(3, 0)
GENMASK           125 drivers/mtd/nand/raw/denali.h #define     CS_SETUP_CNT__VALUE				GENMASK(4, 0)
GENMASK           126 drivers/mtd/nand/raw/denali.h #define     CS_SETUP_CNT__TWB				GENMASK(17, 12)
GENMASK           129 drivers/mtd/nand/raw/denali.h #define     SPARE_AREA_SKIP_BYTES__VALUE		GENMASK(5, 0)
GENMASK           132 drivers/mtd/nand/raw/denali.h #define     SPARE_AREA_MARKER__VALUE			GENMASK(15, 0)
GENMASK           135 drivers/mtd/nand/raw/denali.h #define     DEVICES_CONNECTED__VALUE			GENMASK(2, 0)
GENMASK           138 drivers/mtd/nand/raw/denali.h #define     DIE_MASK__VALUE				GENMASK(7, 0)
GENMASK           141 drivers/mtd/nand/raw/denali.h #define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE		GENMASK(15, 0)
GENMASK           147 drivers/mtd/nand/raw/denali.h #define     RE_2_RE__VALUE				GENMASK(5, 0)
GENMASK           150 drivers/mtd/nand/raw/denali.h #define     MANUFACTURER_ID__VALUE			GENMASK(7, 0)
GENMASK           153 drivers/mtd/nand/raw/denali.h #define     DEVICE_ID__VALUE				GENMASK(7, 0)
GENMASK           156 drivers/mtd/nand/raw/denali.h #define     DEVICE_PARAM_0__VALUE			GENMASK(7, 0)
GENMASK           159 drivers/mtd/nand/raw/denali.h #define     DEVICE_PARAM_1__VALUE			GENMASK(7, 0)
GENMASK           162 drivers/mtd/nand/raw/denali.h #define     DEVICE_PARAM_2__VALUE			GENMASK(7, 0)
GENMASK           165 drivers/mtd/nand/raw/denali.h #define     LOGICAL_PAGE_DATA_SIZE__VALUE		GENMASK(15, 0)
GENMASK           168 drivers/mtd/nand/raw/denali.h #define     LOGICAL_PAGE_SPARE_SIZE__VALUE		GENMASK(15, 0)
GENMASK           171 drivers/mtd/nand/raw/denali.h #define     REVISION__VALUE				GENMASK(15, 0)
GENMASK           174 drivers/mtd/nand/raw/denali.h #define     ONFI_DEVICE_FEATURES__VALUE			GENMASK(5, 0)
GENMASK           177 drivers/mtd/nand/raw/denali.h #define     ONFI_OPTIONAL_COMMANDS__VALUE		GENMASK(5, 0)
GENMASK           180 drivers/mtd/nand/raw/denali.h #define     ONFI_TIMING_MODE__VALUE			GENMASK(5, 0)
GENMASK           183 drivers/mtd/nand/raw/denali.h #define     ONFI_PGM_CACHE_TIMING_MODE__VALUE		GENMASK(5, 0)
GENMASK           186 drivers/mtd/nand/raw/denali.h #define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS		GENMASK(7, 0)
GENMASK           190 drivers/mtd/nand/raw/denali.h #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE	GENMASK(15, 0)
GENMASK           193 drivers/mtd/nand/raw/denali.h #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE	GENMASK(15, 0)
GENMASK           196 drivers/mtd/nand/raw/denali.h #define     FEATURES__N_BANKS				GENMASK(1, 0)
GENMASK           197 drivers/mtd/nand/raw/denali.h #define     FEATURES__ECC_MAX_ERR			GENMASK(5, 2)
GENMASK           206 drivers/mtd/nand/raw/denali.h #define     TRANSFER_MODE__VALUE			GENMASK(1, 0)
GENMASK           235 drivers/mtd/nand/raw/denali.h #define     ECC_THRESHOLD__VALUE			GENMASK(9, 0)
GENMASK           238 drivers/mtd/nand/raw/denali.h #define     ECC_ERROR_BLOCK_ADDRESS__VALUE		GENMASK(15, 0)
GENMASK           241 drivers/mtd/nand/raw/denali.h #define     ECC_ERROR_PAGE_ADDRESS__VALUE		GENMASK(11, 0)
GENMASK           242 drivers/mtd/nand/raw/denali.h #define     ECC_ERROR_PAGE_ADDRESS__BANK		GENMASK(15, 12)
GENMASK           245 drivers/mtd/nand/raw/denali.h #define     ECC_ERROR_ADDRESS__OFFSET			GENMASK(11, 0)
GENMASK           246 drivers/mtd/nand/raw/denali.h #define     ECC_ERROR_ADDRESS__SECTOR			GENMASK(15, 12)
GENMASK           249 drivers/mtd/nand/raw/denali.h #define     ERR_CORRECTION_INFO__BYTE			GENMASK(7, 0)
GENMASK           250 drivers/mtd/nand/raw/denali.h #define     ERR_CORRECTION_INFO__DEVICE			GENMASK(11, 8)
GENMASK           256 drivers/mtd/nand/raw/denali.h #define     ECC_COR_INFO__MAX_ERRORS			GENMASK(6, 0)
GENMASK           283 drivers/mtd/nand/raw/denali.h #define     TARGET_ERR_ADDR_LO__VALUE			GENMASK(15, 0)
GENMASK           286 drivers/mtd/nand/raw/denali.h #define     TARGET_ERR_ADDR_HI__VALUE			GENMASK(15, 0)
GENMASK           882 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 			src_buffer &= GENMASK(nbits - 1, 0);
GENMASK           902 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 			dst[0] &= GENMASK(dst_bit_off - 1, 0);
GENMASK           955 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 		src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
GENMASK           967 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 			     (*dst & GENMASK(dst_bit_off - 1, 0));
GENMASK           977 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 			       GENMASK(7, bits_in_src_buffer % 8)) <<
GENMASK          1378 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 				eccbuf[0] |= GENMASK(bitoffset - 1, 0);
GENMASK          1382 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c 				eccbuf[eccbytes - 1] |= GENMASK(7, bitoffset);
GENMASK           124 drivers/mtd/nand/raw/marvell_nand.c #define NDCR_ALL_INT		GENMASK(11, 0)
GENMASK            41 drivers/mtd/nand/raw/meson_nand.c #define NFC_CMD_GET_SIZE(x)	(((x) >> 22) & GENMASK(4, 0))
GENMASK           101 drivers/mtd/nand/raw/meson_nand.c #define ECC_ERR_CNT(x)		(((x) >> 24) & GENMASK(5, 0))
GENMASK           102 drivers/mtd/nand/raw/meson_nand.c #define ECC_ZERO_CNT(x)		(((x) >> 16) & GENMASK(5, 0))
GENMASK           278 drivers/mtd/nand/raw/meson_nand.c 		cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir);
GENMASK           539 drivers/mtd/nand/raw/meson_nand.c 	cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
GENMASK           563 drivers/mtd/nand/raw/meson_nand.c 	cmd = NFC_CMD_M2N | (len & GENMASK(5, 0));
GENMASK            71 drivers/mtd/nand/raw/mtk_nand.c #define		CNTR_MASK		GENMASK(16, 12)
GENMASK            83 drivers/mtd/nand/raw/mtk_nand.c #define		STROBE_MASK		GENMASK(4, 3)
GENMASK            45 drivers/mtd/nand/raw/mxic_nand.c #define INT_STS_ALL		GENMASK(31, 0)
GENMASK           934 drivers/mtd/nand/raw/nand_base.c 		modes = GENMASK(chip->onfi_timing_mode_default, 0);
GENMASK           358 drivers/mtd/nand/raw/nand_micron.c #define MICRON_ID_INTERNAL_ECC_MASK	GENMASK(1, 0)
GENMASK           107 drivers/mtd/nand/raw/nand_samsung.c 				    (chip->id.data[4] & GENMASK(1, 0)) == 0x1)
GENMASK            88 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_PWID_MASK		GENMASK(5, 4)
GENMASK            94 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_TCLR_MASK		GENMASK(12, 9)
GENMASK            97 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_TAR_MASK		GENMASK(16, 13)
GENMASK           100 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_PCR_ECCSS_MASK		GENMASK(19, 17)
GENMASK           177 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQICR_CLEAR_IRQ		GENMASK(4, 0)
GENMASK           180 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_CSQEMSR_SEM		GENMASK(15, 0)
GENMASK           187 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHICR_CLEAR_IRQ		GENMASK(4, 0)
GENMASK           192 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR0_DEN_MASK		GENMASK(7, 4)
GENMASK           196 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR1_EBP1_MASK		GENMASK(12, 0)
GENMASK           197 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR1_EBP2_MASK		GENMASK(28, 16)
GENMASK           201 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR2_EBP3_MASK		GENMASK(12, 0)
GENMASK           202 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR2_EBP4_MASK		GENMASK(28, 16)
GENMASK           206 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR3_EBP5_MASK		GENMASK(12, 0)
GENMASK           207 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR3_EBP6_MASK		GENMASK(28, 16)
GENMASK           211 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR4_EBP7_MASK		GENMASK(12, 0)
GENMASK           212 drivers/mtd/nand/raw/stm32_fmc2_nand.c #define FMC2_BCHDSR4_EBP8_MASK		GENMASK(28, 16)
GENMASK            66 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CE_SEL_MSK		GENMASK(26, 24)
GENMASK            69 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_PAGE_SHIFT_MSK	GENMASK(11, 8)
GENMASK           103 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_LOW_BYTE_MSK	GENMASK(7, 0)
GENMASK           104 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_HIGH_BYTE_MSK	GENMASK(15, 8)
GENMASK           106 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ADR_NUM_MSK		GENMASK(18, 16)
GENMASK           119 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_CMD_TYPE_MSK	GENMASK(31, 30)
GENMASK           125 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_READ_CMD_MSK	GENMASK(7, 0)
GENMASK           126 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RND_READ_CMD0_MSK	GENMASK(15, 8)
GENMASK           127 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RND_READ_CMD1_MSK	GENMASK(23, 16)
GENMASK           130 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_PROGRAM_CMD_MSK	GENMASK(7, 0)
GENMASK           131 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RND_WRITE_CMD_MSK	GENMASK(15, 8)
GENMASK           132 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_READ_CMD0_MSK	GENMASK(23, 16)
GENMASK           133 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_READ_CMD1_MSK	GENMASK(31, 24)
GENMASK           143 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_MODE_MSK	GENMASK(15, 12)
GENMASK           145 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_RANDOM_SEED_MSK	GENMASK(30, 16)
GENMASK           150 drivers/mtd/nand/raw/sunxi_nand.c #define NFC_ECC_ERR_MSK		GENMASK(15, 0)
GENMASK           705 drivers/mtd/nand/raw/tegra_nand.c 		if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {
GENMASK            66 drivers/mtd/nand/raw/vf610_nfc.c #define COMMAND_NADDR_BYTES(x)		GENMASK(13, 13 - (x) + 1)
GENMASK            15 drivers/mtd/nand/spi/micron.c #define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
GENMASK           163 drivers/mtd/parsers/sharpslpart.c 	return (us >> 1) & GENMASK(9, 0);
GENMASK           142 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_MODE_MASK		GENMASK(30, 28)
GENMASK           148 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_CE_INACTIVE_MASK	GENMASK(27, \
GENMASK           159 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_IO_DUMMY_LO		GENMASK(7, \
GENMASK           168 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_CLOCK_FREQ_SEL_MASK	GENMASK(11, \
GENMASK           174 drivers/mtd/spi-nor/aspeed-smc.c #define CONTROL_COMMAND_MODE_MASK	GENMASK(1, 0)
GENMASK            26 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_ECC_TYPE_MASK		GENMASK(7, 5)
GENMASK            51 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_DATA_NUM_CNT(cnt)		((cnt) & GENMASK(13, 0))
GENMASK            61 drivers/mtd/spi-nor/hisi-sfc.c #define FMC_DMA_LEN_SET(len)		((len) & GENMASK(27, 0))
GENMASK            93 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD1_ADDRESS_BYTES_MASK		GENMASK(18, 17)
GENMASK           108 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD11_PAGE_SIZE_MASK		GENMASK(7, 4)
GENMASK           143 drivers/mtd/spi-nor/spi-nor.c #define BFPT_DWORD15_QER_MASK			GENMASK(22, 20)
GENMASK          3516 drivers/mtd/spi-nor/spi-nor.c #define SMPT_CMD_ADDRESS_LEN_MASK		GENMASK(23, 22)
GENMASK          3522 drivers/mtd/spi-nor/spi-nor.c #define SMPT_CMD_READ_DUMMY_MASK		GENMASK(19, 16)
GENMASK          3528 drivers/mtd/spi-nor/spi-nor.c #define SMPT_CMD_READ_DATA_MASK			GENMASK(31, 24)
GENMASK          3533 drivers/mtd/spi-nor/spi-nor.c #define SMPT_CMD_OPCODE_MASK			GENMASK(15, 8)
GENMASK          3538 drivers/mtd/spi-nor/spi-nor.c #define SMPT_MAP_REGION_COUNT_MASK		GENMASK(23, 16)
GENMASK          3544 drivers/mtd/spi-nor/spi-nor.c #define SMPT_MAP_ID_MASK			GENMASK(15, 8)
GENMASK          3549 drivers/mtd/spi-nor/spi-nor.c #define SMPT_MAP_REGION_SIZE_MASK		GENMASK(31, 8)
GENMASK          3555 drivers/mtd/spi-nor/spi-nor.c #define SMPT_MAP_REGION_ERASE_TYPE_MASK		GENMASK(3, 0)
GENMASK            96 drivers/mux/mmio.c 		if (mask != GENMASK(field.msb, field.lsb)) {
GENMASK           307 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c 				GENMASK(KVASER_USB_KCAN_DATA_DLC_BITS - 1 + \
GENMASK           388 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c 				GENMASK(KVASER_USB_HYDRA_TRANSID_BITS - 1, 0)
GENMASK           389 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_HE_ADDR_SRC_MASK	GENMASK(7, 6)
GENMASK           390 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c #define KVASER_USB_HYDRA_HE_ADDR_DEST_MASK	GENMASK(5, 0)
GENMASK           340 drivers/net/dsa/b53/b53_regs.h #define  ARL_ADDR_MASK			GENMASK(14, 0)
GENMASK           131 drivers/net/dsa/bcm_sf2_cfp.c 	return GENMASK(num_udf - 1, 0) >> (UDFS_PER_SLICE - 1);
GENMASK           136 drivers/net/dsa/bcm_sf2_cfp.c 	return (u8)GENMASK(num_udf - 1, 0);
GENMASK          1293 drivers/net/dsa/lan9303-core.c 	chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
GENMASK           114 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_MII_PCDU_TXDLY_MASK	GENMASK(2, 0)
GENMASK           115 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_MII_PCDU_RXDLY_MASK	GENMASK(9, 7)
GENMASK           123 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_VERSION_REV_MASK		GENMASK(7, 0)
GENMASK           125 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_VERSION_MOD_MASK		GENMASK(15, 8)
GENMASK           136 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_BM_RAM_CTRL_ADDR_MASK	GENMASK(4, 0)
GENMASK           158 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_PCE_TBL_CTRL_GMAP_MASK	GENMASK(10, 7)
GENMASK           159 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_PCE_TBL_CTRL_OPMOD_MASK	GENMASK(6, 5)
GENMASK           164 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_PCE_TBL_CTRL_ADDR_MASK	GENMASK(4, 0)
GENMASK           184 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_PCE_PCTRL_0_PSTATE_MASK	GENMASK(2, 0)
GENMASK           201 drivers/net/dsa/lantiq_gswip.c #define  GSWIP_FDMA_PCTRL_VLANMOD_MASK	GENMASK(4, 3)	/* VLAN Modification Control */
GENMASK          1255 drivers/net/dsa/lantiq_gswip.c 		if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
GENMASK          1387 drivers/net/dsa/lantiq_gswip.c 			if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port)
GENMASK           177 drivers/net/dsa/mv88e6xxx/chip.c 		ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
GENMASK           201 drivers/net/dsa/mv88e6xxx/chip.c 	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
GENMASK           253 drivers/net/dsa/mv88e6xxx/chip.c 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
GENMASK           299 drivers/net/dsa/mv88e6xxx/chip.c 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
GENMASK           313 drivers/net/dsa/mv88e6xxx/chip.c 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
GENMASK           619 drivers/net/dsa/mv88e6xxx/chip.h 	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
GENMASK            69 drivers/net/dsa/mv88e6xxx/serdes.h #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK	GENMASK(15, 14)
GENMASK            54 drivers/net/dsa/qca8k.h #define   QCA8K_MDIO_MASTER_DATA_MASK			GENMASK(15, 0)
GENMASK            60 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_STATUS_SPEED			GENMASK(1, 0)
GENMASK            73 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_HDR_CTRL_RX_MASK			GENMASK(3, 2)
GENMASK            75 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_HDR_CTRL_TX_MASK			GENMASK(1, 0)
GENMASK           122 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_LOOKUP_MEMBER			GENMASK(6, 0)
GENMASK           123 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_LOOKUP_STATE_MASK			GENMASK(18, 16)
GENMASK           129 drivers/net/dsa/qca8k.h #define   QCA8K_PORT_LOOKUP_STATE			GENMASK(18, 16)
GENMASK           137 drivers/net/dsa/qca8k.h #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M		GENMASK(17, 16)
GENMASK           275 drivers/net/dsa/rtl8366.c 			mask = GENMASK(smi->num_ports - 1, 0);
GENMASK            61 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_P4_IOMODE_MASK		GENMASK(9, 7)
GENMASK            63 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_P5_IOMODE_MASK		GENMASK(12, 10)
GENMASK            65 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_PMC0_SDSMODE_MASK		GENMASK(15, 13)
GENMASK           290 drivers/net/dsa/rtl8366rb.c #define RTL8366RB_INTERRUPT_LINK_CHGALL	GENMASK(11, 0)
GENMASK            72 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_SEED_MASK	GENMASK(26, 19)
GENMASK            80 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_TX_IPG_MASK	GENMASK(10, 6)
GENMASK            86 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MAC_CFG_CLK_SEL_MASK	GENMASK(2, 0)
GENMASK           113 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_FCCONF_PAUSE_VAL_MASK	GENMASK(15, 0)
GENMASK           134 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK	GENMASK(4, 1)
GENMASK           173 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_DEST_IDX_MASK		GENMASK(8, 3)
GENMASK           174 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_MACACCESS_CMD_MASK		GENMASK(2, 0)
GENMASK           187 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_VLANACCESS_VLAN_PORT_MASK	GENMASK(9, 2)
GENMASK           188 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK	GENMASK(2, 0)
GENMASK           231 drivers/net/dsa/vitesse-vsc73xx-core.c #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK	GENMASK(12, 8)
GENMASK          1032 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
GENMASK          1041 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
GENMASK          1044 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
GENMASK          1049 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
GENMASK          1050 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
GENMASK          1052 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
GENMASK          1058 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
GENMASK          1061 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
GENMASK          1093 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
GENMASK          1094 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
GENMASK          1107 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
GENMASK          1109 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
GENMASK          1111 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
GENMASK          1113 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
GENMASK          1114 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
GENMASK          1116 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
GENMASK          1118 drivers/net/ethernet/amazon/ena/ena_admin_defs.h #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
GENMASK           303 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_LENGTH_MASK                      GENMASK(15, 0)
GENMASK           305 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK                   GENMASK(21, 16)
GENMASK           316 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK                GENMASK(3, 0)
GENMASK           322 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK                GENMASK(12, 8)
GENMASK           332 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK                   GENMASK(31, 22)
GENMASK           333 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK                     GENMASK(15, 0)
GENMASK           335 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK               GENMASK(31, 24)
GENMASK           338 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK              GENMASK(9, 0)
GENMASK           342 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK                 GENMASK(19, 16)
GENMASK           357 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK              GENMASK(5, 0)
GENMASK           358 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK             GENMASK(7, 0)
GENMASK           360 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK             GENMASK(15, 8)
GENMASK           362 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK    GENMASK(21, 16)
GENMASK           364 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK                 GENMASK(31, 22)
GENMASK           379 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK          GENMASK(4, 0)
GENMASK           381 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK          GENMASK(6, 5)
GENMASK           383 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK          GENMASK(12, 8)
GENMASK           404 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK              GENMASK(14, 0)
GENMASK           406 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK              GENMASK(29, 15)
GENMASK           411 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK              GENMASK(7, 0)
GENMASK            62 drivers/net/ethernet/apm/xgene-v2/mac.h 	u32 mask = GENMASK(pos + len, pos);
GENMASK            70 drivers/net/ethernet/apm/xgene-v2/mac.h 	u32 mask = GENMASK(pos + len, pos);
GENMASK           227 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c 			mask = GENMASK(gstrings_extd_stats[i].mask - 1, 0);
GENMASK           113 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c 	ring_id_val = ring->id & GENMASK(9, 0);
GENMASK           116 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c 	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
GENMASK            23 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h 	u32 mask = GENMASK(end, start);
GENMASK            31 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h 	return (val & GENMASK(end, start)) >> start;
GENMASK            61 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CREATE_MASK(pos, len)		GENMASK((pos)+(len)-1, (pos))
GENMASK            71 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RING_OWNER_MASK		GENMASK(9, 6)
GENMASK            72 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define RING_BUFNUM_MASK	GENMASK(5, 0)
GENMASK           167 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_DSTQID0(val)		((val) & GENMASK(11, 0))
GENMASK           168 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_FPSEL0(val)		(((val) << 16) & GENMASK(19, 16))
GENMASK           180 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define CFG_CLE_NXTFPSEL0(val)		(((val) << 20) & GENMASK(23, 20))
GENMASK           313 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h #define DATALEN_MASK			GENMASK(11, 0)
GENMASK            47 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 		mask = GENMASK(13, 0);
GENMASK            49 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 	} else if (!(hw_len & GENMASK(13, 12))) {
GENMASK            50 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 		mask = GENMASK(11, 0);
GENMASK            53 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 		mask = GENMASK(11, 0);
GENMASK           136 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 	bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
GENMASK          1266 drivers/net/ethernet/apm/xgene/xgene_enet_main.c 	return (owner << 6) | (bufnum & GENMASK(5, 0));
GENMASK           105 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c 	ring_id_val = ring->id & GENMASK(9, 0);
GENMASK           108 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c 	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
GENMASK           166 drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c 	data |= (count & GENMASK(16, 0));
GENMASK            12 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define PHY_ADDR(src)		(((src)<<8) & GENMASK(12, 8))
GENMASK            13 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define REG_ADDR(src)		((src) & GENMASK(4, 0))
GENMASK            14 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define PHY_CONTROL(src)	((src) & GENMASK(15, 0))
GENMASK            15 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.h #define LINK_SPEED(src)		(((src) & GENMASK(11, 10)) >> 10)
GENMASK          3151 drivers/net/ethernet/broadcom/genet/bcmgenet.c 	reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
GENMASK          2509 drivers/net/ethernet/freescale/dpaa/dpaa_eth.c 	    ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) {
GENMASK            91 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h 	GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
GENMASK            49 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIMSGRR_MR_MASK	GENMASK(2, 1)
GENMASK            87 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PSIIER_MR_MASK	GENMASK(2, 1)
GENMASK           129 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TBMR_PRIO_MASK		GENMASK(2, 0)
GENMASK           150 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_PMR_EN	GENMASK(18, 16)
GENMASK           387 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define ENETC_TXBD_L3_START_MASK	GENMASK(6, 0)
GENMASK            28 drivers/net/ethernet/hisilicon/hisi_femac.c #define MAX_FRAME_SIZE_MASK		GENMASK(10, 0)
GENMASK            40 drivers/net/ethernet/hisilicon/hisi_femac.c #define RX_FRAME_LEN_MASK		GENMASK(11, 0)
GENMASK            45 drivers/net/ethernet/hisilicon/hisi_femac.c #define TX_CNT_INUSE_MASK		GENMASK(5, 0)
GENMASK            64 drivers/net/ethernet/hisilicon/hisi_femac.c #define IRQ_ENA_PORT0_MASK		GENMASK(7, 0)
GENMASK            77 drivers/net/ethernet/hisilicon/hisi_femac.c #define MACFLT_HI16_MASK		GENMASK(15, 0)
GENMASK           191 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
GENMASK           196 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_FW_VERSION_BYTE3_MASK	GENMASK(31, 24)
GENMASK           198 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_FW_VERSION_BYTE2_MASK	GENMASK(23, 16)
GENMASK           200 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_FW_VERSION_BYTE1_MASK	GENMASK(15, 8)
GENMASK           202 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define HNAE3_FW_VERSION_BYTE0_MASK	GENMASK(7, 0)
GENMASK           334 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_INT_TYPE_M	GENMASK(1, 0)
GENMASK           336 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_TQP_ID_M		GENMASK(12, 2)
GENMASK           338 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_INT_GL_IDX_M	GENMASK(14, 13)
GENMASK           448 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MSIX_OFT_ROCEE_M		GENMASK(15, 0)
GENMASK           450 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_PF_VEC_NUM_M		GENMASK(7, 0)
GENMASK           459 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_OFFSET_M	GENMASK(19, 0)
GENMASK           461 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_RD_LEN_M	GENMASK(27, 24)
GENMASK           466 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_VMDQ_M	GENMASK(7, 0)
GENMASK           468 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_TC_NUM_M	GENMASK(15, 8)
GENMASK           470 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_TQP_DESC_N_M	GENMASK(31, 16)
GENMASK           472 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_PHY_ADDR_M	GENMASK(7, 0)
GENMASK           474 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_MEDIA_TP_M	GENMASK(15, 8)
GENMASK           476 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_RX_BUF_LEN_M	GENMASK(31, 16)
GENMASK           478 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_MAC_ADDR_H_M	GENMASK(15, 0)
GENMASK           480 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_DEFAULT_SPEED_M	GENMASK(23, 16)
GENMASK           482 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_RSS_SIZE_M	GENMASK(31, 24)
GENMASK           484 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_SPEED_ABILITY_M	GENMASK(7, 0)
GENMASK           486 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_UMV_TBL_SPACE_M	GENMASK(31, 16)
GENMASK           534 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_RSS_TC_OFFSET_M		GENMASK(9, 0)
GENMASK           536 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_RSS_TC_SIZE_M		GENMASK(14, 12)
GENMASK           602 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_CFG_SPEED_M		GENMASK(5, 0)
GENMASK           615 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_RING_ID_MASK		GENMASK(9, 0)
GENMASK           644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_CFG_FEC_MODE_M	GENMASK(3, 1)
GENMASK           682 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_EPORT_VFID_M		GENMASK(10, 3)
GENMASK           684 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_MAC_EPORT_PFID_M		GENMASK(2, 0)
GENMASK           881 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_TSO_MSS_MIN_M	GENMASK(13, 0)
GENMASK           884 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_TSO_MSS_MAX_M	GENMASK(29, 16)
GENMASK           962 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_LED_LOCATE_STATE_M	GENMASK(1, 0)
GENMASK          1021 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_FD_AD_QID_M		GENMASK(12, 2)
GENMASK          1024 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_FD_AD_COUNTER_NUM_M	GENMASK(20, 13)
GENMASK          1027 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_FD_AD_NXT_KEY_M		GENMASK(26, 21)
GENMASK          1030 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define HCLGE_FD_AD_RULE_ID_M		GENMASK(13, 1)
GENMASK            56 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_MAC_TNL_INT_EN			GENMASK(9, 0)
GENMASK            57 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_MAC_TNL_INT_EN_MASK		GENMASK(9, 0)
GENMASK            58 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_MAC_TNL_INT_CLR			GENMASK(9, 0)
GENMASK            59 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN		GENMASK(31, 0)
GENMASK            60 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK	GENMASK(31, 0)
GENMASK            61 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN		GENMASK(31, 0)
GENMASK            62 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK	GENMASK(31, 0)
GENMASK            67 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN		GENMASK(7, 0)
GENMASK            68 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK	GENMASK(23, 16)
GENMASK            69 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_PF_ABNORMAL_INT_EN		GENMASK(5, 0)
GENMASK            70 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK	GENMASK(5, 0)
GENMASK            71 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN		GENMASK(31, 0)
GENMASK            72 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK	GENMASK(31, 0)
GENMASK            73 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN	GENMASK(31, 0)
GENMASK            74 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK	GENMASK(31, 0)
GENMASK            77 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_COMMON_INT_EN			GENMASK(9, 0)
GENMASK            78 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_COMMON_INT_EN_MASK		GENMASK(9, 0)
GENMASK            81 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN	GENMASK(23, 0)
GENMASK            82 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK	GENMASK(23, 0)
GENMASK            84 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_SSU_COMMON_ERR_INT_MASK	GENMASK(9, 0)
GENMASK            86 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_IGU_INT_MASK		GENMASK(3, 0)
GENMASK            87 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_IGU_EGU_TNL_INT_MASK	GENMASK(5, 0)
GENMASK            88 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPP_MPF_INT_ST3_MASK	GENMASK(5, 0)
GENMASK            89 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_PPU_MPF_INT_ST3_MASK	GENMASK(7, 0)
GENMASK            94 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_QCN_FIFO_INT_MASK		GENMASK(17, 0)
GENMASK            95 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_QCN_ECC_INT_MASK		GENMASK(21, 0)
GENMASK            96 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_NCSI_ECC_INT_MASK		GENMASK(1, 0)
GENMASK           104 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h #define HCLGE_ROCEE_AXI_ERR_INT_MASK		GENMASK(1, 0)
GENMASK          5028 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 					GENMASK(cur_pos + tuple_size, cur_pos),
GENMASK            92 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)
GENMASK            97 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_RSS_HASH_ALGO_MASK	GENMASK(3, 0)
GENMASK           101 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
GENMASK           102 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
GENMASK           137 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)
GENMASK           154 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_PF_ID_M			GENMASK(2, 0)
GENMASK           156 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_VF_ID_M			GENMASK(10, 3)
GENMASK           159 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_NETWORK_PORT_ID_M		GENMASK(3, 0)
GENMASK           169 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define HCLGE_RESET_INT_M		GENMASK(7, 5)
GENMASK            71 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
GENMASK            73 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_SHAP_IR_U_MSK  GENMASK(11, 8)
GENMASK            75 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_SHAP_IR_S_MSK  GENMASK(15, 12)
GENMASK            77 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_SHAP_BS_B_MSK  GENMASK(20, 16)
GENMASK            79 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_TM_SHAP_BS_S_MSK  GENMASK(25, 21)
GENMASK           101 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_BP_SUB_GRP_ID_M		GENMASK(4, 0)
GENMASK           103 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h #define HCLGE_BP_GRP_ID_M		GENMASK(9, 5)
GENMASK           120 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
GENMASK           121 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h #define HCLGEVF_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
GENMASK            67 drivers/net/ethernet/intel/igb/igb_ptp.c #define INCVALUE_82576_MASK		GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
GENMASK           994 drivers/net/ethernet/intel/igbvf/netdev.c 	adapter->eims_enable_mask = GENMASK(vector - 1, 0);
GENMASK          4220 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
GENMASK          4222 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
GENMASK           696 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 		hwaddr |= regnum & GENMASK(21, 0);
GENMASK           699 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
GENMASK           721 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
GENMASK           749 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 		hwaddr |= regnum & GENMASK(21, 0);
GENMASK           752 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
GENMASK           943 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c 	bus->phy_mask = GENMASK(31, 0);
GENMASK           169 drivers/net/ethernet/marvell/mvmdio.c 	return val & GENMASK(15, 0);
GENMASK           209 drivers/net/ethernet/marvell/mvmdio.c 	u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
GENMASK           219 drivers/net/ethernet/marvell/mvmdio.c 	writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
GENMASK           235 drivers/net/ethernet/marvell/mvmdio.c 	return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
GENMASK           242 drivers/net/ethernet/marvell/mvmdio.c 	u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
GENMASK           252 drivers/net/ethernet/marvell/mvmdio.c 	writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
GENMASK            70 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define     MVPP2_PRS_TCAM_HIT_CNT_MASK		GENMASK(15, 0)
GENMASK           408 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define     MVPP2_GMAC_FLOW_CTRL_MASK		GENMASK(2, 1)
GENMASK           350 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define DQSI0(x)		((x << 0) & GENMASK(6, 0))
GENMASK           351 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define DQSI1(x)		((x << 8) & GENMASK(14, 8))
GENMASK           352 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define RXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
GENMASK           362 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define TXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
GENMASK           400 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
GENMASK           433 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_LINK_TIMER_DEFAULT	(0x186a0 & GENMASK(19, 0))
GENMASK           448 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define SGMII_IF_MODE_MASK		GENMASK(5, 1)
GENMASK           804 drivers/net/ethernet/mediatek/mtk_eth_soc.h #define MTK_SGMII_PHYSPEED_MASK        GENMASK(2, 0)
GENMASK            26 drivers/net/ethernet/mellanox/mlxsw/core_thermal.c #define MLXSW_THERMAL_TEMP_SCORE_MAX	GENMASK(31, 0)
GENMASK           105 drivers/net/ethernet/mellanox/mlxsw/i2c.c 				   GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
GENMASK           106 drivers/net/ethernet/mellanox/mlxsw/i2c.c 	mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,
GENMASK           112 drivers/net/ethernet/mellanox/mlxsw/i2c.c 				    GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
GENMASK           113 drivers/net/ethernet/mellanox/mlxsw/i2c.c 	mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,
GENMASK            53 drivers/net/ethernet/mellanox/mlxsw/item.h 	tmp &= GENMASK(item->size.bits - 1, 0);
GENMASK            65 drivers/net/ethernet/mellanox/mlxsw/item.h 	u8 mask = GENMASK(item->size.bits - 1, 0) << item->shift;
GENMASK            87 drivers/net/ethernet/mellanox/mlxsw/item.h 	tmp &= GENMASK(item->size.bits - 1, 0);
GENMASK            99 drivers/net/ethernet/mellanox/mlxsw/item.h 	u16 mask = GENMASK(item->size.bits - 1, 0) << item->shift;
GENMASK           121 drivers/net/ethernet/mellanox/mlxsw/item.h 	tmp &= GENMASK(item->size.bits - 1, 0);
GENMASK           133 drivers/net/ethernet/mellanox/mlxsw/item.h 	u32 mask = GENMASK(item->size.bits - 1, 0) << item->shift;
GENMASK           238 drivers/net/ethernet/mellanox/mlxsw/item.h 	tmp &= GENMASK(item->element_size - 1, 0);
GENMASK           248 drivers/net/ethernet/mellanox/mlxsw/item.h 	u8 mask = GENMASK(item->element_size - 1, 0) << shift;
GENMASK          8197 drivers/net/ethernet/mellanox/mlxsw/reg.h 					  ((s16)((GENMASK(15, 0) + (v_) + 1) \
GENMASK           193 drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c 				       key->vrid, GENMASK(7, 0));
GENMASK           196 drivers/net/ethernet/mellanox/mlxsw/spectrum2_mr_tcam.c 				       key->vrid >> 8, GENMASK(2, 0));
GENMASK           333 drivers/net/ethernet/mscc/ocelot.c 	ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
GENMASK           345 drivers/net/ethernet/mscc/ocelot.c 	ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
GENMASK           694 drivers/net/ethernet/mscc/ocelot.c 	val = GENMASK(ocelot->num_phys_ports - 1, 0);
GENMASK          1548 drivers/net/ethernet/mscc/ocelot.c 		ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
GENMASK          2154 drivers/net/ethernet/mscc/ocelot.c 		u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
GENMASK          2159 drivers/net/ethernet/mscc/ocelot.c 			 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
GENMASK            75 drivers/net/ethernet/mscc/ocelot.h #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
GENMASK           163 drivers/net/ethernet/mscc/ocelot_ace.c 		mask = GENMASK(width, 0);
GENMASK           186 drivers/net/ethernet/mscc/ocelot_ace.c 	data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0);
GENMASK           203 drivers/net/ethernet/mscc/ocelot_ace.c 		data->tg_mask |= GENMASK(offset + width - 1, offset);
GENMASK            15 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_PID_VAL(x)                           (((x) << 14) & GENMASK(18, 14))
GENMASK            16 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_PID_VAL_M                            GENMASK(18, 14)
GENMASK            17 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_PID_VAL_X(x)                         (((x) & GENMASK(18, 14)) >> 14)
GENMASK            19 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_VID_VAL(x)                           ((x) & GENMASK(12, 0))
GENMASK            20 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_ANAGEFIL_VID_VAL_M                            GENMASK(12, 0)
GENMASK            24 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_RATE(x)                  (((x) << 3) & GENMASK(6, 3))
GENMASK            25 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_RATE_M                   GENMASK(6, 3)
GENMASK            26 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x)                (((x) & GENMASK(6, 3)) >> 3)
GENMASK            28 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_MODE(x)                  ((x) & GENMASK(1, 0))
GENMASK            29 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_STORMLIMIT_CFG_STORM_MODE_M                   GENMASK(1, 0)
GENMASK            32 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AUTOAGE_AGE_PERIOD(x)                         (((x) << 1) & GENMASK(20, 1))
GENMASK            33 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AUTOAGE_AGE_PERIOD_M                          GENMASK(20, 1)
GENMASK            34 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AUTOAGE_AGE_PERIOD_X(x)                       (((x) & GENMASK(20, 1)) >> 1)
GENMASK            40 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_FID_MASK(x)                          (((x) << 12) & GENMASK(23, 12))
GENMASK            41 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_FID_MASK_M                           GENMASK(23, 12)
GENMASK            42 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_AGENCTRL_FID_MASK_X(x)                        (((x) & GENMASK(23, 12)) >> 12)
GENMASK            58 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_UNICAST(x)                       (((x) << 12) & GENMASK(17, 12))
GENMASK            59 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_UNICAST_M                        GENMASK(17, 12)
GENMASK            60 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_UNICAST_X(x)                     (((x) & GENMASK(17, 12)) >> 12)
GENMASK            61 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_BROADCAST(x)                     (((x) << 6) & GENMASK(11, 6))
GENMASK            62 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_BROADCAST_M                      GENMASK(11, 6)
GENMASK            63 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_BROADCAST_X(x)                   (((x) & GENMASK(11, 6)) >> 6)
GENMASK            64 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_MULTICAST(x)                     ((x) & GENMASK(5, 0))
GENMASK            65 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_FLD_MULTICAST_M                      GENMASK(5, 0)
GENMASK            67 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x)                 (((x) << 18) & GENMASK(23, 18))
GENMASK            68 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M                  GENMASK(23, 18)
GENMASK            69 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x)               (((x) & GENMASK(23, 18)) >> 18)
GENMASK            70 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_DATA(x)                 (((x) << 12) & GENMASK(17, 12))
GENMASK            71 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_DATA_M                  GENMASK(17, 12)
GENMASK            72 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x)               (((x) & GENMASK(17, 12)) >> 12)
GENMASK            73 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x)                 (((x) << 6) & GENMASK(11, 6))
GENMASK            74 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M                  GENMASK(11, 6)
GENMASK            75 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x)               (((x) & GENMASK(11, 6)) >> 6)
GENMASK            76 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x)                 ((x) & GENMASK(5, 0))
GENMASK            77 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M                  GENMASK(5, 0)
GENMASK            81 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SFLOW_CFG_SF_RATE(x)                          (((x) << 2) & GENMASK(13, 2))
GENMASK            82 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SFLOW_CFG_SF_RATE_M                           GENMASK(13, 2)
GENMASK            83 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SFLOW_CFG_SF_RATE_X(x)                        (((x) & GENMASK(13, 2)) >> 2)
GENMASK            90 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_MODE_VLAN_PARSE_CFG(x)                   (((x) << 1) & GENMASK(2, 1))
GENMASK            91 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_MODE_VLAN_PARSE_CFG_M                    GENMASK(2, 1)
GENMASK            92 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x)                 (((x) & GENMASK(2, 1)) >> 1)
GENMASK            99 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PGID_PGID_PGID(x)                             ((x) & GENMASK(11, 0))
GENMASK           100 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PGID_PGID_PGID_M                              GENMASK(11, 0)
GENMASK           101 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PGID_PGID_CPUQ_DST_PGID(x)                    (((x) << 27) & GENMASK(29, 27))
GENMASK           102 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PGID_PGID_CPUQ_DST_PGID_M                     GENMASK(29, 27)
GENMASK           103 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PGID_PGID_CPUQ_DST_PGID_X(x)                  (((x) & GENMASK(29, 27)) >> 27)
GENMASK           105 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACHDATA_VID(x)                        (((x) << 16) & GENMASK(28, 16))
GENMASK           106 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACHDATA_VID_M                         GENMASK(28, 16)
GENMASK           107 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACHDATA_VID_X(x)                      (((x) & GENMASK(28, 16)) >> 16)
GENMASK           108 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACHDATA_MACHDATA(x)                   ((x) & GENMASK(15, 0))
GENMASK           109 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACHDATA_MACHDATA_M                    GENMASK(15, 0)
GENMASK           112 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SSID(x)                     (((x) << 9) & GENMASK(15, 9))
GENMASK           113 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SSID_M                      GENMASK(15, 9)
GENMASK           114 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SSID_X(x)                   (((x) & GENMASK(15, 9)) >> 9)
GENMASK           116 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SFID(x)                     ((x) & GENMASK(7, 0))
GENMASK           117 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMDATA_SFID_M                      GENMASK(7, 0)
GENMASK           124 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_ENTRYTYPE(x)                 (((x) << 9) & GENMASK(10, 9))
GENMASK           125 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_ENTRYTYPE_M                  GENMASK(10, 9)
GENMASK           126 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x)               (((x) & GENMASK(10, 9)) >> 9)
GENMASK           127 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_DEST_IDX(x)                  (((x) << 3) & GENMASK(8, 3))
GENMASK           128 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_DEST_IDX_M                   GENMASK(8, 3)
GENMASK           129 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_DEST_IDX_X(x)                (((x) & GENMASK(8, 3)) >> 3)
GENMASK           130 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x)             ((x) & GENMASK(2, 0))
GENMASK           131 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M              GENMASK(2, 0)
GENMASK           141 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x)           (((x) << 2) & GENMASK(13, 2))
GENMASK           142 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M            GENMASK(13, 2)
GENMASK           143 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x)         (((x) & GENMASK(13, 2)) >> 2)
GENMASK           144 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x)             ((x) & GENMASK(1, 0))
GENMASK           145 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M              GENMASK(1, 0)
GENMASK           156 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_V_INDEX(x)                    ((x) & GENMASK(11, 0))
GENMASK           157 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_VLANTIDX_V_INDEX_M                     GENMASK(11, 0)
GENMASK           159 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x)           (((x) << 2) & GENMASK(8, 2))
GENMASK           160 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M            GENMASK(8, 2)
GENMASK           161 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x)         (((x) & GENMASK(8, 2)) >> 2)
GENMASK           162 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x)             ((x) & GENMASK(1, 0))
GENMASK           163 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M              GENMASK(1, 0)
GENMASK           165 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x)                 (((x) << 21) & GENMASK(28, 21))
GENMASK           166 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M                  GENMASK(28, 21)
GENMASK           167 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x)               (((x) & GENMASK(28, 21)) >> 21)
GENMASK           168 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x)                  (((x) << 15) & GENMASK(20, 15))
GENMASK           169 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M                   GENMASK(20, 15)
GENMASK           170 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x)                (((x) & GENMASK(20, 15)) >> 15)
GENMASK           173 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x)                 ((x) & GENMASK(7, 0))
GENMASK           174 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M                  GENMASK(7, 0)
GENMASK           178 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ENTRYLIM_ENTRYLIM(x)                   (((x) << 14) & GENMASK(17, 14))
GENMASK           179 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ENTRYLIM_ENTRYLIM_M                    GENMASK(17, 14)
GENMASK           180 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x)                 (((x) & GENMASK(17, 14)) >> 14)
GENMASK           181 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x)                  ((x) & GENMASK(13, 0))
GENMASK           182 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M                   GENMASK(13, 0)
GENMASK           184 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x)        (((x) << 4) & GENMASK(31, 4))
GENMASK           185 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M         GENMASK(31, 4)
GENMASK           186 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x)      (((x) & GENMASK(31, 4)) >> 4)
GENMASK           189 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x)         ((x) & GENMASK(1, 0))
GENMASK           190 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M          GENMASK(1, 0)
GENMASK           192 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x)       (((x) << 30) & GENMASK(31, 30))
GENMASK           193 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M        GENMASK(31, 30)
GENMASK           194 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x)     (((x) & GENMASK(31, 30)) >> 30)
GENMASK           195 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_S_INDEX(x)                  (((x) << 16) & GENMASK(22, 16))
GENMASK           196 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_S_INDEX_M                   GENMASK(22, 16)
GENMASK           197 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_S_INDEX_X(x)                (((x) & GENMASK(22, 16)) >> 16)
GENMASK           199 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x)          (((x) << 8) & GENMASK(13, 8))
GENMASK           200 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M           GENMASK(13, 8)
GENMASK           201 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x)        (((x) & GENMASK(13, 8)) >> 8)
GENMASK           205 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x)           ((x) & GENMASK(4, 0))
GENMASK           206 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M            GENMASK(4, 0)
GENMASK           208 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x)                 (((x) << 16) & GENMASK(22, 16))
GENMASK           209 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M                  GENMASK(22, 16)
GENMASK           210 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x)               (((x) & GENMASK(22, 16)) >> 16)
GENMASK           211 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x)            ((x) & GENMASK(6, 0))
GENMASK           212 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M             GENMASK(6, 0)
GENMASK           214 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x)             (((x) << 1) & GENMASK(7, 1))
GENMASK           215 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M              GENMASK(7, 1)
GENMASK           216 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x)           (((x) & GENMASK(7, 1)) >> 1)
GENMASK           220 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_IGR_PRIO(x)                 (((x) << 19) & GENMASK(21, 19))
GENMASK           221 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_IGR_PRIO_M                  GENMASK(21, 19)
GENMASK           222 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x)               (((x) & GENMASK(21, 19)) >> 19)
GENMASK           224 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x)              (((x) << 2) & GENMASK(17, 2))
GENMASK           225 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M               GENMASK(17, 2)
GENMASK           226 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x)            (((x) & GENMASK(17, 2)) >> 2)
GENMASK           227 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x)             ((x) & GENMASK(1, 0))
GENMASK           228 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M              GENMASK(1, 0)
GENMASK           231 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SGID(x)                       (((x) << 18) & GENMASK(25, 18))
GENMASK           232 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SGID_M                        GENMASK(25, 18)
GENMASK           233 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SGID_X(x)                     (((x) & GENMASK(25, 18)) >> 18)
GENMASK           235 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_POL_IDX(x)                    (((x) << 8) & GENMASK(16, 8))
GENMASK           236 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_POL_IDX_M                     GENMASK(16, 8)
GENMASK           237 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_POL_IDX_X(x)                  (((x) & GENMASK(16, 8)) >> 8)
GENMASK           238 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SFID_INDEX(x)                 ((x) & GENMASK(7, 0))
GENMASK           239 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_TABLES_SFIDTIDX_SFID_INDEX_M                  GENMASK(7, 0)
GENMASK           245 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_ACCESS_CTRL_SGID(x)                        ((x) & GENMASK(7, 0))
GENMASK           246 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_ACCESS_CTRL_SGID_M                         GENMASK(7, 0)
GENMASK           249 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x)          ((x) & GENMASK(15, 0))
GENMASK           250 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M           GENMASK(15, 0)
GENMASK           251 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x)                (((x) << 16) & GENMASK(18, 16))
GENMASK           252 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M                 GENMASK(18, 16)
GENMASK           253 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x)              (((x) & GENMASK(18, 16)) >> 16)
GENMASK           255 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_INIT_IPS(x)                   (((x) << 24) & GENMASK(27, 24))
GENMASK           256 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_INIT_IPS_M                    GENMASK(27, 24)
GENMASK           257 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x)                 (((x) & GENMASK(27, 24)) >> 24)
GENMASK           262 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_GCL_GS_CONFIG_IPS(x)                       ((x) & GENMASK(3, 0))
GENMASK           263 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_GCL_GS_CONFIG_IPS_M                        GENMASK(3, 0)
GENMASK           268 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x)       ((x) & GENMASK(15, 0))
GENMASK           269 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M        GENMASK(15, 0)
GENMASK           271 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_IPS(x)                        (((x) << 20) & GENMASK(23, 20))
GENMASK           272 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_IPS_M                         GENMASK(23, 20)
GENMASK           273 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_SG_STATUS_REG_3_IPS_X(x)                      (((x) & GENMASK(23, 20)) >> 20)
GENMASK           280 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x)                 (((x) << 18) & GENMASK(19, 18))
GENMASK           281 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M                  GENMASK(19, 18)
GENMASK           282 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x)               (((x) & GENMASK(19, 18)) >> 18)
GENMASK           286 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_PCP(x)                     (((x) << 12) & GENMASK(14, 12))
GENMASK           287 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_PCP_M                      GENMASK(14, 12)
GENMASK           288 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x)                   (((x) & GENMASK(14, 12)) >> 12)
GENMASK           289 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_VID(x)                     ((x) & GENMASK(11, 0))
GENMASK           290 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VLAN_CFG_VLAN_VID_M                      GENMASK(11, 0)
GENMASK           305 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x)               (((x) << 5) & GENMASK(7, 5))
GENMASK           306 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M                GENMASK(7, 5)
GENMASK           307 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x)             (((x) & GENMASK(7, 5)) >> 5)
GENMASK           311 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x)                 ((x) & GENMASK(1, 0))
GENMASK           312 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M                  GENMASK(1, 0)
GENMASK           317 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x)              (((x) << 11) & GENMASK(13, 11))
GENMASK           318 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M               GENMASK(13, 11)
GENMASK           319 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x)            (((x) & GENMASK(13, 11)) >> 11)
GENMASK           320 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x)        (((x) << 8) & GENMASK(10, 8))
GENMASK           321 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M         GENMASK(10, 8)
GENMASK           322 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x)      (((x) & GENMASK(10, 8)) >> 8)
GENMASK           323 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_PAG_VAL(x)                      ((x) & GENMASK(7, 0))
GENMASK           324 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_CFG_PAG_VAL_M                       GENMASK(7, 0)
GENMASK           329 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x)        (((x) << 4) & GENMASK(6, 4))
GENMASK           330 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M         GENMASK(6, 4)
GENMASK           331 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x)      (((x) & GENMASK(6, 4)) >> 4)
GENMASK           332 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x)        (((x) << 2) & GENMASK(3, 2))
GENMASK           333 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M         GENMASK(3, 2)
GENMASK           334 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x)      (((x) & GENMASK(3, 2)) >> 2)
GENMASK           335 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x)      ((x) & GENMASK(1, 0))
GENMASK           336 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M       GENMASK(1, 0)
GENMASK           340 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x)        (((x) << 17) & GENMASK(18, 17))
GENMASK           341 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M         GENMASK(18, 17)
GENMASK           342 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x)      (((x) & GENMASK(18, 17)) >> 17)
GENMASK           343 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x)      (((x) << 15) & GENMASK(16, 15))
GENMASK           344 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M       GENMASK(16, 15)
GENMASK           345 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x)    (((x) & GENMASK(16, 15)) >> 15)
GENMASK           347 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x)               (((x) << 12) & GENMASK(13, 12))
GENMASK           348 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M                GENMASK(13, 12)
GENMASK           349 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x)             (((x) & GENMASK(13, 12)) >> 12)
GENMASK           350 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x)                (((x) << 10) & GENMASK(11, 10))
GENMASK           351 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M                 GENMASK(11, 10)
GENMASK           352 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x)              (((x) & GENMASK(11, 10)) >> 10)
GENMASK           353 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x)          (((x) << 8) & GENMASK(9, 8))
GENMASK           354 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M           GENMASK(9, 8)
GENMASK           355 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x)        (((x) & GENMASK(9, 8)) >> 8)
GENMASK           356 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x)           (((x) << 6) & GENMASK(7, 6))
GENMASK           357 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M            GENMASK(7, 6)
GENMASK           358 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x)         (((x) & GENMASK(7, 6)) >> 6)
GENMASK           359 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x)                (((x) << 2) & GENMASK(5, 2))
GENMASK           360 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M                 GENMASK(5, 2)
GENMASK           361 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x)              (((x) & GENMASK(5, 2)) >> 2)
GENMASK           362 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x)                ((x) & GENMASK(1, 0))
GENMASK           363 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M                 GENMASK(1, 0)
GENMASK           369 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x)           ((x) & GENMASK(2, 0))
GENMASK           370 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M            GENMASK(2, 0)
GENMASK           385 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x)        (((x) << 16) & GENMASK(31, 16))
GENMASK           386 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M         GENMASK(31, 16)
GENMASK           387 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x)      (((x) & GENMASK(31, 16)) >> 16)
GENMASK           388 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x)       ((x) & GENMASK(15, 0))
GENMASK           389 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M        GENMASK(15, 0)
GENMASK           393 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x)        (((x) << 16) & GENMASK(31, 16))
GENMASK           394 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M         GENMASK(31, 16)
GENMASK           395 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x)      (((x) & GENMASK(31, 16)) >> 16)
GENMASK           396 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x)       ((x) & GENMASK(15, 0))
GENMASK           397 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M        GENMASK(15, 0)
GENMASK           401 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x)          (((x) << 16) & GENMASK(31, 16))
GENMASK           402 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M           GENMASK(31, 16)
GENMASK           403 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x)        (((x) & GENMASK(31, 16)) >> 16)
GENMASK           404 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x)         ((x) & GENMASK(15, 0))
GENMASK           405 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M          GENMASK(15, 0)
GENMASK           419 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_PORTID_VAL(x)                   (((x) << 2) & GENMASK(5, 2))
GENMASK           420 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_PORTID_VAL_M                    GENMASK(5, 2)
GENMASK           421 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_PORT_CFG_PORTID_VAL_X(x)                 (((x) & GENMASK(5, 2)) >> 2)
GENMASK           430 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x)                 (((x) << 9) & GENMASK(16, 9))
GENMASK           431 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M                  GENMASK(16, 9)
GENMASK           432 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x)               (((x) & GENMASK(16, 9)) >> 9)
GENMASK           433 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_POL_ORDER(x)                     ((x) & GENMASK(8, 0))
GENMASK           434 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_POL_CFG_POL_ORDER_M                      GENMASK(8, 0)
GENMASK           448 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_SFID_CFG_SFID(x)                         ((x) & GENMASK(7, 0))
GENMASK           449 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PORT_SFID_CFG_SFID_M                          GENMASK(7, 0)
GENMASK           453 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PFC_PFC_CFG_RX_PFC_ENA(x)                     (((x) << 2) & GENMASK(9, 2))
GENMASK           454 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PFC_PFC_CFG_RX_PFC_ENA_M                      GENMASK(9, 2)
GENMASK           455 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x)                   (((x) & GENMASK(9, 2)) >> 2)
GENMASK           456 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x)                  ((x) & GENMASK(1, 0))
GENMASK           457 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M                   GENMASK(1, 0)
GENMASK           464 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x)                  (((x) << 6) & GENMASK(10, 6))
GENMASK           465 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M                   GENMASK(10, 6)
GENMASK           466 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x)                (((x) & GENMASK(10, 6)) >> 6)
GENMASK           467 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x)                    (((x) << 1) & GENMASK(5, 1))
GENMASK           468 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M                     GENMASK(5, 1)
GENMASK           469 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x)                  (((x) & GENMASK(5, 1)) >> 1)
GENMASK           474 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_IPT_CFG(x)                            (((x) << 15) & GENMASK(16, 15))
GENMASK           475 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_IPT_CFG_M                             GENMASK(16, 15)
GENMASK           476 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_IPT_CFG_X(x)                          (((x) & GENMASK(16, 15)) >> 15)
GENMASK           477 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_ISDX_P(x)                             (((x) << 7) & GENMASK(14, 7))
GENMASK           478 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_ISDX_P_M                              GENMASK(14, 7)
GENMASK           479 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_ISDX_P_X(x)                           (((x) & GENMASK(14, 7)) >> 7)
GENMASK           480 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_PPT_IDX(x)                            ((x) & GENMASK(6, 0))
GENMASK           481 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_IPT_IPT_PPT_IDX_M                             GENMASK(6, 0)
GENMASK           487 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_MAP_FID_MAP_FID_C_VAL(x)                  (((x) << 6) & GENMASK(11, 6))
GENMASK           488 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_MAP_FID_MAP_FID_C_VAL_M                   GENMASK(11, 6)
GENMASK           489 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x)                (((x) & GENMASK(11, 6)) >> 6)
GENMASK           490 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_MAP_FID_MAP_FID_B_VAL(x)                  ((x) & GENMASK(5, 0))
GENMASK           491 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_FID_MAP_FID_MAP_FID_B_VAL_M                   GENMASK(5, 0)
GENMASK           502 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MLD(x)                          (((x) << 27) & GENMASK(29, 27))
GENMASK           503 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MLD_M                           GENMASK(29, 27)
GENMASK           504 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MLD_X(x)                        (((x) & GENMASK(29, 27)) >> 27)
GENMASK           505 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IGMP(x)                         (((x) << 24) & GENMASK(26, 24))
GENMASK           506 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IGMP_M                          GENMASK(26, 24)
GENMASK           507 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IGMP_X(x)                       (((x) & GENMASK(26, 24)) >> 24)
GENMASK           508 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x)                    (((x) << 21) & GENMASK(23, 21))
GENMASK           509 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M                     GENMASK(23, 21)
GENMASK           510 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x)                  (((x) & GENMASK(23, 21)) >> 21)
GENMASK           511 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x)                    (((x) << 18) & GENMASK(20, 18))
GENMASK           512 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M                     GENMASK(20, 18)
GENMASK           513 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x)                  (((x) & GENMASK(20, 18)) >> 18)
GENMASK           514 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x)              (((x) << 15) & GENMASK(17, 15))
GENMASK           515 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M               GENMASK(17, 15)
GENMASK           516 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x)            (((x) & GENMASK(17, 15)) >> 15)
GENMASK           517 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x)                     (((x) << 12) & GENMASK(14, 12))
GENMASK           518 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M                      GENMASK(14, 12)
GENMASK           519 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x)                   (((x) & GENMASK(14, 12)) >> 12)
GENMASK           520 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x)                     (((x) << 9) & GENMASK(11, 9))
GENMASK           521 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M                      GENMASK(11, 9)
GENMASK           522 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x)                   (((x) & GENMASK(11, 9)) >> 9)
GENMASK           523 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LRN(x)                          (((x) << 6) & GENMASK(8, 6))
GENMASK           524 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LRN_M                           GENMASK(8, 6)
GENMASK           525 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_LRN_X(x)                        (((x) & GENMASK(8, 6)) >> 6)
GENMASK           526 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MIRROR(x)                       (((x) << 3) & GENMASK(5, 3))
GENMASK           527 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MIRROR_M                        GENMASK(5, 3)
GENMASK           528 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x)                     (((x) & GENMASK(5, 3)) >> 3)
GENMASK           529 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_SFLOW(x)                        ((x) & GENMASK(2, 0))
GENMASK           530 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_CFG_CPUQ_SFLOW_M                         GENMASK(2, 0)
GENMASK           534 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x)                (((x) << 6) & GENMASK(8, 6))
GENMASK           535 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M                 GENMASK(8, 6)
GENMASK           536 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x)              (((x) & GENMASK(8, 6)) >> 6)
GENMASK           537 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x)                (((x) << 3) & GENMASK(5, 3))
GENMASK           538 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M                 GENMASK(5, 3)
GENMASK           539 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x)              (((x) & GENMASK(5, 3)) >> 3)
GENMASK           540 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x)                 ((x) & GENMASK(2, 0))
GENMASK           541 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M                  GENMASK(2, 0)
GENMASK           546 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_QOS_DSCP_VAL(x)                      (((x) << 8) & GENMASK(10, 8))
GENMASK           547 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_QOS_DSCP_VAL_M                       GENMASK(10, 8)
GENMASK           548 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x)                    (((x) & GENMASK(10, 8)) >> 8)
GENMASK           549 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x)                (((x) << 2) & GENMASK(7, 2))
GENMASK           550 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M                 GENMASK(7, 2)
GENMASK           551 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x)              (((x) & GENMASK(7, 2)) >> 2)
GENMASK           561 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x)          (((x) << 16) & GENMASK(31, 16))
GENMASK           562 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M           GENMASK(31, 16)
GENMASK           563 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x)        (((x) & GENMASK(31, 16)) >> 16)
GENMASK           564 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x)          ((x) & GENMASK(15, 0))
GENMASK           565 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M           GENMASK(15, 0)
GENMASK           568 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VRAP_CFG_VRAP_VID(x)                          ((x) & GENMASK(11, 0))
GENMASK           569 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_VRAP_CFG_VRAP_VID_M                           GENMASK(11, 0)
GENMASK           580 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_PIR_CFG_PIR_RATE(x)                       (((x) << 6) & GENMASK(20, 6))
GENMASK           581 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_PIR_CFG_PIR_RATE_M                        GENMASK(20, 6)
GENMASK           582 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_PIR_CFG_PIR_RATE_X(x)                     (((x) & GENMASK(20, 6)) >> 6)
GENMASK           583 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_PIR_CFG_PIR_BURST(x)                      ((x) & GENMASK(5, 0))
GENMASK           584 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_PIR_CFG_PIR_BURST_M                       GENMASK(5, 0)
GENMASK           588 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_CIR_CFG_CIR_RATE(x)                       (((x) << 6) & GENMASK(20, 6))
GENMASK           589 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_CIR_CFG_CIR_RATE_M                        GENMASK(20, 6)
GENMASK           590 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_CIR_CFG_CIR_RATE_X(x)                     (((x) & GENMASK(20, 6)) >> 6)
GENMASK           591 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_CIR_CFG_CIR_BURST(x)                      ((x) & GENMASK(5, 0))
GENMASK           592 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_CIR_CFG_CIR_BURST_M                       GENMASK(5, 0)
GENMASK           596 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_IPG_SIZE(x)                      (((x) << 5) & GENMASK(9, 5))
GENMASK           597 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_IPG_SIZE_M                       GENMASK(9, 5)
GENMASK           598 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_IPG_SIZE_X(x)                    (((x) & GENMASK(9, 5)) >> 5)
GENMASK           599 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_FRM_MODE(x)                      (((x) << 3) & GENMASK(4, 3))
GENMASK           600 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_FRM_MODE_M                       GENMASK(4, 3)
GENMASK           601 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_MODE_CFG_FRM_MODE_X(x)                    (((x) & GENMASK(4, 3)) >> 3)
GENMASK           616 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_HYST_POL_FC_HYST(x)                       (((x) << 4) & GENMASK(9, 4))
GENMASK           617 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_HYST_POL_FC_HYST_M                        GENMASK(9, 4)
GENMASK           618 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_HYST_POL_FC_HYST_X(x)                     (((x) & GENMASK(9, 4)) >> 4)
GENMASK           619 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_HYST_POL_STOP_HYST(x)                     ((x) & GENMASK(3, 0))
GENMASK           620 drivers/net/ethernet/mscc/ocelot_ana.h #define ANA_POL_HYST_POL_STOP_HYST_M                      GENMASK(3, 0)
GENMASK            19 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_LINK_SPEED(x)                       ((x) & GENMASK(1, 0))
GENMASK            20 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_CLOCK_CFG_LINK_SPEED_M                        GENMASK(1, 0)
GENMASK            35 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_AGE(x)                      (((x) << 15) & GENMASK(21, 15))
GENMASK            36 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_AGE_M                       GENMASK(21, 15)
GENMASK            37 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x)                    (((x) & GENMASK(21, 15)) >> 15)
GENMASK            38 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x)                   (((x) << 8) & GENMASK(14, 8))
GENMASK            39 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M                    GENMASK(14, 8)
GENMASK            40 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x)                 (((x) & GENMASK(14, 8)) >> 8)
GENMASK            41 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x)                  (((x) << 1) & GENMASK(7, 1))
GENMASK            42 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M                   GENMASK(7, 1)
GENMASK            43 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x)                (((x) & GENMASK(7, 1)) >> 1)
GENMASK            52 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
GENMASK            53 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
GENMASK            54 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
GENMASK            55 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x)      ((x) & GENMASK(3, 0))
GENMASK            56 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M       GENMASK(3, 0)
GENMASK            73 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
GENMASK            74 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
GENMASK            75 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
GENMASK            88 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_TX_IFG(x)                         (((x) << 8) & GENMASK(12, 8))
GENMASK            89 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_TX_IFG_M                          GENMASK(12, 8)
GENMASK            90 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_TX_IFG_X(x)                       (((x) & GENMASK(12, 8)) >> 8)
GENMASK            91 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
GENMASK            92 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
GENMASK            93 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
GENMASK            94 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RX_IFG1(x)                        ((x) & GENMASK(3, 0))
GENMASK            95 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_IFG_CFG_RX_IFG1_M                         GENMASK(3, 0)
GENMASK           102 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_SEED(x)                           (((x) << 16) & GENMASK(23, 16))
GENMASK           103 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_SEED_M                            GENMASK(23, 16)
GENMASK           104 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_SEED_X(x)                         (((x) & GENMASK(23, 16)) >> 16)
GENMASK           107 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_LATE_COL_POS(x)                   ((x) & GENMASK(6, 0))
GENMASK           108 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_MAC_HDX_CFG_LATE_COL_POS_M                    GENMASK(6, 0)
GENMASK           151 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_ADV_ABILITY(x)                     (((x) << 16) & GENMASK(31, 16))
GENMASK           152 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_ADV_ABILITY_M                      GENMASK(31, 16)
GENMASK           153 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x)                   (((x) & GENMASK(31, 16)) >> 16)
GENMASK           160 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_NP_CFG_NP_TX(x)                        (((x) << 16) & GENMASK(31, 16))
GENMASK           161 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_NP_CFG_NP_TX_M                         GENMASK(31, 16)
GENMASK           162 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_NP_CFG_NP_TX_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
GENMASK           181 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x)               (((x) << 16) & GENMASK(31, 16))
GENMASK           182 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M                GENMASK(31, 16)
GENMASK           183 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x)             (((x) & GENMASK(31, 16)) >> 16)
GENMASK           192 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_DELAY_VAR(x)                    (((x) << 12) & GENMASK(15, 12))
GENMASK           193 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_DELAY_VAR_M                     GENMASK(15, 12)
GENMASK           194 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LINK_STATUS_DELAY_VAR_X(x)                  (((x) & GENMASK(15, 12)) >> 12)
GENMASK           213 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_LPI_RX_WTIM(x)                      (((x) << 4) & GENMASK(5, 4))
GENMASK           214 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_LPI_RX_WTIM_M                       GENMASK(5, 4)
GENMASK           215 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x)                    (((x) & GENMASK(5, 4)) >> 4)
GENMASK           234 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x)                (((x) << 8) & GENMASK(15, 8))
GENMASK           235 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M                 GENMASK(15, 8)
GENMASK           236 drivers/net/ethernet/mscc/ocelot_dev.h #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x)              (((x) & GENMASK(15, 8)) >> 8)
GENMASK           247 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_RXBITSEL(x)                     (((x) << 12) & GENMASK(15, 12))
GENMASK           248 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_RXBITSEL_M                      GENMASK(15, 12)
GENMASK           249 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_RXBITSEL_X(x)                   (((x) & GENMASK(15, 12)) >> 12)
GENMASK           250 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SIGDET_CFG(x)                   (((x) << 9) & GENMASK(10, 9))
GENMASK           251 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SIGDET_CFG_M                    GENMASK(10, 9)
GENMASK           252 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x)                 (((x) & GENMASK(10, 9)) >> 9)
GENMASK           254 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x)                (((x) << 4) & GENMASK(7, 4))
GENMASK           255 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M                 GENMASK(7, 4)
GENMASK           256 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x)              (((x) & GENMASK(7, 4)) >> 4)
GENMASK           264 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x)              (((x) << 8) & GENMASK(11, 8))
GENMASK           265 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M               GENMASK(11, 8)
GENMASK           266 drivers/net/ethernet/mscc/ocelot_dev.h #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x)            (((x) & GENMASK(11, 8)) >> 8)
GENMASK            62 drivers/net/ethernet/mscc/ocelot_police.c 			ipg = min_t(u8, GENMASK(4, 0), conf->ipg);
GENMASK           102 drivers/net/ethernet/mscc/ocelot_police.c 			pbs_max = GENMASK(6, 0); /* Limit burst size */
GENMASK           119 drivers/net/ethernet/mscc/ocelot_police.c 		pir = GENMASK(15, 0);
GENMASK           125 drivers/net/ethernet/mscc/ocelot_police.c 	if (pir > GENMASK(15, 0)) {
GENMASK           130 drivers/net/ethernet/mscc/ocelot_police.c 	if (cir > GENMASK(15, 0)) {
GENMASK           159 drivers/net/ethernet/mscc/ocelot_police.c 			 (pir_discard ? GENMASK(22, 0) : 0),
GENMASK           168 drivers/net/ethernet/mscc/ocelot_police.c 			 (cir_discard ? GENMASK(22, 0) : 0),
GENMASK            24 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
GENMASK            25 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_GRP_CFG_MODE_M                             GENMASK(3, 2)
GENMASK            26 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
GENMASK            34 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_DP_WM(x)                               (((x) << 5) & GENMASK(7, 5))
GENMASK            35 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_DP_WM_M                                GENMASK(7, 5)
GENMASK            36 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_DP_WM_X(x)                             (((x) & GENMASK(7, 5)) >> 5)
GENMASK            37 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_SCH_WM(x)                              (((x) << 2) & GENMASK(4, 2))
GENMASK            38 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_SCH_WM_M                               GENMASK(4, 2)
GENMASK            39 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_SCH_WM_X(x)                            (((x) & GENMASK(4, 2)) >> 2)
GENMASK            40 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_OFLW_ERR_STICKY(x)                     ((x) & GENMASK(1, 0))
GENMASK            41 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_XTR_CFG_OFLW_ERR_STICKY_M                      GENMASK(1, 0)
GENMASK            45 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
GENMASK            46 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_GRP_CFG_MODE_M                             GENMASK(3, 2)
GENMASK            47 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
GENMASK            54 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_GAP_SIZE(x)                           (((x) << 21) & GENMASK(24, 21))
GENMASK            55 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_GAP_SIZE_M                            GENMASK(24, 21)
GENMASK            56 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_GAP_SIZE_X(x)                         (((x) & GENMASK(24, 21)) >> 21)
GENMASK            60 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_VLD_BYTES(x)                          (((x) << 16) & GENMASK(17, 16))
GENMASK            61 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_VLD_BYTES_M                           GENMASK(17, 16)
GENMASK            62 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_CTRL_VLD_BYTES_X(x)                        (((x) & GENMASK(17, 16)) >> 16)
GENMASK            64 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_WMARK_REACHED(x)                    (((x) << 4) & GENMASK(5, 4))
GENMASK            65 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_WMARK_REACHED_M                     GENMASK(5, 4)
GENMASK            66 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_WMARK_REACHED_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
GENMASK            67 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_FIFO_RDY(x)                         (((x) << 2) & GENMASK(3, 2))
GENMASK            68 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_FIFO_RDY_M                          GENMASK(3, 2)
GENMASK            69 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_FIFO_RDY_X(x)                       (((x) & GENMASK(3, 2)) >> 2)
GENMASK            70 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_INJ_IN_PROGRESS(x)                  ((x) & GENMASK(1, 0))
GENMASK            71 drivers/net/ethernet/mscc/ocelot_qs.h #define QS_INJ_STATUS_INJ_IN_PROGRESS_M                   GENMASK(1, 0)
GENMASK            19 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x)             (((x) << 11) & GENMASK(13, 11))
GENMASK            20 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M              GENMASK(13, 11)
GENMASK            21 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x)           (((x) & GENMASK(13, 11)) >> 11)
GENMASK            24 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x)               (((x) << 1) & GENMASK(8, 1))
GENMASK            25 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M                GENMASK(8, 1)
GENMASK            26 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x)             (((x) & GENMASK(8, 1)) >> 1)
GENMASK            38 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x)                  (((x) << 8) & GENMASK(15, 8))
GENMASK            39 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M                   GENMASK(15, 8)
GENMASK            40 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x)                (((x) & GENMASK(15, 8)) >> 8)
GENMASK            41 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x)                 ((x) & GENMASK(7, 0))
GENMASK            42 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M                  GENMASK(7, 0)
GENMASK            46 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x)                  (((x) << 8) & GENMASK(12, 8))
GENMASK            47 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M                   GENMASK(12, 8)
GENMASK            48 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x)                (((x) & GENMASK(12, 8)) >> 8)
GENMASK            49 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x)                  ((x) & GENMASK(7, 0))
GENMASK            50 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M                   GENMASK(7, 0)
GENMASK            54 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_BASE(x)                              (((x) << 5) & GENMASK(12, 5))
GENMASK            55 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_BASE_M                               GENMASK(12, 5)
GENMASK            56 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_BASE_X(x)                            (((x) & GENMASK(12, 5)) >> 5)
GENMASK            57 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_IDX_SEL(x)                           (((x) << 2) & GENMASK(4, 2))
GENMASK            58 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_IDX_SEL_M                            GENMASK(4, 2)
GENMASK            59 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_IDX_SEL_X(x)                         (((x) & GENMASK(4, 2)) >> 2)
GENMASK            60 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_INP_SEL(x)                           ((x) & GENMASK(1, 0))
GENMASK            61 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_QMAP_SE_INP_SEL_M                            GENMASK(1, 0)
GENMASK            67 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x)               (((x) << 9) & GENMASK(18, 9))
GENMASK            68 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M                GENMASK(18, 9)
GENMASK            69 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x)             (((x) & GENMASK(18, 9)) >> 9)
GENMASK            72 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x)            ((x) & GENMASK(6, 0))
GENMASK            73 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M             GENMASK(6, 0)
GENMASK            77 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RED_PROFILE_WM_RED_LOW(x)                    (((x) << 8) & GENMASK(15, 8))
GENMASK            78 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RED_PROFILE_WM_RED_LOW_M                     GENMASK(15, 8)
GENMASK            79 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RED_PROFILE_WM_RED_LOW_X(x)                  (((x) & GENMASK(15, 8)) >> 8)
GENMASK            80 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RED_PROFILE_WM_RED_HIGH(x)                   ((x) & GENMASK(7, 0))
GENMASK            81 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RED_PROFILE_WM_RED_HIGH_M                    GENMASK(7, 0)
GENMASK            87 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RES_STAT_INUSE(x)                            (((x) << 12) & GENMASK(23, 12))
GENMASK            88 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RES_STAT_INUSE_M                             GENMASK(23, 12)
GENMASK            89 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RES_STAT_INUSE_X(x)                          (((x) & GENMASK(23, 12)) >> 12)
GENMASK            90 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RES_STAT_MAXUSE(x)                           ((x) & GENMASK(11, 0))
GENMASK            91 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_RES_STAT_MAXUSE_M                            GENMASK(11, 0)
GENMASK            93 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EVENTS_CORE_EV_FDC(x)                        (((x) << 2) & GENMASK(4, 2))
GENMASK            94 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EVENTS_CORE_EV_FDC_M                         GENMASK(4, 2)
GENMASK            95 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EVENTS_CORE_EV_FDC_X(x)                      (((x) & GENMASK(4, 2)) >> 2)
GENMASK            96 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EVENTS_CORE_EV_FRD(x)                        ((x) & GENMASK(1, 0))
GENMASK            97 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EVENTS_CORE_EV_FRD_M                         GENMASK(1, 0)
GENMASK           117 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_P_QUEUES(x)                   ((x) & GENMASK(7, 0))
GENMASK           118 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_P_QUEUES_M                    GENMASK(7, 0)
GENMASK           119 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x)           (((x) << 8) & GENMASK(9, 8))
GENMASK           120 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M            GENMASK(9, 8)
GENMASK           121 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x)         (((x) & GENMASK(9, 8)) >> 8)
GENMASK           122 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_STRICT_IPG(x)                 (((x) << 12) & GENMASK(13, 12))
GENMASK           123 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_STRICT_IPG_M                  GENMASK(13, 12)
GENMASK           124 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x)               (((x) & GENMASK(13, 12)) >> 12)
GENMASK           125 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x)               (((x) << 16) & GENMASK(31, 16))
GENMASK           126 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M                GENMASK(31, 16)
GENMASK           127 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x)             (((x) & GENMASK(31, 16)) >> 16)
GENMASK           131 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_CFG_CIR_RATE(x)                          (((x) << 6) & GENMASK(20, 6))
GENMASK           132 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_CFG_CIR_RATE_M                           GENMASK(20, 6)
GENMASK           133 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_CFG_CIR_RATE_X(x)                        (((x) & GENMASK(20, 6)) >> 6)
GENMASK           134 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_CFG_CIR_BURST(x)                         ((x) & GENMASK(5, 0))
GENMASK           135 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_CFG_CIR_BURST_M                          GENMASK(5, 0)
GENMASK           139 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_RATE(x)                          (((x) << 7) & GENMASK(21, 7))
GENMASK           140 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_RATE_M                           GENMASK(21, 7)
GENMASK           141 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_RATE_X(x)                        (((x) & GENMASK(21, 7)) >> 7)
GENMASK           142 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_BURST(x)                         (((x) << 1) & GENMASK(6, 1))
GENMASK           143 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_BURST_M                          GENMASK(6, 1)
GENMASK           144 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_EIR_CFG_EIR_BURST_X(x)                       (((x) & GENMASK(6, 1)) >> 1)
GENMASK           149 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_DWRR_CNT(x)                        (((x) << 6) & GENMASK(9, 6))
GENMASK           150 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_DWRR_CNT_M                         GENMASK(9, 6)
GENMASK           151 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_DWRR_CNT_X(x)                      (((x) & GENMASK(9, 6)) >> 6)
GENMASK           154 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_FRM_MODE(x)                        (((x) << 2) & GENMASK(3, 2))
GENMASK           155 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_FRM_MODE_M                         GENMASK(3, 2)
GENMASK           156 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CFG_SE_FRM_MODE_X(x)                      (((x) & GENMASK(3, 2)) >> 2)
GENMASK           165 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_IDX(x)                    (((x) << 17) & GENMASK(24, 17))
GENMASK           166 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_IDX_M                     GENMASK(24, 17)
GENMASK           167 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x)                  (((x) & GENMASK(24, 17)) >> 17)
GENMASK           168 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_IDX(x)                     (((x) << 9) & GENMASK(16, 9))
GENMASK           169 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_IDX_M                      GENMASK(16, 9)
GENMASK           170 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_IDX_X(x)                   (((x) & GENMASK(16, 9)) >> 9)
GENMASK           171 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_CON(x)                    (((x) << 5) & GENMASK(8, 5))
GENMASK           172 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_CON_M                     GENMASK(8, 5)
GENMASK           173 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x)                  (((x) & GENMASK(8, 5)) >> 5)
GENMASK           174 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_CNT(x)                     (((x) << 1) & GENMASK(4, 1))
GENMASK           175 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_CNT_M                      GENMASK(4, 1)
GENMASK           176 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_CONNECT_SE_INP_CNT_X(x)                   (((x) & GENMASK(4, 1)) >> 1)
GENMASK           181 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x)                  (((x) << 11) & GENMASK(13, 11))
GENMASK           182 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M                   GENMASK(13, 11)
GENMASK           183 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x)                (((x) & GENMASK(13, 11)) >> 11)
GENMASK           184 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x)                 (((x) << 7) & GENMASK(10, 7))
GENMASK           185 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M                  GENMASK(10, 7)
GENMASK           186 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x)               (((x) & GENMASK(10, 7)) >> 7)
GENMASK           187 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x)                 (((x) << 3) & GENMASK(6, 3))
GENMASK           188 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M                  GENMASK(6, 3)
GENMASK           189 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x)               (((x) & GENMASK(6, 3)) >> 3)
GENMASK           196 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_STATE_CIR_LVL(x)                         (((x) << 4) & GENMASK(25, 4))
GENMASK           197 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_STATE_CIR_LVL_M                          GENMASK(25, 4)
GENMASK           198 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_STATE_CIR_LVL_X(x)                       (((x) & GENMASK(25, 4)) >> 4)
GENMASK           199 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_STATE_SHP_TIME(x)                        ((x) & GENMASK(3, 0))
GENMASK           200 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_CIR_STATE_SHP_TIME_M                         GENMASK(3, 0)
GENMASK           206 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_STATE_SE_OUTP_LVL(x)                      (((x) << 1) & GENMASK(2, 1))
GENMASK           207 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_STATE_SE_OUTP_LVL_M                       GENMASK(2, 1)
GENMASK           208 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_SE_STATE_SE_OUTP_LVL_X(x)                    (((x) & GENMASK(2, 1)) >> 1)
GENMASK           212 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_FRM_ADJ(x)                     (((x) << 3) & GENMASK(7, 3))
GENMASK           213 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_FRM_ADJ_M                      GENMASK(7, 3)
GENMASK           214 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x)                   (((x) & GENMASK(7, 3)) >> 3)
GENMASK           222 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_LINK_SPEED(x)                     (((x) << 4) & GENMASK(5, 4))
GENMASK           223 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_LINK_SPEED_M                      GENMASK(5, 4)
GENMASK           224 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_LINK_SPEED_X(x)                   (((x) & GENMASK(5, 4)) >> 4)
GENMASK           225 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x)                (((x) << 8) & GENMASK(15, 8))
GENMASK           226 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M                 GENMASK(15, 8)
GENMASK           227 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x)              (((x) & GENMASK(15, 8)) >> 8)
GENMASK           228 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x)             (((x) << 16) & GENMASK(23, 16))
GENMASK           229 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M              GENMASK(23, 16)
GENMASK           230 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x)           (((x) & GENMASK(23, 16)) >> 16)
GENMASK           232 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x)               ((x) & GENMASK(7, 0))
GENMASK           233 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M                GENMASK(7, 0)
GENMASK           239 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x)         ((x) & GENMASK(15, 0))
GENMASK           240 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M          GENMASK(15, 0)
GENMASK           241 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x)               (((x) << 16) & GENMASK(31, 16))
GENMASK           242 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M                GENMASK(31, 16)
GENMASK           243 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x)             (((x) & GENMASK(31, 16)) >> 16)
GENMASK           245 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x)               ((x) & GENMASK(5, 0))
GENMASK           246 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M                GENMASK(5, 0)
GENMASK           247 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_CFG_REG_1_GATE_STATE(x)                  (((x) << 8) & GENMASK(15, 8))
GENMASK           248 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_CFG_REG_1_GATE_STATE_M                   GENMASK(15, 8)
GENMASK           249 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x)                (((x) & GENMASK(15, 8)) >> 8)
GENMASK           251 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x)      ((x) & GENMASK(15, 0))
GENMASK           252 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M       GENMASK(15, 0)
GENMASK           253 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x)            (((x) << 16) & GENMASK(31, 16))
GENMASK           254 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M             GENMASK(31, 16)
GENMASK           255 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x)          (((x) & GENMASK(31, 16)) >> 16)
GENMASK           257 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x)   ((x) & GENMASK(15, 0))
GENMASK           258 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M    GENMASK(15, 0)
GENMASK           259 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x)        (((x) << 16) & GENMASK(23, 16))
GENMASK           260 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M         GENMASK(23, 16)
GENMASK           261 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x)      (((x) & GENMASK(23, 16)) >> 16)
GENMASK           264 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x)            ((x) & GENMASK(5, 0))
GENMASK           265 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M             GENMASK(5, 0)
GENMASK           266 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x)               (((x) << 8) & GENMASK(15, 8))
GENMASK           267 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M                GENMASK(15, 8)
GENMASK           268 drivers/net/ethernet/mscc/ocelot_qsys.h #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x)             (((x) & GENMASK(15, 8)) >> 8)
GENMASK            13 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_TPID(x)                    (((x) << 16) & GENMASK(31, 16))
GENMASK            14 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_TPID_M                     GENMASK(31, 16)
GENMASK            15 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_TPID_X(x)                  (((x) & GENMASK(31, 16)) >> 16)
GENMASK            17 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_PCP(x)                     (((x) << 12) & GENMASK(14, 12))
GENMASK            18 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_PCP_M                      GENMASK(14, 12)
GENMASK            19 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_PCP_X(x)                   (((x) & GENMASK(14, 12)) >> 12)
GENMASK            20 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_VID(x)                     ((x) & GENMASK(11, 0))
GENMASK            21 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_VLAN_CFG_PORT_VID_M                      GENMASK(11, 0)
GENMASK            25 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_CFG(x)                            (((x) << 7) & GENMASK(8, 7))
GENMASK            26 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_CFG_M                             GENMASK(8, 7)
GENMASK            27 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_CFG_X(x)                          (((x) & GENMASK(8, 7)) >> 7)
GENMASK            28 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_TPID_CFG(x)                       (((x) << 5) & GENMASK(6, 5))
GENMASK            29 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_TPID_CFG_M                        GENMASK(6, 5)
GENMASK            30 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_TPID_CFG_X(x)                     (((x) & GENMASK(6, 5)) >> 5)
GENMASK            32 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_PCP_CFG(x)                        (((x) << 2) & GENMASK(3, 2))
GENMASK            33 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_PCP_CFG_M                         GENMASK(3, 2)
GENMASK            34 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_PCP_CFG_X(x)                      (((x) & GENMASK(3, 2)) >> 2)
GENMASK            35 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_DEI_CFG(x)                        ((x) & GENMASK(1, 0))
GENMASK            36 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_TAG_CFG_TAG_DEI_CFG_M                         GENMASK(1, 0)
GENMASK            41 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x)             (((x) << 3) & GENMASK(4, 3))
GENMASK            42 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M              GENMASK(4, 3)
GENMASK            43 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x)           (((x) & GENMASK(4, 3)) >> 3)
GENMASK            54 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x)            ((x) & GENMASK(2, 0))
GENMASK            55 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M             GENMASK(2, 0)
GENMASK            60 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_GP_CFG_UNUSED(x)                      (((x) << 3) & GENMASK(6, 3))
GENMASK            61 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_GP_CFG_UNUSED_M                       GENMASK(6, 3)
GENMASK            62 drivers/net/ethernet/mscc/ocelot_rew.h #define REW_PTP_CFG_GP_CFG_UNUSED_X(x)                    (((x) & GENMASK(6, 3)) >> 3)
GENMASK             9 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_CMD(x)      (((x) << 22) & GENMASK(24, 22))
GENMASK            10 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_CMD_M       GENMASK(24, 22)
GENMASK            11 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_CMD_X(x)    (((x) & GENMASK(24, 22)) >> 22)
GENMASK            15 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR(x)     (((x) << 3) & GENMASK(18, 3))
GENMASK            16 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_M      GENMASK(18, 3)
GENMASK            17 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x)   (((x) & GENMASK(18, 3)) >> 3)
GENMASK            22 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_MV_CFG_MV_NUM_POS(x)           (((x) << 16) & GENMASK(31, 16))
GENMASK            23 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_MV_CFG_MV_NUM_POS_M            GENMASK(31, 16)
GENMASK            24 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_MV_CFG_MV_NUM_POS_X(x)         (((x) & GENMASK(31, 16)) >> 16)
GENMASK            25 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_MV_CFG_MV_SIZE(x)              ((x) & GENMASK(15, 0))
GENMASK            26 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_CORE_MV_CFG_MV_SIZE_M               GENMASK(15, 0)
GENMASK            44 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CFG_TCAM_BIAS(x)               ((x) & GENMASK(5, 0))
GENMASK            45 drivers/net/ethernet/mscc/ocelot_s2.h #define S2_BIST_CFG_TCAM_BIAS_M                GENMASK(5, 0)
GENMASK            17 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_DATA_WO_TS(x)                       (((x) << 5) & GENMASK(6, 5))
GENMASK            18 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_DATA_WO_TS_M                        GENMASK(6, 5)
GENMASK            19 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_DATA_WO_TS_X(x)                     (((x) & GENMASK(6, 5)) >> 5)
GENMASK            20 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_INJ_HDR(x)                     (((x) << 3) & GENMASK(4, 3))
GENMASK            21 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_INJ_HDR_M                      GENMASK(4, 3)
GENMASK            22 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_INJ_HDR_X(x)                   (((x) & GENMASK(4, 3)) >> 3)
GENMASK            23 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_XTR_HDR(x)                     (((x) << 1) & GENMASK(2, 1))
GENMASK            24 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_XTR_HDR_M                      GENMASK(2, 1)
GENMASK            25 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PORT_MODE_INCL_XTR_HDR_X(x)                   (((x) & GENMASK(2, 1)) >> 1)
GENMASK            33 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_FRM_AGING_MAX_AGE(x)                          ((x) & GENMASK(19, 0))
GENMASK            34 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_FRM_AGING_MAX_AGE_M                           GENMASK(19, 0)
GENMASK            36 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x)                   (((x) << 10) & GENMASK(16, 10))
GENMASK            37 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M                    GENMASK(16, 10)
GENMASK            38 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x)                 (((x) & GENMASK(16, 10)) >> 10)
GENMASK            39 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_STAT_CFG_STAT_VIEW(x)                         ((x) & GENMASK(9, 0))
GENMASK            40 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_STAT_CFG_STAT_VIEW_M                          GENMASK(9, 0)
GENMASK            53 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x)              (((x) << 6) & GENMASK(21, 6))
GENMASK            54 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M               GENMASK(21, 6)
GENMASK            55 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x)            (((x) & GENMASK(21, 6)) >> 6)
GENMASK            56 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x)          ((x) & GENMASK(5, 0))
GENMASK            57 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M           GENMASK(5, 0)
GENMASK            61 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_START(x)                      (((x) << 10) & GENMASK(18, 10))
GENMASK            62 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_START_M                       GENMASK(18, 10)
GENMASK            63 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_START_X(x)                    (((x) & GENMASK(18, 10)) >> 10)
GENMASK            64 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_STOP(x)                       (((x) << 1) & GENMASK(9, 1))
GENMASK            65 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_STOP_M                        GENMASK(9, 1)
GENMASK            66 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_CFG_PAUSE_STOP_X(x)                     (((x) & GENMASK(9, 1)) >> 1)
GENMASK            69 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x)              (((x) << 9) & GENMASK(17, 9))
GENMASK            70 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M               GENMASK(17, 9)
GENMASK            71 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x)            (((x) & GENMASK(17, 9)) >> 9)
GENMASK            72 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x)               ((x) & GENMASK(8, 0))
GENMASK            73 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M                GENMASK(8, 0)
GENMASK            79 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x)                   (((x) << 26) & GENMASK(27, 26))
GENMASK            80 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M                    GENMASK(27, 26)
GENMASK            81 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x)                 (((x) & GENMASK(27, 26)) >> 26)
GENMASK            82 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x)                  (((x) << 20) & GENMASK(25, 20))
GENMASK            83 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M                   GENMASK(25, 20)
GENMASK            84 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x)                (((x) & GENMASK(25, 20)) >> 20)
GENMASK            88 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x)                   ((x) & GENMASK(15, 0))
GENMASK            89 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M                    GENMASK(15, 0)
GENMASK            91 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_RELCNT(x)                                (((x) << 16) & GENMASK(31, 16))
GENMASK            92 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_RELCNT_M                                 GENMASK(31, 16)
GENMASK            93 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_RELCNT_X(x)                              (((x) & GENMASK(31, 16)) >> 16)
GENMASK            94 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FREECNT(x)                               ((x) & GENMASK(15, 0))
GENMASK            95 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FREECNT_M                                GENMASK(15, 0)
GENMASK            97 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FAST_FREEVLD(x)                          (((x) << 4) & GENMASK(7, 4))
GENMASK            98 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FAST_FREEVLD_M                           GENMASK(7, 4)
GENMASK            99 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FAST_FREEVLD_X(x)                        (((x) & GENMASK(7, 4)) >> 4)
GENMASK           100 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FAST_RELVLD(x)                           ((x) & GENMASK(3, 0))
GENMASK           101 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_MMGT_FAST_RELVLD_M                            GENMASK(3, 0)
GENMASK           105 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_DIF_EV_DRX(x)                          (((x) << 6) & GENMASK(8, 6))
GENMASK           106 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_DIF_EV_DRX_M                           GENMASK(8, 6)
GENMASK           107 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_DIF_EV_DRX_X(x)                        (((x) & GENMASK(8, 6)) >> 6)
GENMASK           108 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_DIF_EV_DTX(x)                          ((x) & GENMASK(5, 0))
GENMASK           109 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_DIF_EV_DTX_M                           GENMASK(5, 0)
GENMASK           112 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_CORE_EV_ANA(x)                         ((x) & GENMASK(1, 0))
GENMASK           113 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_EVENTS_CORE_EV_ANA_M                          GENMASK(1, 0)
GENMASK           120 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_ID(x)                     (((x) << 21) & GENMASK(26, 21))
GENMASK           121 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_ID_M                      GENMASK(26, 21)
GENMASK           122 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_ID_X(x)                   (((x) & GENMASK(26, 21)) >> 21)
GENMASK           123 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x)                 (((x) << 16) & GENMASK(20, 16))
GENMASK           124 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M                  GENMASK(20, 16)
GENMASK           125 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x)               (((x) & GENMASK(20, 16)) >> 16)
GENMASK           126 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x)                 ((x) & GENMASK(15, 0))
GENMASK           127 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M                  GENMASK(15, 0)
GENMASK           129 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x)                    ((x) & GENMASK(29, 0))
GENMASK           130 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M                     GENMASK(29, 0)
GENMASK           135 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_CFG_PTP_STAMP_WID(x)                      (((x) << 2) & GENMASK(7, 2))
GENMASK           136 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_CFG_PTP_STAMP_WID_M                       GENMASK(7, 2)
GENMASK           137 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_CFG_PTP_STAMP_WID_X(x)                    (((x) & GENMASK(7, 2)) >> 2)
GENMASK           138 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x)                   ((x) & GENMASK(1, 0))
GENMASK           139 drivers/net/ethernet/mscc/ocelot_sys.h #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M                    GENMASK(1, 0)
GENMASK           392 drivers/net/ethernet/netronome/nfp/abm/ctrl.c 	abm->dscp_mask = GENMASK(7, 8 - order_base_2(abm->num_prios));
GENMASK            24 drivers/net/ethernet/netronome/nfp/abm/main.h #define NFP_ABM_PORTID_TYPE	GENMASK(23, 16)
GENMASK            25 drivers/net/ethernet/netronome/nfp/abm/main.h #define NFP_ABM_PORTID_ID	GENMASK(7, 0)
GENMASK           909 drivers/net/ethernet/netronome/nfp/bpf/jit.c 	mask = size < 4 ? GENMASK(size - 1, 0) : 0;
GENMASK          3628 drivers/net/ethernet/netronome/nfp/bpf/jit.c 	wrp_immed(nfp_prog, plen_reg(nfp_prog), GENMASK(13, 0));
GENMASK            71 drivers/net/ethernet/netronome/nfp/ccm.h #define NFP_NET_MBOX_TLV_TYPE		GENMASK(31, 16)
GENMASK            72 drivers/net/ethernet/netronome/nfp/ccm.h #define NFP_NET_MBOX_TLV_LEN		GENMASK(15, 0)
GENMASK            22 drivers/net/ethernet/netronome/nfp/crypto/fw.h #define NFP_NET_TLS_IPVER		GENMASK(15, 12)
GENMASK            23 drivers/net/ethernet/netronome/nfp/crypto/fw.h #define NFP_NET_TLS_VLAN		GENMASK(11, 0)
GENMASK            30 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_VLAN_PRIO	GENMASK(15, 13)
GENMASK            32 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_VLAN_VID	GENMASK(11, 0)
GENMASK            34 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_MPLS_LB		GENMASK(31, 12)
GENMASK            35 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_MASK_MPLS_TC		GENMASK(11, 9)
GENMASK            90 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_OUT_FLAGS_TYPE_IDX	GENMASK(2, 0)
GENMASK            92 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_PUSH_VLAN_PRIO		GENMASK(15, 13)
GENMASK            93 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_PUSH_VLAN_VID		GENMASK(11, 0)
GENMASK           102 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_IPV4_TUNNEL_TYPE		GENMASK(7, 4)
GENMASK           103 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FL_IPV4_PRE_TUN_INDEX	GENMASK(2, 0)
GENMASK           503 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_MAC_REPR_NBI		GENMASK(1, 0)
GENMASK           548 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_TYPE		GENMASK(31, 28)
GENMASK           549 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_SYS_ID		GENMASK(27, 24)
GENMASK           550 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_NFP_ID		GENMASK(23, 22)
GENMASK           551 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_PCI		GENMASK(15, 14)
GENMASK           552 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_VNIC_TYPE		GENMASK(13, 12)
GENMASK           553 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_VNIC		GENMASK(11, 6)
GENMASK           554 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_PCIE_Q		GENMASK(5, 0)
GENMASK           555 drivers/net/ethernet/netronome/nfp/flower/cmsg.h #define NFP_FLOWER_CMSG_PORT_PHYS_PORT_NUM	GENMASK(7, 0)
GENMASK            72 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_PKT_NUMBER_MASK	GENMASK(30, 0)
GENMASK            73 drivers/net/ethernet/netronome/nfp/flower/lag_conf.c #define NFP_FL_LAG_VERSION_MASK		GENMASK(22, 0)
GENMASK            24 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_STAT_ID_MU_NUM		GENMASK(31, 22)
GENMASK            25 drivers/net/ethernet/netronome/nfp/flower/main.h #define NFP_FL_STAT_ID_STAT		GENMASK(21, 0)
GENMASK           257 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define CMD_OVE_DATA	GENMASK(5, 3)
GENMASK           259 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define CMD_OV_LEN	GENMASK(12, 8)
GENMASK           286 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_TYPE	GENMASK(31, 24)
GENMASK           287 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_LM_IDX	GENMASK(23, 22)
GENMASK           290 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_LM_MOD	GENMASK(21, 20)
GENMASK           291 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NN_REG_VAL	GENMASK(7, 0)
GENMASK           401 drivers/net/ethernet/netronome/nfp/nfp_asm.h #define NFP_IND_ME_CTX_PTR_BASE_MASK	GENMASK(9, 0)
GENMASK           128 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_OFFSET_MASK	GENMASK(6, 0)
GENMASK           129 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_TX_MSS_MASK		GENMASK(13, 0)
GENMASK           234 drivers/net/ethernet/netronome/nfp/nfp_net.h #define PCIE_DESC_RX_META_LEN_MASK	GENMASK(6, 0)
GENMASK           290 drivers/net/ethernet/netronome/nfp/nfp_net.h #define NFP_NET_META_FIELD_MASK GENMASK(NFP_NET_META_FIELD_SIZE - 1, 0)
GENMASK            26 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c #define   NFP_PL_DEVICE_ID_MASK			GENMASK(7, 0)
GENMASK            27 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c #define   NFP_PL_DEVICE_PART_MASK		GENMASK(31, 16)
GENMASK            64 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_CODE_MAJOR		GENMASK(15, 12)
GENMASK            65 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NSP_CODE_MINOR		GENMASK(11, 0)
GENMASK            67 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NFP_FW_LOAD_RET_MAJOR	GENMASK(15, 8)
GENMASK            68 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NFP_FW_LOAD_RET_MINOR	GENMASK(23, 16)
GENMASK            70 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NFP_HWINFO_LOOKUP_SIZE	GENMASK(11, 0)
GENMASK            72 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c #define NFP_VERSIONS_SIZE	GENMASK(11, 0)
GENMASK            42 drivers/net/ethernet/qualcomm/emac/emac-mac.h #define BITS_GET(val, lo, hi) ((le32_to_cpu(val) & GENMASK((hi), (lo))) >> lo)
GENMASK            44 drivers/net/ethernet/qualcomm/emac/emac-mac.h 	val = cpu_to_le32((le32_to_cpu(val) & (~GENMASK((hi), (lo)))) |	\
GENMASK            45 drivers/net/ethernet/qualcomm/emac/emac-mac.h 		(((new_val) << (lo)) & GENMASK((hi), (lo))))
GENMASK          6181 drivers/net/ethernet/realtek/r8169_main.c 			pkt_size = status & GENMASK(13, 0);
GENMASK           426 drivers/net/ethernet/renesas/ravb.h 	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
GENMASK           471 drivers/net/ethernet/renesas/ravb.h 	RIS0_RESERVED	= GENMASK(31, 18),
GENMASK           528 drivers/net/ethernet/renesas/ravb.h 	RIS2_RESERVED	= GENMASK(30, 18),
GENMASK           545 drivers/net/ethernet/renesas/ravb.h 	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
GENMASK           619 drivers/net/ethernet/renesas/ravb.h 	GIS_RESERVED	= GENMASK(15, 10),
GENMASK           119 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXCR_MPSIZ_MASK	GENMASK(10, 0)
GENMASK           129 drivers/net/ethernet/socionext/sni_ave.c #define AVE_DESCC_STATUS_MASK	GENMASK(31, 16)
GENMASK           135 drivers/net/ethernet/socionext/sni_ave.c #define AVE_TXDC_SIZE		GENMASK(27, 16)	/* Size of Tx descriptor */
GENMASK           136 drivers/net/ethernet/socionext/sni_ave.c #define AVE_TXDC_ADDR		GENMASK(11, 0)	/* Start address */
GENMASK           140 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXDC0_SIZE		GENMASK(30, 16)	/* Size of Rx descriptor */
GENMASK           141 drivers/net/ethernet/socionext/sni_ave.c #define AVE_RXDC0_ADDR		GENMASK(14, 0)	/* Start address */
GENMASK           146 drivers/net/ethernet/socionext/sni_ave.c #define AVE_IIRQC_BSCK		GENMASK(15, 0)	/* Interval count unit */
GENMASK           158 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_PKTLEN_TX_MASK	GENMASK(15, 0)
GENMASK           162 drivers/net/ethernet/socionext/sni_ave.c #define AVE_STS_PKTLEN_RX_MASK	GENMASK(10, 0)
GENMASK           165 drivers/net/ethernet/socionext/sni_ave.c #define AVE_PFMBYTE_MASK0	(GENMASK(31, 8) | GENMASK(5, 0))
GENMASK           166 drivers/net/ethernet/socionext/sni_ave.c #define AVE_PFMBYTE_MASK1	GENMASK(25, 0)
GENMASK           167 drivers/net/ethernet/socionext/sni_ave.c #define AVE_PFMBIT_MASK		GENMASK(15, 0)
GENMASK           388 drivers/net/ethernet/socionext/sni_ave.c 	major = (vr & GENMASK(15, 8)) >> 8;
GENMASK           389 drivers/net/ethernet/socionext/sni_ave.c 	minor = (vr & GENMASK(7, 0));
GENMASK           516 drivers/net/ethernet/socionext/sni_ave.c 	return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0);
GENMASK          1028 drivers/net/ethernet/socionext/sni_ave.c 	writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0,
GENMASK            24 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			GENMASK(1, 0)
GENMASK            45 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_PARTNER_SPEED_MASK			GENMASK(11, 10)
GENMASK            52 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c #define TSE_PCS_SGMII_SPEED_MASK			GENMASK(3, 2)
GENMASK            34 drivers/net/ethernet/stmicro/stmmac/descs.h #define	RDES0_FRAME_LEN_MASK	GENMASK(29, 16)
GENMASK            39 drivers/net/ethernet/stmicro/stmmac/descs.h #define	RDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
GENMASK            40 drivers/net/ethernet/stmicro/stmmac/descs.h #define	RDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
GENMASK            52 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
GENMASK            55 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
GENMASK            64 drivers/net/ethernet/stmicro/stmmac/descs.h #define	TDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
GENMASK            78 drivers/net/ethernet/stmicro/stmmac/descs.h #define	TDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)
GENMASK            79 drivers/net/ethernet/stmicro/stmmac/descs.h #define	TDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)
GENMASK            86 drivers/net/ethernet/stmicro/stmmac/descs.h #define	TDES1_CHECKSUM_INSERTION_MASK	GENMASK(28, 27)
GENMASK            97 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ETDES0_COLLISION_COUNT_MASK	GENMASK(6, 3)
GENMASK           111 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ETDES0_CHECKSUM_INSERTION_MASK	GENMASK(23, 22)
GENMASK           121 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ETDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)
GENMASK           122 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ETDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)
GENMASK           126 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES4_IP_PAYLOAD_TYPE_MASK	GENMASK(6, 2)
GENMASK           132 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES4_MSG_TYPE_MASK		GENMASK(11, 8)
GENMASK           138 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES4_VLAN_TAG_PRI_VAL_MASK	GENMASK(20, 18)
GENMASK           141 drivers/net/ethernet/stmicro/stmmac/descs.h #define	ERDES4_L3_L4_FILT_NO_MATCH_MASK	GENMASK(27, 26)
GENMASK            30 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_GTXC_STAGES	GENMASK(4, 0)
GENMASK            33 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_TXC_STAGES	GENMASK(18, 14)
GENMASK            36 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c #define ETH_DLY_RXC_STAGES	GENMASK(11, 7)
GENMASK            27 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
GENMASK            33 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
GENMASK            36 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c #define PRG_ETH0_TXDLY_MASK		GENMASK(6, 5)
GENMASK            25 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_GPIO_CFG_RX_INT		GENMASK(21, 20)
GENMASK            26 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_GPIO_CFG_TX_INT		GENMASK(19, 17)
GENMASK            27 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_MAX_SPD_PRG_9		GENMASK(16, 8)
GENMASK            28 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_MAX_SPD_PRG_2		GENMASK(7, 6)
GENMASK            29 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG_INTF_SEL			GENMASK(5, 4)
GENMASK            38 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_MCLK_FREQ		GENMASK(26, 24)
GENMASK            39 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG_CDR_SELEXT		GENMASK(23, 20)
GENMASK            45 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CDR_FINE_PHASE			GENMASK(3, 2)
GENMASK            49 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	GENMASK(26, 21)
GENMASK            50 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	GENMASK(29, 27)
GENMASK            52 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DDR_CONFIG_PRG_RCLK_DLY		GENMASK(8, 0)
GENMASK            56 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC		GENMASK(17, 10)
GENMASK            57 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	GENMASK(3, 2)
GENMASK            65 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c #define RGMII_CONFIG2_RSVD_CONFIG15		GENMASK(31, 17)
GENMASK           351 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      BIT(12) | GENMASK(9, 8),
GENMASK           418 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 		rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
GENMASK            73 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STIH4XX_RETIME_SRC_MASK			GENMASK(8, 6)
GENMASK            95 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define STID127_RETIME_SRC_MASK			GENMASK(7, 6)
GENMASK            99 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define ENMII_MASK	GENMASK(5, 5)
GENMASK           101 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define EN_MASK		GENMASK(1, 1)
GENMASK           111 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c #define MII_PHY_SEL_MASK	GENMASK(4, 2)
GENMASK            26 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c #define SYSCFG_MP1_ETH_MASK		GENMASK(23, 16)
GENMASK           195 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_RX_TH_MASK		GENMASK(5, 4)
GENMASK           206 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_TX_TH_MASK		GENMASK(10, 8)
GENMASK           260 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define SYSCON_ETCS_MASK		GENMASK(1, 0)
GENMASK          1056 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 	mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
GENMASK          1064 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 	mac->mii.reg_mask = GENMASK(8, 4);
GENMASK          1066 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 	mac->mii.addr_mask = GENMASK(16, 12);
GENMASK          1068 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c 	mac->mii.clk_csr_mask = GENMASK(22, 20);
GENMASK            90 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_RGSMIIIS_SPEED		GENMASK(2, 1)
GENMASK           161 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TRCSTS_MASK	GENMASK(21, 20)
GENMASK           169 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_TFCSTS_MASK	GENMASK(18, 17)
GENMASK           177 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_RXFSTS_MASK	GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
GENMASK           183 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_RRCSTS_MASK	GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
GENMASK           191 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
GENMASK           561 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c 	mac->mii.clk_csr_mask = GENMASK(5, 2);
GENMASK           198 drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c 	mac->mii.clk_csr_mask = GENMASK(5, 2);
GENMASK            48 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
GENMASK            50 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
GENMASK            52 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
GENMASK            54 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
GENMASK            56 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
GENMASK            79 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_VID			GENMASK(15, 0)
GENMASK            82 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_VLAN_VLC			GENMASK(17, 16)
GENMASK            86 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
GENMASK            94 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
GENMASK            98 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
GENMASK           157 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
GENMASK           164 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
GENMASK           170 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_CONFIG_SARC		GENMASK(30, 28)
GENMASK           205 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_HASH_TB_SZ		GENMASK(25, 24)
GENMASK           208 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
GENMASK           209 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
GENMASK           212 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_PPSOUTNUM		GENMASK(26, 24)
GENMASK           213 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
GENMASK           214 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
GENMASK           215 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
GENMASK           216 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
GENMASK           219 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
GENMASK           220 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
GENMASK           221 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
GENMASK           226 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_HI_DCS			GENMASK(18, 16)
GENMASK           233 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)
GENMASK           247 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_RXQ_DMA_Q04MDMACH_MASK	GENMASK(3, 0)
GENMASK           249 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_RXQ_DMA_QXMDMACH_MASK(x)	GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
GENMASK           264 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_TXQEN_MASK		GENMASK(3, 2)
GENMASK           269 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
GENMASK           284 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_RQS_MASK		GENMASK(29, 20)
GENMASK           287 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_RFD_MASK		GENMASK(19, 14)
GENMASK           290 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_OP_MODE_RFA_MASK		GENMASK(13, 8)
GENMASK           317 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)
GENMASK           325 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)
GENMASK           333 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)
GENMASK           341 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)
GENMASK           349 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
GENMASK           358 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
GENMASK           364 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
GENMASK           390 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
GENMASK           399 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
GENMASK           405 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
GENMASK           418 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)
GENMASK           938 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 	mac->mii.addr_mask = GENMASK(25, 21);
GENMASK           940 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 	mac->mii.reg_mask = GENMASK(20, 16);
GENMASK           942 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 	mac->mii.clk_csr_mask = GENMASK(11, 8);
GENMASK            19 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_BUFFER1_SIZE_MASK		GENMASK(13, 0)
GENMASK            20 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_VLAN_TAG_MASK		GENMASK(15, 14)
GENMASK            22 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_BUFFER2_SIZE_MASK		GENMASK(29, 16)
GENMASK            24 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_IVTIR_MASK		GENMASK(19, 18)
GENMASK            28 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES2_IVT_MASK			GENMASK(31, 16)
GENMASK            33 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_PACKET_SIZE_MASK		GENMASK(14, 0)
GENMASK            34 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_VLAN_TAG			GENMASK(15, 0)
GENMASK            36 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_CHECKSUM_INSERTION_MASK	GENMASK(17, 16)
GENMASK            38 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_TCP_PKT_PAYLOAD_MASK	GENMASK(17, 0)
GENMASK            41 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_SLOT_NUMBER_MASK		GENMASK(22, 19)
GENMASK            42 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_SA_INSERT_CTRL_MASK	GENMASK(25, 23)
GENMASK            44 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_CRC_PAD_CTRL_MASK		GENMASK(27, 26)
GENMASK            51 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define TDES3_COLLISION_COUNT_MASK	GENMASK(7, 4)
GENMASK            83 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES0_VLAN_TAG_MASK		GENMASK(15, 0)
GENMASK            86 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IP_PAYLOAD_TYPE_MASK	GENMASK(2, 0)
GENMASK            92 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_PTP_MSG_TYPE_MASK		GENMASK(11, 8)
GENMASK            98 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES1_IP_TYPE1_CSUM_MASK	GENMASK(31, 16)
GENMASK           101 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_L3_L4_HEADER_SIZE_MASK	GENMASK(9, 0)
GENMASK           106 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_MAC_ADDR_MATCH_MASK	GENMASK(26, 19)
GENMASK           107 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_HASH_VALUE_MATCH_MASK	GENMASK(26, 19)
GENMASK           110 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES2_L3_L4_FILT_NB_MATCH_MASK	GENMASK(27, 26)
GENMASK           114 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_PACKET_SIZE_MASK		GENMASK(14, 0)
GENMASK           116 drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h #define RDES3_PACKET_LEN_TYPE_MASK	GENMASK(18, 16)
GENMASK            56 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_WR_OSR_LMT		GENMASK(27, 24)
GENMASK            58 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_AXI_RD_OSR_LMT		GENMASK(19, 16)
GENMASK           110 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CONTROL_MSS_MASK		GENMASK(13, 0)
GENMASK           119 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_RBSZ_MASK			GENMASK(14, 1)
GENMASK           123 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_REB		GENMASK(21, 19)
GENMASK           125 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN_STATUS_TEB		GENMASK(18, 16)
GENMASK           179 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN0_DBG_STAT_TPS		GENMASK(15, 12)
GENMASK           181 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h #define DMA_CHAN0_DBG_STAT_RPS		GENMASK(11, 8)
GENMASK            17 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define PPSx_MASK(x)			GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
GENMASK            20 drivers/net/ethernet/stmicro/stmmac/dwmac5.h 	GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
GENMASK            23 drivers/net/ethernet/stmicro/stmmac/dwmac5.h 	GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
GENMASK            29 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define TTSL0				GENMASK(30, 0)
GENMASK            35 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define NPE				GENMASK(23, 16)
GENMASK            36 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define NVE				GENMASK(7, 0)
GENMASK            39 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define RXPEIEC				GENMASK(22, 21)
GENMASK            42 drivers/net/ethernet/stmicro/stmmac/dwmac5.h #define ADDR				GENMASK(15, 0)
GENMASK            36 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_WR_OSR_LMT	GENMASK(23, 20)
GENMASK            39 drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h #define DMA_AXI_RD_OSR_LMT	GENMASK(19, 16)
GENMASK            18 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_SS_MASK		GENMASK(31, 29)
GENMASK            26 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_SARC		GENMASK(22, 20)
GENMASK            33 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_GPSL		GENMASK(29, 16)
GENMASK            35 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_CONFIG_HDSMS		GENMASK(14, 12)
GENMASK            66 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_VID			GENMASK(15, 0)
GENMASK            71 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_VLAN_VLC			GENMASK(17, 16)
GENMASK            74 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RXQEN(x)			GENMASK((x) * 2 + 1, (x) * 2)
GENMASK            78 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PSRQ(x)			GENMASK((x) * 8 + 7, (x) * 8)
GENMASK            89 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PT			GENMASK(31, 16)
GENMASK           124 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_L3L4FNUM		GENMASK(30, 27)
GENMASK           125 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_HASHTBLSZ		GENMASK(25, 24)
GENMASK           129 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_ADDR64		GENMASK(15, 14)
GENMASK           130 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TXFIFOSIZE		GENMASK(10, 6)
GENMASK           131 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RXFIFOSIZE		GENMASK(4, 0)
GENMASK           133 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_PPSOUTNUM		GENMASK(26, 24)
GENMASK           134 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TXCHCNT		GENMASK(21, 18)
GENMASK           135 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RXCHCNT		GENMASK(15, 12)
GENMASK           136 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_TXQCNT		GENMASK(9, 6)
GENMASK           137 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_RXQCNT		GENMASK(3, 0)
GENMASK           139 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_ASP		GENMASK(15, 14)
GENMASK           141 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_FRPES		GENMASK(12, 11)
GENMASK           142 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_HWFEAT_FRPPB		GENMASK(10, 9)
GENMASK           154 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_DCS			GENMASK(19, 16)
GENMASK           158 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_IDDR			GENMASK(15, 8)
GENMASK           170 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3HDBM0			GENMASK(15, 11)
GENMASK           171 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L3HSBM0			GENMASK(10, 6)
GENMASK           178 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4DP0			GENMASK(31, 16)
GENMASK           180 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_L4SP0			GENMASK(15, 0)
GENMASK           200 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXTSSTSLO			GENMASK(30, 0)
GENMASK           206 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 	GENMASK(XGMAC_PPS_MAXIDX(x), XGMAC_PPS_MINIDX(x))
GENMASK           208 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 	GENMASK(XGMAC_PPS_MAXIDX(x) - 1, XGMAC_PPS_MAXIDX(x) - 2) & \
GENMASK           211 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 	GENMASK(XGMAC_PPS_MINIDX(x) + 3, XGMAC_PPS_MINIDX(x)) & \
GENMASK           225 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_ETSALG			GENMASK(6, 5)
GENMASK           233 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_QxMDMACH(x)		GENMASK((x) * 8 + 7, (x) * 8)
GENMASK           238 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_PSTC(x)			GENMASK((x) * 8 + 7, (x) * 8)
GENMASK           242 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_NPE			GENMASK(23, 16)
GENMASK           243 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_NVE			GENMASK(7, 0)
GENMASK           247 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_ADDR			GENMASK(9, 0)
GENMASK           260 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TQS			GENMASK(25, 16)
GENMASK           262 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_Q2TCMAP			GENMASK(10, 8)
GENMASK           264 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TTC			GENMASK(6, 4)
GENMASK           266 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TXQEN			GENMASK(3, 2)
GENMASK           275 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TSA			GENMASK(1, 0)
GENMASK           280 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RQS			GENMASK(25, 16)
GENMASK           284 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RTC			GENMASK(1, 0)
GENMASK           287 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RFD			GENMASK(31, 17)
GENMASK           289 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RFA			GENMASK(15, 1)
GENMASK           303 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_WR_OSR_LMT		GENMASK(29, 24)
GENMASK           305 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RD_OSR_LMT		GENMASK(21, 16)
GENMASK           311 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_BLEN			GENMASK(7, 1)
GENMASK           321 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDPS			GENMASK(29, 0)
GENMASK           323 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDPS			GENMASK(29, 0)
GENMASK           338 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TxPBL			GENMASK(21, 16)
GENMASK           344 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RxPBL			GENMASK(21, 16)
GENMASK           346 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RBSZ			GENMASK(14, 1)
GENMASK           367 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RWT			GENMASK(7, 0)
GENMASK           380 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_IVT			GENMASK(31, 16)
GENMASK           384 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_B2L			GENMASK(29, 16)
GENMASK           386 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_VTIR		GENMASK(15, 14)
GENMASK           388 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES2_B1L			GENMASK(13, 0)
GENMASK           393 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_CPC			GENMASK(27, 26)
GENMASK           396 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_SAIC		GENMASK(25, 23)
GENMASK           398 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_THL			GENMASK(22, 19)
GENMASK           400 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_IVTIR		GENMASK(19, 18)
GENMASK           404 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_CIC			GENMASK(17, 16)
GENMASK           406 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_TPL			GENMASK(17, 0)
GENMASK           408 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_VT			GENMASK(15, 0)
GENMASK           409 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_TDES3_FL			GENMASK(14, 0)
GENMASK           410 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES2_HL			GENMASK(9, 0)
GENMASK           417 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_L34T		GENMASK(23, 20)
GENMASK           424 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h #define XGMAC_RDES3_PL			GENMASK(13, 0)
GENMASK          1420 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 	mac->mii.addr_mask = GENMASK(20, 16);
GENMASK          1422 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 	mac->mii.reg_mask = GENMASK(15, 0);
GENMASK          1424 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 	mac->mii.clk_csr_mask = GENMASK(21, 19);
GENMASK            21 drivers/net/ethernet/stmicro/stmmac/hwif.c 			(unsigned int)(reg & GENMASK(15, 8)) >> 8,
GENMASK            22 drivers/net/ethernet/stmicro/stmmac/hwif.c 			(unsigned int)(reg & GENMASK(7, 0)));
GENMASK            23 drivers/net/ethernet/stmicro/stmmac/hwif.c 	return reg & GENMASK(7, 0);
GENMASK           348 drivers/net/ethernet/stmicro/stmmac/mmc_core.c 	if (tmp > GENMASK(31, 0))
GENMASK            27 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c #define MII_DATA_MASK GENMASK(15, 0)
GENMASK            43 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c #define MII_XGMAC_C22P_MASK		GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
GENMASK           105 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c 	return readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
GENMASK            41 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_ANE_PSE		GENMASK(8, 7)
GENMASK            43 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h #define GMAC_ANE_RFE		GENMASK(13, 12)
GENMASK           137 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 			GENMASK(31, rem * 8);
GENMASK           139 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 			GENMASK(31, rem * 8);
GENMASK           144 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 			GENMASK(rem * 8 - 1, 0);
GENMASK           146 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 			GENMASK(rem * 8 - 1, 0);
GENMASK           344 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 	priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0);
GENMASK           347 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 	priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0);
GENMASK           350 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 	priv->plat->tx_queues_cfg[queue].high_credit = value & GENMASK(31, 0);
GENMASK           353 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 	priv->plat->tx_queues_cfg[queue].low_credit = value & GENMASK(31, 0);
GENMASK           103 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
GENMASK           110 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);		\
GENMASK           118 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
GENMASK           119 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
GENMASK           127 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	_val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);		\
GENMASK           128 drivers/net/ethernet/synopsys/dwc-xlgmac.h 	_var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;		\
GENMASK           124 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK		GENMASK(2, 0)
GENMASK           127 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK	GENMASK(1, 0)
GENMASK           107 drivers/net/fjes/fjes_regs.h 	REG_ICTL_MASK_ALL             = GENMASK(20, 16),
GENMASK           112 drivers/net/fjes/fjes_regs.h 	REG_IS_MASK_EPID	= GENMASK(15, 0),
GENMASK            43 drivers/net/phy/adin.c #define   ADIN1300_DOWNSPEED_RETRIES_MSK	GENMASK(12, 10)
GENMASK            76 drivers/net/phy/adin.c #define   ADIN1300_GE_RGMII_RX_MSK		GENMASK(8, 6)
GENMASK            79 drivers/net/phy/adin.c #define   ADIN1300_GE_RGMII_GTX_MSK		GENMASK(5, 3)
GENMASK            94 drivers/net/phy/adin.c #define   ADIN1300_GE_RMII_FIFO_DEPTH_MSK	GENMASK(6, 4)
GENMASK            27 drivers/net/phy/aquantia_main.c #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
GENMASK            38 drivers/net/phy/aquantia_main.c #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
GENMASK            42 drivers/net/phy/aquantia_main.c #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK	GENMASK(3, 1)
GENMASK            67 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT4_FW_MAJOR		GENMASK(15, 8)
GENMASK            68 drivers/net/phy/aquantia_main.c #define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
GENMASK            87 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
GENMASK            88 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
GENMASK            91 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
GENMASK            92 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
GENMASK            95 drivers/net/phy/aquantia_main.c #define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
GENMASK           175 drivers/net/phy/aquantia_main.c 	ret = val & GENMASK(len_l - 1, 0);
GENMASK           181 drivers/net/phy/aquantia_main.c 		ret += (val & GENMASK(len_h - 1, 0)) << 16;
GENMASK            73 drivers/net/phy/dp83867.c #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK	GENMASK(6, 4)
GENMASK            75 drivers/net/phy/dp83867.c #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK	GENMASK(2, 0)
GENMASK            83 drivers/net/phy/dp83867.c #define DP83867_PHYCR_FIFO_DEPTH_MASK		GENMASK(15, 14)
GENMASK            96 drivers/net/phy/marvell.c #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK	GENMASK(11, 10)
GENMASK            21 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_CTRL_OP		GENMASK(27, 26)
GENMASK            24 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_CTRL_PHYAD	GENMASK(25, 21)
GENMASK            25 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_CTRL_REGAD	GENMASK(20, 16)
GENMASK            26 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_CTRL_MIIWDATA	GENMASK(15, 0)
GENMASK            29 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_DATA_MDC_THRES	GENMASK(31, 24)
GENMASK            31 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_DATA_MDIO_LATCH	GENMASK(22, 20)
GENMASK            33 drivers/net/phy/mdio-aspeed.c #define   ASPEED_MDIO_DATA_MIIRDATA	GENMASK(15, 0)
GENMASK            23 drivers/net/phy/mdio-mux-meson-g12a.c #define  PLL_CTL0_N		GENMASK(14, 10)
GENMASK            24 drivers/net/phy/mdio-mux-meson-g12a.c #define  PLL_CTL0_M		GENMASK(8, 0)
GENMASK            38 drivers/net/phy/mdio-mux-meson-g12a.c #define  PHY_CNTL1_ST_MODE	GENMASK(2, 0)
GENMASK            39 drivers/net/phy/mdio-mux-meson-g12a.c #define  PHY_CNTL1_ST_PHYADD	GENMASK(7, 3)
GENMASK            41 drivers/net/phy/mdio-mux-meson-g12a.c #define  PHY_CNTL1_MII_MODE	GENMASK(15, 14)
GENMASK            20 drivers/net/phy/meson-gxl.c #define  TSTCNTL_REG_BANK_SEL	GENMASK(12, 11)
GENMASK            22 drivers/net/phy/meson-gxl.c #define  TSTCNTL_READ_ADDRESS	GENMASK(9, 5)
GENMASK            23 drivers/net/phy/meson-gxl.c #define  TSTCNTL_WRITE_ADDRESS	GENMASK(4, 0)
GENMASK            46 drivers/net/phy/mscc.c #define ERR_CNT_MASK			  GENMASK(7, 0)
GENMASK            85 drivers/net/phy/mscc.c #define LED_MODE_SEL_MASK(x)		  (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
GENMASK           140 drivers/net/phy/mscc.c #define VALID_CRC_CNT_CRC_MASK		  GENMASK(13, 0)
GENMASK           314 drivers/net/phy/mscc.c #define MSCC_DEV_REV_MASK			GENMASK(3, 0)
GENMASK           891 drivers/net/phy/mscc.c 	__phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
GENMASK          1010 drivers/net/phy/mscc.c 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
GENMASK            21 drivers/net/phy/nxp-tja11xx.c #define MII_ECTRL_POWER_MODE_MASK	GENMASK(14, 11)
GENMASK            31 drivers/net/phy/nxp-tja11xx.c #define MII_CFG1_LED_MODE_MASK		GENMASK(5, 4)
GENMASK            36 drivers/net/phy/nxp-tja11xx.c #define MII_CFG2_SLEEP_REQUEST_TO	GENMASK(1, 0)
GENMASK            65 drivers/net/phy/nxp-tja11xx.c 	{ "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
GENMASK            69 drivers/net/phy/nxp-tja11xx.c 	{ "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
GENMASK            70 drivers/net/phy/nxp-tja11xx.c 	{ "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
GENMASK            17 drivers/net/phy/realtek.c #define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
GENMASK            45 drivers/net/thunderbolt.c #define TBNET_L0_PORT_NUM(route) ((route) & GENMASK(5, 0))
GENMASK            88 drivers/net/thunderbolt.c #define TBIP_HDR_LENGTH_MASK		GENMASK(5, 0)
GENMASK            89 drivers/net/thunderbolt.c #define TBIP_HDR_SN_MASK		GENMASK(28, 27)
GENMASK            32 drivers/net/wireless/ath/ath10k/ce.h #define CE_DESC_ADDR_HI_MASK		GENMASK(4, 0)
GENMASK            41 drivers/net/wireless/ath/ath10k/ce.h #define CE_DDR_RRI_MASK			GENMASK(15, 0)
GENMASK           372 drivers/net/wireless/ath/ath10k/ce.h #define CE_INTERRUPT_SUMMARY		(GENMASK(CE_COUNT_MAX - 1, 0))
GENMASK           318 drivers/net/wireless/ath/ath10k/htt.h #define HTT_STATS_BIT_MASK GENMASK(16, 0)
GENMASK           548 drivers/net/wireless/ath/ath10k/htt.h #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK	GENMASK(7, 0)
GENMASK           988 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK	GENMASK(15, 0)
GENMASK           989 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_PPDU_DUR_INFO0_TID_MASK		GENMASK(20, 16)
GENMASK           996 drivers/net/wireless/ath/ath10k/htt.h #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK	GENMASK(7, 0)
GENMASK           213 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(17, 17),
GENMASK           219 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(18, 18),
GENMASK           225 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK           236 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(0, 0),
GENMASK           267 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(31, 16),
GENMASK           273 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK           286 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(31, 16),
GENMASK           292 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK           345 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(16, 16),
GENMASK           351 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(17, 17),
GENMASK           357 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK           376 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(3, 3),
GENMASK           381 drivers/net/wireless/ath/ath10k/hw.c 	.mask		= GENMASK(0, 0),
GENMASK           389 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(0, 0),
GENMASK           421 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(31, 16),
GENMASK           427 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK           440 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(31, 16),
GENMASK           446 drivers/net/wireless/ath/ath10k/hw.c 	.mask	= GENMASK(15, 0),
GENMASK          1196 drivers/net/wireless/ath/ath10k/hw.h #define CPU_ADDR_MSB_REGION_MASK	GENMASK(23, 20)
GENMASK            89 drivers/net/wireless/ath/ath10k/sdio.c 	       FIELD_PREP(GENMASK(25, 9), address) |
GENMASK            91 drivers/net/wireless/ath/ath10k/sdio.c 	       FIELD_PREP(GENMASK(7, 0), val);
GENMASK            13 drivers/net/wireless/ath/ath10k/sdio.h #define QCA_MANUFACTURER_ID_BASE                GENMASK(11, 8)
GENMASK          1927 drivers/net/wireless/ath/ath10k/wmi-tlv.h #define WMI_TLV_PEER_RX_DURATION_HIGH_MASK	GENMASK(30, 0)
GENMASK            61 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CTRL_XTYPE_SHIFT)
GENMASK            66 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT)
GENMASK            71 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CTRL_PRIO_SHIFT)
GENMASK            76 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CTRL_BDT_IDX_MASK GENMASK(19, WCN36xx_DXE_CTRL_BDT_IDX_SHIFT)
GENMASK           180 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)
GENMASK           185 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)
GENMASK           190 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)
GENMASK           195 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT)
GENMASK           200 drivers/net/wireless/ath/wcn36xx/dxe.h #define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)
GENMASK            12 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_SD_LEN1		GENMASK(13, 0)
GENMASK            15 drivers/net/wireless/mediatek/mt76/dma.h #define MT_DMA_CTL_SD_LEN0		GENMASK(29, 16)
GENMASK           865 drivers/net/wireless/mediatek/mt76/mac80211.c 		if ((sband->bitrates[i].hw_value & GENMASK(7, 0)) == idx)
GENMASK           186 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_WCID_TX_INFO_RATE		GENMASK(15, 0)
GENMASK           187 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_WCID_TX_INFO_NSS		GENMASK(17, 16)
GENMASK           188 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_WCID_TX_INFO_TXPWR_ADJ	GENMASK(25, 18)
GENMASK           255 drivers/net/wireless/mediatek/mt76/mt76.h #define MT_PACKET_ID_MASK		GENMASK(6, 0)
GENMASK            90 drivers/net/wireless/mediatek/mt76/mt7603/beacon.c 	mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
GENMASK           192 drivers/net/wireless/mediatek/mt76/mt7603/init.c 	mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
GENMASK           460 drivers/net/wireless/mediatek/mt76/mt7603/init.c 	val &= GENMASK(5, 0);
GENMASK           483 drivers/net/wireless/mediatek/mt76/mt7603/init.c 		target_power = -(target_power & GENMASK(5, 0));
GENMASK            15 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	ret |= GENMASK(3, 0) * !!(mask & BIT(0));
GENMASK            16 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	ret |= GENMASK(8, 5) * !!(mask & BIT(1));
GENMASK            17 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	ret |= GENMASK(13, 10) * !!(mask & BIT(2));
GENMASK            18 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	ret |= GENMASK(19, 16) * !!(mask & BIT(3));
GENMASK           139 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
GENMASK           144 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	mt76_start_tx_ac(dev, GENMASK(3, 0));
GENMASK           293 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
GENMASK           297 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 	mt76_start_tx_ac(dev, GENMASK(3, 0));
GENMASK           898 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 		txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
GENMASK          1059 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 		final_rate &= GENMASK(5, 0);
GENMASK          1067 drivers/net/wireless/mediatek/mt76/mt7603/mac.c 		final_rate &= GENMASK(5, 0);
GENMASK             6 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_LENGTH			GENMASK(15, 0)
GENMASK             7 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_PKT_TYPE		GENMASK(31, 29)
GENMASK             9 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
GENMASK            27 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
GENMASK            28 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_PAYLOAD_FORMAT	GENMASK(25, 24)
GENMASK            31 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_MAC_HDR_LEN	GENMASK(21, 16)
GENMASK            32 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_CH_FREQ		GENMASK(15, 8)
GENMASK            33 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD1_NORMAL_KEY_ID		GENMASK(7, 6)
GENMASK            57 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_SEC_MODE		GENMASK(15, 12)
GENMASK            58 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_TID		GENMASK(11, 8)
GENMASK            59 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD2_NORMAL_WLAN_IDX		GENMASK(7, 0)
GENMASK            61 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
GENMASK            63 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_CLS_BITMAP	GENMASK(28, 19)
GENMASK            64 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_WOL		GENMASK(18, 14)
GENMASK            66 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_OFLD		GENMASK(12, 11)
GENMASK            70 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
GENMASK            72 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_VHTA1_B5_B4		GENMASK(31, 30)
GENMASK            73 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_VHTA2_B8_B1		GENMASK(29, 22)
GENMASK            79 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_FRAME_MODE		GENMASK(16, 15)
GENMASK            80 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_TX_MODE			GENMASK(14, 12)
GENMASK            81 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_EXT_LTF		GENMASK(11, 10)
GENMASK            83 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_HT_STBC			GENMASK(8, 7)
GENMASK            84 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV1_TX_RATE			GENMASK(6, 0)
GENMASK            86 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV2_VHTA1_B16_B6		GENMASK(31, 21)
GENMASK            87 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV2_LENGTH			GENMASK(20, 0)
GENMASK            89 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_F_AGC1_CAL_GAIN		GENMASK(31, 29)
GENMASK            91 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_RCPI1			GENMASK(27, 20)
GENMASK            92 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_F_AGC0_CAL_GAIN		GENMASK(19, 17)
GENMASK            94 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_RCPI0			GENMASK(15, 8)
GENMASK            98 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV3_VHTA1_B21_B17		GENMASK(4, 0)
GENMASK           100 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_F_AGC_CAL_GAIN		GENMASK(31, 29)
GENMASK           102 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_IB_RSSI1		GENMASK(27, 20)
GENMASK           103 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_F_AGC_LPF_GAIN_X	GENMASK(19, 16)
GENMASK           104 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_WB_RSSI_X		GENMASK(15, 8)
GENMASK           105 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV4_IB_RSSI0		GENMASK(7, 0)
GENMASK           107 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_LTF_SNR0		GENMASK(31, 26)
GENMASK           108 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_LTF_PROC_TIME		GENMASK(25, 19)
GENMASK           109 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_FOE			GENMASK(18, 7)
GENMASK           110 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_C_AGC_SATE		GENMASK(6, 4)
GENMASK           111 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_F_AGC_LNA_GAIN_0	GENMASK(3, 2)
GENMASK           112 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV5_F_AGC_LNA_GAIN_1	GENMASK(1, 0)
GENMASK           114 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_C_AGC_STATE		GENMASK(30, 28)
GENMASK           115 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_NS_TS_FIELD		GENMASK(27, 25)
GENMASK           117 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_NF2			GENMASK(23, 16)
GENMASK           118 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_NF1			GENMASK(15, 8)
GENMASK           119 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_RXV6_NF0			GENMASK(7, 0)
GENMASK           131 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_Q_IDX			GENMASK(30, 27)
GENMASK           136 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
GENMASK           137 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
GENMASK           139 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_OWN_MAC			GENMASK(31, 26)
GENMASK           141 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_TID			GENMASK(22, 20)
GENMASK           143 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_HDR_PAD			GENMASK(18, 16)
GENMASK           145 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_HDR_FORMAT		GENMASK(14, 13)
GENMASK           146 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_HDR_INFO		GENMASK(12, 8)
GENMASK           147 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD1_WLAN_IDX		GENMASK(7, 0)
GENMASK           152 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_POWER_OFFSET		GENMASK(28, 24)
GENMASK           153 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
GENMASK           154 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_FRAG			GENMASK(15, 14)
GENMASK           163 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
GENMASK           164 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
GENMASK           168 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD3_SEQ			GENMASK(27, 16)
GENMASK           169 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
GENMASK           170 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
GENMASK           172 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD4_PN_LOW			GENMASK(31, 0)
GENMASK           174 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
GENMASK           181 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD5_PID			GENMASK(7, 0)
GENMASK           185 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_TX_RATE			GENMASK(29, 18)
GENMASK           189 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_ANT_PRI			GENMASK(14, 12)
GENMASK           192 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_BW			GENMASK(9, 8)
GENMASK           193 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXD6_ANT_ID			GENMASK(7, 2)
GENMASK           197 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TX_RATE_NSS			GENMASK(10, 9)
GENMASK           198 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TX_RATE_MODE			GENMASK(8, 6)
GENMASK           199 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TX_RATE_IDX			GENMASK(5, 0)
GENMASK           201 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_ANTENNA			GENMASK(31, 26)
GENMASK           202 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TID			GENMASK(25, 22)
GENMASK           211 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
GENMASK           217 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS0_TX_RATE			GENMASK(11, 0)
GENMASK           219 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS1_F0_TIMESTAMP		GENMASK(31, 0)
GENMASK           220 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS1_F1_NOISE_2		GENMASK(23, 16)
GENMASK           221 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS1_F1_NOISE_1		GENMASK(15, 8)
GENMASK           222 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS1_F1_NOISE_0		GENMASK(7, 0)
GENMASK           224 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS2_F0_FRONT_TIME		GENMASK(24, 0)
GENMASK           225 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS2_F1_RCPI_2		GENMASK(23, 16)
GENMASK           226 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS2_F1_RCPI_1		GENMASK(15, 8)
GENMASK           227 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS2_F1_RCPI_0		GENMASK(7, 0)
GENMASK           229 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS3_WCID			GENMASK(31, 24)
GENMASK           230 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS3_RXV_SEQNO		GENMASK(23, 16)
GENMASK           231 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS3_TX_DELAY		GENMASK(15, 0)
GENMASK           233 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_LAST_TX_RATE		GENMASK(31, 29)
GENMASK           234 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_TX_COUNT		GENMASK(28, 24)
GENMASK           237 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_PID			GENMASK(21, 14)
GENMASK           238 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_BW			GENMASK(13, 12)
GENMASK           239 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_F0_SEQNO		GENMASK(11, 0)
GENMASK           240 drivers/net/wireless/mediatek/mt76/mt7603/mac.h #define MT_TXS4_F1_TSSI			GENMASK(11, 0)
GENMASK            14 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_PCIE_REMAP_1_OFFSET	GENMASK(17, 0)
GENMASK            15 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_PCIE_REMAP_1_BASE	GENMASK(31, 18)
GENMASK            18 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_PCIE_REMAP_2_OFFSET	GENMASK(18, 0)
GENMASK            19 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_PCIE_REMAP_2_BASE	GENMASK(31, 19)
GENMASK            29 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_RX_DONE_ALL		GENMASK(1, 0)
GENMASK            30 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_INT_TX_DONE_ALL		GENMASK(19, 4)
GENMASK            44 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE	GENMASK(5, 4)
GENMASK            47 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN	GENMASK(15, 8)
GENMASK            56 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_DEBUG_VALUE		GENMASK(17, 0)
GENMASK            58 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WPDMA_DEBUG_IDX		GENMASK(31, 28)
GENMASK            74 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_SCH_4_FORCE_QID		GENMASK(4, 0)
GENMASK           101 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MCU_DEBUG_RESET_QUEUES	GENMASK(6, 2)
GENMASK           104 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FC_P0_MIN_RESERVE	GENMASK(11, 0)
GENMASK           105 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FC_P0_MAX_QUOTA		GENMASK(27, 16)
GENMASK           108 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FRP_P0			GENMASK(2, 0)
GENMASK           109 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FRP_P1			GENMASK(5, 3)
GENMASK           110 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FRP_P2_RQ0		GENMASK(8, 6)
GENMASK           111 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FRP_P2_RQ1		GENMASK(11, 9)
GENMASK           112 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_FRP_P2_RQ2		GENMASK(14, 12)
GENMASK           115 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_FC_RSV_COUNT_0_P0		GENMASK(11, 0)
GENMASK           116 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_FC_RSV_COUNT_0_P1		GENMASK(27, 16)
GENMASK           119 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0	GENMASK(11, 0)
GENMASK           120 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1	GENMASK(27, 16)
GENMASK           125 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_QUEUE_ID		GENMASK(4, 0)
GENMASK           126 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_PORT_ID		GENMASK(6, 5)
GENMASK           128 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PSE_RTA_TAG_ID		GENMASK(15, 8)
GENMASK           142 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGC_41_RSSI_0		GENMASK(23, 16)
GENMASK           143 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGC_41_RSSI_1		GENMASK(7, 0)
GENMASK           148 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_RXTD_6_ACI_TH		GENMASK(4, 0)
GENMASK           149 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_RXTD_6_CCAED_TH		GENMASK(14, 8)
GENMASK           151 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_RXTD_8_LOWER_SIGNAL		GENMASK(5, 0)
GENMASK           167 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_STAT_PD_OFDM		GENMASK(31, 16)
GENMASK           168 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_STAT_PD_CCK		GENMASK(15, 0)
GENMASK           171 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_STAT_MDRDY_OFDM	GENMASK(31, 16)
GENMASK           172 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PHYCTRL_STAT_MDRDY_CCK	GENMASK(15, 0)
GENMASK           181 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_RTS_RATE_THR	GENMASK(12, 8)
GENMASK           182 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_RATE_DOWN_RATIO	GENMASK(17, 16)
GENMASK           184 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_RATE_UP_EXTRA_TH	GENMASK(22, 20)
GENMASK           185 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARCR_SPE_DIS_TH		GENMASK(27, 24)
GENMASK           190 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_ARxCR_LIMIT(_n)		GENMASK(2 + \
GENMASK           196 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_LIMIT_AC(_n)		GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)
GENMASK           212 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_RTS_THR		GENMASK(19, 0)
GENMASK           213 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_PCR_RTS_PKT_THR		GENMASK(31, 25)
GENMASK           219 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_CFEND_RATE	GENMASK(15, 4)
GENMASK           221 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_CONTROL_BAR_RATE		GENMASK(31, 20)
GENMASK           226 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_BWCR_BW			GENMASK(3, 2)
GENMASK           229 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_RETRY_CONTROL_RTS_LIMIT	GENMASK(11, 7)
GENMASK           230 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_AGG_RETRY_CONTROL_BAR_LIMIT	GENMASK(15, 12)
GENMASK           236 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_DCR0_MAX_RX_LEN		GENMASK(15, 0)
GENMASK           243 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_TARGET_WCID	GENMASK(7, 0)
GENMASK           244 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_TARGET_BSS		GENMASK(13, 8)
GENMASK           245 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_TARGET_QID		GENMASK(20, 16)
GENMASK           246 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_DEST_PORT_ID	GENMASK(23, 22)
GENMASK           247 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_FQCR0_DEST_QUEUE_ID	GENMASK(28, 24)
GENMASK           257 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_TCFR_TXS_AGGR_TIMEOUT	GENMASK(27, 16)
GENMASK           259 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_TCFR_TXS_AGGR_COUNT	GENMASK(12, 8)
GENMASK           260 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_DMA_TCFR_TXS_BIT_MAP		GENMASK(6, 0)
GENMASK           268 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WMM_AIFSN_MASK		GENMASK(3, 0)
GENMASK           274 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WMM_CWMAX_MASK		GENMASK(15, 0)
GENMASK           277 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WMM_CWMIN_MASK		GENMASK(7, 0)
GENMASK           287 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_ARB_SCR_BCNQ_OPMODE_MASK	GENMASK(1, 0)
GENMASK           333 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_ARB_CAB_COUNT_MASK	GENMASK(3, 0)
GENMASK           342 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TX_ABORT_WCID		GENMASK(15, 8)
GENMASK           348 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_BLINK_SEL		GENMASK(7, 6)
GENMASK           349 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_PRE_RTS_GUARD	GENMASK(11, 8)
GENMASK           350 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_PRE_RTS_SEC_IDLE	GENMASK(13, 12)
GENMASK           353 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_TX_STREAMS		GENMASK(17, 16)
GENMASK           354 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_TCR_SCH_IDLE_SEL	GENMASK(19, 18)
GENMASK           371 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WMM_TXOP_MASK		GENMASK(15, 0)
GENMASK           375 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TIMEOUT_VAL_PLCP		GENMASK(15, 0)
GENMASK           376 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TIMEOUT_VAL_CCA		GENMASK(31, 16)
GENMASK           379 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TXREQ_CCA_SRC_SEL		GENMASK(31, 30)
GENMASK           382 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_RXREQ_DELAY			GENMASK(8, 0)
GENMASK           385 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_IFS_EIFS			GENMASK(8, 0)
GENMASK           386 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_IFS_RIFS			GENMASK(14, 10)
GENMASK           387 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_IFS_SIFS			GENMASK(22, 16)
GENMASK           388 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_IFS_SLOT			GENMASK(30, 24)
GENMASK           391 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_RATE		GENMASK(8, 0)
GENMASK           393 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_ANT_ID		GENMASK(21, 16)
GENMASK           396 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_ANT_PRI		GENMASK(26, 24)
GENMASK           397 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TMAC_PCR_ANT_PRI_SEL		GENMASK(27)
GENMASK           431 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MAC_ADDR1_ADDR		GENMASK(15, 0)
GENMASK           436 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BA_CONTROL_1_ADDR		GENMASK(15, 0)
GENMASK           437 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_BA_CONTROL_1_TID		GENMASK(19, 16)
GENMASK           445 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMACDR_MBSSID_MASK	GENMASK(25, 24)
GENMASK           450 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMAC_RMCR_SMPS_MODE	GENMASK(21, 20)
GENMASK           451 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WF_RMAC_RMCR_RX_STREAMS	GENMASK(24, 22)
GENMASK           463 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_SEC_SCR_MASK_ORDER		GENMASK(1, 0)
GENMASK           469 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(7, 0)
GENMASK           484 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LPON_T0CR_MODE		GENMASK(1, 0)
GENMASK           490 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LPON_BTEIR_MBSS_MODE		GENMASK(31, 29)
GENMASK           493 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_PRE_TBTT_MASK		GENMASK(7, 0)
GENMASK           497 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TBTT_PERIOD			GENMASK(15, 0)
GENMASK           498 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TBTT_DTIM_PERIOD		GENMASK(23, 16)
GENMASK           499 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TBTT_TBTT_WAKE_PERIOD	GENMASK(27, 24)
GENMASK           500 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_TBTT_DTIM_WAKE_PERIOD	GENMASK(30, 28)
GENMASK           507 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LPON_SBTOR_TIME_OFFSET	GENMASK(19, 0)
GENMASK           526 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR1_RATE0		GENMASK(11, 0)
GENMASK           527 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR1_RATE1		GENMASK(23, 12)
GENMASK           528 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR1_RATE2_LO		GENMASK(31, 24)
GENMASK           531 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR2_RATE2_HI		GENMASK(3, 0)
GENMASK           532 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR2_RATE3		GENMASK(15, 4)
GENMASK           533 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR2_RATE4		GENMASK(27, 16)
GENMASK           534 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR2_RATE5_LO		GENMASK(31, 28)
GENMASK           537 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR3_RATE5_HI		GENMASK(7, 0)
GENMASK           538 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR3_RATE6		GENMASK(19, 8)
GENMASK           539 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL_RIUCR3_RATE7		GENMASK(31, 20)
GENMASK           545 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_CTL_PSCCA_TIME		GENMASK(13, 11)
GENMASK           546 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_CTL_CCA_NAV_TX		GENMASK(16, 14)
GENMASK           547 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_CTL_ED_TIME		GENMASK(30, 28)
GENMASK           553 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_STAT_CCA_MASK		GENMASK(23, 0)
GENMASK           556 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_STAT_PSCCA_MASK		GENMASK(23, 0)
GENMASK           559 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_MIB_STAT_ED_MASK		GENMASK(23, 0)
GENMASK           583 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_STATUS_OFF_MASK		GENMASK(31, 24)
GENMASK           587 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_STATUS_ON_MASK		GENMASK(23, 16)
GENMASK           591 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_LED_STATUS_DURATION_MASK	GENMASK(15, 0)
GENMASK           614 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_AOUT		GENMASK(5, 0)
GENMASK           615 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_MODE		GENMASK(7, 6)
GENMASK           616 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_LDO_OFF_TIME	GENMASK(13, 8)
GENMASK           617 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_LDO_ON_TIME	GENMASK(15, 14)
GENMASK           618 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_EFUSE_CTRL_AIN		GENMASK(25, 16)
GENMASK           627 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_CLIENT_RXINF_RXSH_GROUPS	GENMASK(2, 0)
GENMASK           641 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_ADDR_HI		GENMASK(15, 0)
GENMASK           642 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_MUAR_IDX		GENMASK(21, 16)
GENMASK           644 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W0_KEY_IDX		GENMASK(24, 23)
GENMASK           653 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W1_ADDR_LO		GENMASK(31, 0)
GENMASK           655 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_MPDU_DENSITY	GENMASK(2, 0)
GENMASK           656 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_KEY_TYPE		GENMASK(6, 3)
GENMASK           661 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W2_AMPDU_FACTOR	GENMASK(13, 11)
GENMASK           681 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_WTBL2_FRAME_ID	GENMASK(10, 0)
GENMASK           682 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_WTBL2_ENTRY_ID	GENMASK(15, 11)
GENMASK           683 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W3_WTBL4_FRAME_ID	GENMASK(26, 16)
GENMASK           690 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W4_WTBL3_FRAME_ID	GENMASK(10, 0)
GENMASK           691 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W4_WTBL3_ENTRY_ID	GENMASK(16, 11)
GENMASK           692 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W4_WTBL4_ENTRY_ID	GENMASK(22, 17)
GENMASK           693 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL1_W4_PARTIAL_AID		GENMASK(31, 23)
GENMASK           695 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W0_PN_LO		GENMASK(31, 0)
GENMASK           697 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W1_PN_HI		GENMASK(15, 0)
GENMASK           698 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W1_NON_QOS_SEQNO	GENMASK(27, 16)
GENMASK           700 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W2_TID0_SN		GENMASK(11, 0)
GENMASK           701 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W2_TID1_SN		GENMASK(23, 12)
GENMASK           702 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W2_TID2_SN_LO		GENMASK(31, 24)
GENMASK           704 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W3_TID2_SN_HI		GENMASK(3, 0)
GENMASK           705 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W3_TID3_SN		GENMASK(15, 4)
GENMASK           706 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W3_TID4_SN		GENMASK(27, 16)
GENMASK           707 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W3_TID5_SN_LO		GENMASK(31, 28)
GENMASK           709 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W4_TID5_SN_HI		GENMASK(7, 0)
GENMASK           710 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W4_TID6_SN		GENMASK(19, 8)
GENMASK           711 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W4_TID7_SN		GENMASK(31, 20)
GENMASK           713 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W5_TX_COUNT_RATE1	GENMASK(15, 0)
GENMASK           716 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W6_TX_COUNT_RATE2	GENMASK(7, 0)
GENMASK           717 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W6_TX_COUNT_RATE3	GENMASK(15, 8)
GENMASK           718 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W6_TX_COUNT_RATE4	GENMASK(23, 16)
GENMASK           719 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W6_TX_COUNT_RATE5	GENMASK(31, 24)
GENMASK           721 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W7_TX_COUNT_CUR_BW	GENMASK(15, 0)
GENMASK           722 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW	GENMASK(31, 16)
GENMASK           724 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W8_TX_COUNT_OTHER_BW	GENMASK(15, 0)
GENMASK           725 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW	GENMASK(31, 16)
GENMASK           727 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_POWER_OFFSET	GENMASK(4, 0)
GENMASK           729 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_ANT_PRIORITY	GENMASK(8, 6)
GENMASK           730 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_CC_BW_SEL		GENMASK(10, 9)
GENMASK           731 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_CHANGE_BW_RATE	GENMASK(13, 11)
GENMASK           732 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_BW_CAP		GENMASK(15, 14)
GENMASK           737 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_MPDU_FAIL_COUNT	GENMASK(25, 23)
GENMASK           738 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_MPDU_OK_COUNT	GENMASK(28, 26)
GENMASK           739 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W9_RATE_IDX		GENMASK(31, 29)
GENMASK           741 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W10_RATE1		GENMASK(11, 0)
GENMASK           742 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W10_RATE2		GENMASK(23, 12)
GENMASK           743 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W10_RATE3_LO		GENMASK(31, 24)
GENMASK           745 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W11_RATE3_HI		GENMASK(3, 0)
GENMASK           746 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W11_RATE4		GENMASK(15, 4)
GENMASK           747 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W11_RATE5		GENMASK(27, 16)
GENMASK           748 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W11_RATE6_LO		GENMASK(31, 28)
GENMASK           750 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W12_RATE6_HI		GENMASK(7, 0)
GENMASK           751 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W12_RATE7		GENMASK(19, 8)
GENMASK           752 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W12_RATE8		GENMASK(31, 20)
GENMASK           754 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W13_AVG_RCPI0		GENMASK(7, 0)
GENMASK           755 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W13_AVG_RCPI1		GENMASK(15, 8)
GENMASK           758 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_CC_NOISE_1S	GENMASK(6, 0)
GENMASK           759 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_CC_NOISE_2S	GENMASK(13, 7)
GENMASK           760 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_CC_NOISE_3S	GENMASK(20, 14)
GENMASK           761 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_CHAN_EST_RMS	GENMASK(24, 21)
GENMASK           763 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W14_ANT_SEL		GENMASK(31, 26)
GENMASK           765 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W15_BA_WIN_SIZE	GENMASK(2, 0)
GENMASK           767 drivers/net/wireless/mediatek/mt76/mt7603/regs.h #define MT_WTBL2_W15_BA_EN_TIDS		GENMASK(31, 24)
GENMASK            30 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.h #define MT_EE_NIC_WIFI_CONF_BAND_SEL		GENMASK(5, 4)
GENMASK          1124 drivers/net/wireless/mediatek/mt76/mt7615/mac.c 	mt76_clear(dev, MT_WF_PHY_R0_B0_PHYMUX_5, GENMASK(22, 20));
GENMASK            10 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_LENGTH			GENMASK(15, 0)
GENMASK            11 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_PKT_TYPE		GENMASK(31, 29)
GENMASK            13 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
GENMASK            32 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
GENMASK            33 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_PAYLOAD_FORMAT	GENMASK(25, 24)
GENMASK            36 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_MAC_HDR_LEN	GENMASK(21, 16)
GENMASK            37 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_CH_FREQ		GENMASK(15, 8)
GENMASK            38 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_KEY_ID		GENMASK(7, 6)
GENMASK            42 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_ADDR_TYPE	GENMASK(2, 1)
GENMASK            43 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD1_NORMAL_BCAST		GENMASK(2, 1)
GENMASK            64 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_SEC_MODE		GENMASK(15, 12)
GENMASK            65 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_TID		GENMASK(11, 8)
GENMASK            66 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD2_NORMAL_WLAN_IDX		GENMASK(7, 0)
GENMASK            68 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
GENMASK            70 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_CLS_BITMAP	GENMASK(28, 19)
GENMASK            71 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_WOL		GENMASK(18, 14)
GENMASK            73 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_OFLD		GENMASK(12, 11)
GENMASK            77 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
GENMASK            81 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_VHTA2_B8_B3		GENMASK(29, 24)
GENMASK            82 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_NUM_RX			GENMASK(23, 22)
GENMASK            88 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_FRAME_MODE		GENMASK(16, 15)
GENMASK            89 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_TX_MODE			GENMASK(14, 12)
GENMASK            90 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_EXT_LTF		GENMASK(11, 10)
GENMASK            92 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_HT_STBC			GENMASK(8, 7)
GENMASK            93 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV1_TX_RATE			GENMASK(6, 0)
GENMASK            97 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV2_NSTS			GENMASK(29, 27)
GENMASK            98 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV2_GROUP_ID		GENMASK(26, 21)
GENMASK            99 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV2_LENGTH			GENMASK(20, 0)
GENMASK           101 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV4_RCPI3			GENMASK(31, 24)
GENMASK           102 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV4_RCPI2			GENMASK(23, 16)
GENMASK           103 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV4_RCPI1			GENMASK(15, 8)
GENMASK           104 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_RXV4_RCPI0			GENMASK(7, 0)
GENMASK           160 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_Q_IDX			GENMASK(30, 26)
GENMASK           163 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
GENMASK           164 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
GENMASK           166 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_OWN_MAC			GENMASK(31, 26)
GENMASK           167 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_PKT_FMT			GENMASK(25, 24)
GENMASK           168 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_TID			GENMASK(23, 21)
GENMASK           171 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_HDR_PAD			GENMASK(18, 17)
GENMASK           174 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_HDR_FORMAT		GENMASK(14, 13)
GENMASK           175 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_HDR_INFO		GENMASK(12, 8)
GENMASK           176 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD1_WLAN_IDX		GENMASK(7, 0)
GENMASK           181 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_POWER_OFFSET		GENMASK(28, 24)
GENMASK           182 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
GENMASK           183 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_FRAG			GENMASK(15, 14)
GENMASK           192 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
GENMASK           193 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
GENMASK           197 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_SEQ			GENMASK(27, 16)
GENMASK           198 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
GENMASK           199 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
GENMASK           203 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD4_PN_LOW			GENMASK(31, 0)
GENMASK           205 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
GENMASK           211 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD5_PID			GENMASK(7, 0)
GENMASK           217 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_TX_RATE			GENMASK(27, 16)
GENMASK           218 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_ANT_ID			GENMASK(15, 4)
GENMASK           221 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD6_BW			GENMASK(1, 0)
GENMASK           223 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD7_TYPE			GENMASK(21, 20)
GENMASK           224 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXD7_SUB_TYPE		GENMASK(19, 16)
GENMASK           227 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TX_RATE_NSS			GENMASK(10, 9)
GENMASK           228 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TX_RATE_MODE			GENMASK(8, 6)
GENMASK           229 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TX_RATE_IDX			GENMASK(5, 0)
GENMASK           252 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TX_FREE_MSDU_ID_CNT		GENMASK(6, 0)
GENMASK           254 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_PID			GENMASK(31, 24)
GENMASK           263 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
GENMASK           269 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS0_TX_RATE			GENMASK(11, 0)
GENMASK           271 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_ANT_ID			GENMASK(31, 20)
GENMASK           272 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
GENMASK           273 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_BW			GENMASK(15, 14)
GENMASK           276 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_TID			GENMASK(11, 9)
GENMASK           279 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS1_TX_POWER_DBM		GENMASK(6, 0)
GENMASK           281 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS2_WCID			GENMASK(31, 24)
GENMASK           282 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS2_RXV_SEQNO		GENMASK(23, 16)
GENMASK           283 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
GENMASK           285 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS3_LAST_TX_RATE		GENMASK(31, 29)
GENMASK           286 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS3_TX_COUNT		GENMASK(28, 24)
GENMASK           287 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS3_F1_TSSI1		GENMASK(23, 12)
GENMASK           288 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS3_F1_TSSI0		GENMASK(11, 0)
GENMASK           289 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS3_F0_SEQNO		GENMASK(11, 0)
GENMASK           291 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS4_F0_TIMESTAMP		GENMASK(31, 0)
GENMASK           292 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS4_F1_TSSI3		GENMASK(23, 12)
GENMASK           293 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS4_F1_TSSI2		GENMASK(11, 0)
GENMASK           295 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS5_F0_FRONT_TIME		GENMASK(24, 0)
GENMASK           296 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS5_F1_NOISE_2		GENMASK(23, 16)
GENMASK           297 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS5_F1_NOISE_1		GENMASK(15, 8)
GENMASK           298 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS5_F1_NOISE_0		GENMASK(7, 0)
GENMASK           300 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS6_F1_RCPI_3		GENMASK(31, 24)
GENMASK           301 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS6_F1_RCPI_2		GENMASK(23, 16)
GENMASK           302 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS6_F1_RCPI_1		GENMASK(15, 8)
GENMASK           303 drivers/net/wireless/mediatek/mt76/mt7615/mac.h #define MT_TXS6_F1_RCPI_0		GENMASK(7, 0)
GENMASK            40 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define FW_FEATURE_SET_KEY_IDX		GENMASK(2, 1)
GENMASK            43 drivers/net/wireless/mediatek/mt76/mt7615/mcu.c #define DL_MODE_KEY_IDX			GENMASK(2, 1)
GENMASK            10 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TOP_MISC2_FW_STATE		GENMASK(2, 0)
GENMASK            16 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MCU_PCIE_REMAP_1_OFFSET	GENMASK(17, 0)
GENMASK            17 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MCU_PCIE_REMAP_1_BASE	GENMASK(31, 18)
GENMASK            21 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MCU_PCIE_REMAP_2_OFFSET	GENMASK(18, 0)
GENMASK            22 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MCU_PCIE_REMAP_2_BASE	GENMASK(31, 19)
GENMASK            37 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_INT_RX_DONE_ALL		GENMASK(1, 0)
GENMASK            38 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_INT_TX_DONE_ALL		GENMASK(7, 4)
GENMASK            46 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE	GENMASK(5, 4)
GENMASK            50 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN	GENMASK(11, 10)
GENMASK            52 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21	GENMASK(23, 22)
GENMASK            77 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHYCTRL_STAT_PD_OFDM	GENMASK(31, 16)
GENMASK            78 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHYCTRL_STAT_PD_CCK	GENMASK(15, 0)
GENMASK            81 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHYCTRL_STAT_MDRDY_OFDM	GENMASK(31, 16)
GENMASK            82 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHYCTRL_STAT_MDRDY_CCK	GENMASK(15, 0)
GENMASK            85 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B0_PD_OFDM_MASK	GENMASK(28, 20)
GENMASK            90 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B1_PD_OFDM_MASK	GENMASK(24, 16)
GENMASK            95 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B0_PD_CCK_MASK	GENMASK(8, 1)
GENMASK            99 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WF_PHY_B1_PD_CCK_MASK	GENMASK(31, 24)
GENMASK           116 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARCR_RTS_RATE_THR	GENMASK(12, 8)
GENMASK           117 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARCR_RATE_DOWN_RATIO	GENMASK(17, 16)
GENMASK           119 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARCR_RATE_UP_EXTRA_TH	GENMASK(22, 20)
GENMASK           124 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ARxCR_LIMIT(_n)		GENMASK(2 + \
GENMASK           133 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ACR_CFEND_RATE		GENMASK(15, 4)
GENMASK           134 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_AGG_ACR_BAR_RATE		GENMASK(31, 20)
GENMASK           144 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_TRCR_CCA_SEL		GENMASK(31, 30)
GENMASK           145 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_TRCR_SEC_CCA_SEL	GENMASK(29, 28)
GENMASK           148 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME	GENMASK(5, 0)
GENMASK           149 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_TMAC_CTCR0_INS_DDLMT_DENSITY	GENMASK(15, 12)
GENMASK           183 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_DMA_DCR0_MAX_RX_LEN		GENMASK(15, 2)
GENMASK           192 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W0_KEY_IDX		GENMASK(24, 23)
GENMASK           196 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W2_KEY_TYPE		GENMASK(7, 4)
GENMASK           199 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(7, 0)
GENMASK           214 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR1_RATE0		GENMASK(11, 0)
GENMASK           215 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR1_RATE1		GENMASK(23, 12)
GENMASK           216 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR1_RATE2_LO		GENMASK(31, 24)
GENMASK           219 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR2_RATE2_HI		GENMASK(3, 0)
GENMASK           220 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR2_RATE3		GENMASK(15, 4)
GENMASK           221 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR2_RATE4		GENMASK(27, 16)
GENMASK           222 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR2_RATE5_LO		GENMASK(31, 28)
GENMASK           225 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR3_RATE5_HI		GENMASK(7, 0)
GENMASK           226 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR3_RATE6		GENMASK(19, 8)
GENMASK           227 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_RIUCR3_RATE7		GENMASK(31, 20)
GENMASK           229 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_CHANGE_BW_RATE	GENMASK(7, 5)
GENMASK           234 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_BW_CAP		GENMASK(13, 12)
GENMASK           235 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_MPDU_FAIL_COUNT	GENMASK(25, 23)
GENMASK           236 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_MPDU_OK_COUNT	GENMASK(28, 26)
GENMASK           237 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W5_RATE_IDX		GENMASK(31, 29)
GENMASK           239 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_WTBL_W27_CC_BW_SEL		GENMASK(6, 5)
GENMASK           245 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_LPON_T0CR_MODE		GENMASK(1, 0)
GENMASK           255 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MIB_RTS_RETRIES_COUNT_MASK	GENMASK(31, 16)
GENMASK           256 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MIB_RTS_COUNT_MASK		GENMASK(15, 0)
GENMASK           259 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_MIB_BUSY_MASK		GENMASK(23, 0)
GENMASK           266 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_AOUT		GENMASK(5, 0)
GENMASK           267 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_MODE		GENMASK(7, 6)
GENMASK           268 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_LDO_OFF_TIME	GENMASK(13, 8)
GENMASK           269 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_LDO_ON_TIME	GENMASK(15, 14)
GENMASK           270 drivers/net/wireless/mediatek/mt76/mt7615/regs.h #define MT_EFUSE_CTRL_AIN		GENMASK(25, 16)
GENMASK            28 drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h 	s8 ret = val & GENMASK(5, 0);
GENMASK           439 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c 	coex3 &= ~GENMASK(5, 2);
GENMASK           466 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c 	mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant);
GENMASK           467 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c 	mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1);
GENMASK            26 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_VCO_BP_CLOSE_LOOP_MASK	GENMASK(3, 0)
GENMASK            27 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_VCO_CAL_MASK		GENMASK(2, 0)
GENMASK            29 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_START_TIME_MASK		GENMASK(2, 0)
GENMASK            30 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_SETTLE_TIME_MASK		GENMASK(6, 4)
GENMASK            32 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_PLL_DEN_MASK		GENMASK(4, 0)
GENMASK            33 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_PLL_K_MASK		GENMASK(4, 0)
GENMASK            35 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_SDM_MASH_PRBS_MASK	GENMASK(6, 2)
GENMASK            37 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_ISI_ISO_MASK		GENMASK(7, 6)
GENMASK            38 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_PFD_DLY_MASK		GENMASK(5, 4)
GENMASK            39 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_CLK_SEL_MASK		GENMASK(3, 2)
GENMASK            40 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF_XO_DIV_MASK		GENMASK(1, 0)
GENMASK            58 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h #define MT_DFS_CHECK_EVENT(x)		((x) != GENMASK(31, 0))
GENMASK            60 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h #define MT_DFS_EVENT_TIMESTAMP(x)	((x) & GENMASK(21, 0))
GENMASK            61 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h #define MT_DFS_EVENT_WIDTH(x)		((x) & GENMASK(11, 0))
GENMASK            12 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_LEN			GENMASK(15, 0)
GENMASK            19 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_QSEL		GENMASK(26, 25)
GENMASK            20 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_DPORT		GENMASK(29, 27)
GENMASK            21 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_TXD_INFO_TYPE		GENMASK(31, 30)
GENMASK            23 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_LEN		GENMASK(13, 0)
GENMASK            25 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_CMD_SEQ		GENMASK(19, 16)
GENMASK            26 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_EVT_TYPE		GENMASK(23, 20)
GENMASK            28 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_QSEL		GENMASK(26, 25)
GENMASK            29 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_D_PORT		GENMASK(29, 27)
GENMASK            30 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_RX_FCE_INFO_TYPE		GENMASK(31, 30)
GENMASK            33 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_LEN			GENMASK(15, 0)
GENMASK            34 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_CMD_SEQ		GENMASK(19, 16)
GENMASK            35 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_CMD_TYPE		GENMASK(26, 20)
GENMASK            36 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_PORT			GENMASK(29, 27)
GENMASK            37 drivers/net/wireless/mediatek/mt76/mt76x02_dma.h #define MT_MCU_MSG_TYPE			GENMASK(31, 30)
GENMASK           102 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_RX_PATH		GENMASK(3, 0)
GENMASK           103 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_TX_PATH		GENMASK(7, 4)
GENMASK           104 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_PA_TYPE		GENMASK(9, 8)
GENMASK           108 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_0_BOARD_TYPE		GENMASK(13, 12)
GENMASK           118 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h #define MT_EE_NIC_CONF_2_XTAL_OPTION		GENMASK(10, 9)
GENMASK          1016 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c 		mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0),
GENMASK            59 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXINFO_PN_LEN		GENMASK(21, 19)
GENMASK            70 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_WCID		GENMASK(7, 0)
GENMASK            71 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_KEY_IDX		GENMASK(9, 8)
GENMASK            72 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_BSS_IDX		GENMASK(12, 10)
GENMASK            73 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_UDF			GENMASK(15, 13)
GENMASK            74 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_CTL_MPDU_LEN		GENMASK(29, 16)
GENMASK            77 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_TID			GENMASK(3, 0)
GENMASK            78 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_SN			GENMASK(15, 4)
GENMASK            80 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_INDEX		GENMASK(5, 0)
GENMASK            82 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_BW			GENMASK(8, 7)
GENMASK            86 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RXWI_RATE_PHY		GENMASK(15, 13)
GENMASK            88 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RATE_INDEX_VHT_IDX		GENMASK(3, 0)
GENMASK            89 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_RATE_INDEX_VHT_NSS		GENMASK(5, 4)
GENMASK           104 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TX_PWR_ADJ			GENMASK(3, 0)
GENMASK           117 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_MPDU_DENSITY	GENMASK(7, 5)
GENMASK           118 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_TXOP		GENMASK(9, 8)
GENMASK           121 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_FLAGS_NDP_BW		GENMASK(13, 12)
GENMASK           127 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h #define MT_TXWI_ACK_CTL_BA_WINDOW	GENMASK(7, 2)
GENMASK            19 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_AOUT		GENMASK(5, 0)
GENMASK            20 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_MODE		GENMASK(7, 6)
GENMASK            21 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_LDO_OFF_TIME	GENMASK(13, 8)
GENMASK            22 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_LDO_ON_TIME	GENMASK(15, 14)
GENMASK            23 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EFUSE_CTRL_AIN		GENMASK(25, 16)
GENMASK            54 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_GPIO_IN	GENMASK(15, 8) /* MT76x0 */
GENMASK            55 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_GPIO_OUT	GENMASK(23, 16) /* MT76x0 */
GENMASK            56 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN	GENMASK(31, 24) /* MT76x0 */
GENMASK            68 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XO_CTRL5_C2_VAL		GENMASK(14, 8)
GENMASK            71 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XO_CTRL6_C2_CTRL		GENMASK(14, 8)
GENMASK            78 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT	GENMASK(7, 0)
GENMASK            79 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT	GENMASK(15, 8)
GENMASK            88 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_USB_DMA_CFG_EP_OUT_VALID	GENMASK(29, 24)
GENMASK            96 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WLAN_MTC_CTRL_BBP_MEM_PD	GENMASK(19, 16)
GENMASK           110 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_RX_DONE_ALL		GENMASK(1, 0)
GENMASK           111 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TX_DONE_ALL		GENMASK(13, 4)
GENMASK           130 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE	GENMASK(5, 4)
GENMASK           133 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN	GENMASK(15, 8)
GENMASK           142 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WMM_AIFSN_MASK		GENMASK(3, 0)
GENMASK           146 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WMM_CWMIN_MASK		GENMASK(3, 0)
GENMASK           150 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WMM_CWMAX_MASK		GENMASK(3, 0)
GENMASK           156 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WMM_TXOP_MASK		GENMASK(15, 0)
GENMASK           167 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_US_CYC_CNT			GENMASK(7, 0)
GENMASK           199 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CSR_CFG_DATA		GENMASK(7, 0)
GENMASK           200 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CSR_CFG_REG_ID		GENMASK(14, 8)
GENMASK           201 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CSR_CFG_REG_BANK		GENMASK(17, 15)
GENMASK           213 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RF_CTRL_ADDR			GENMASK(11, 0)
GENMASK           238 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_STATUS_OFF_MASK		GENMASK(31, 24)
GENMASK           241 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_STATUS_ON_MASK		GENMASK(23, 16)
GENMASK           244 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_LED_STATUS_DURATION_MASK	GENMASK(15, 8)
GENMASK           259 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN	GENMASK(15, 8)
GENMASK           260 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_TS_LEN_EN	GENMASK(23, 16)
GENMASK           261 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_FCE_L2_STUFF_OTHER_PORT	GENMASK(25, 24)
GENMASK           283 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_ADDR_DW1_U2ME_MASK	GENMASK(23, 16)
GENMASK           287 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_ADDR		GENMASK(15, 0)
GENMASK           288 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBSS_MODE	GENMASK(17, 16)
GENMASK           289 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBEACON_N	GENMASK(20, 18)
GENMASK           293 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE	GENMASK(26, 24)
GENMASK           296 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAX_LEN_CFG_AMPDU		GENMASK(13, 12)
GENMASK           315 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_MAC_APC_BSSID_H_ADDR		GENMASK(15, 0)
GENMASK           319 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XIFS_TIME_CFG_CCK_SIFS	GENMASK(7, 0)
GENMASK           320 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XIFS_TIME_CFG_OFDM_SIFS	GENMASK(15, 8)
GENMASK           321 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XIFS_TIME_CFG_OFDM_XIFS	GENMASK(19, 16)
GENMASK           322 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_XIFS_TIME_CFG_EIFS		GENMASK(28, 20)
GENMASK           326 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BKOFF_SLOT_CFG_SLOTTIME	GENMASK(7, 0)
GENMASK           327 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BKOFF_SLOT_CFG_CC_DELAY	GENMASK(11, 8)
GENMASK           337 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_CH_TIMER_CLR	GENMASK(9, 8)
GENMASK           338 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_CH_TIME_CFG_MDRDY_CLR	GENMASK(11, 10)
GENMASK           343 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_INTVAL	GENMASK(15, 0)
GENMASK           345 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_SYNC_MODE	GENMASK(18, 17)
GENMASK           348 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BEACON_TIME_CFG_TSF_COMP	GENMASK(31, 24)
GENMASK           354 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TBTT_TIMER_VAL		GENMASK(16, 0)
GENMASK           357 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TIMER_CFG_PRE_TBTT	GENMASK(15, 0)
GENMASK           358 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_INT_TIMER_CFG_GP_TIMER	GENMASK(31, 16)
GENMASK           388 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EDCA_CFG_TXOP		GENMASK(7, 0)
GENMASK           389 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EDCA_CFG_AIFSN		GENMASK(11, 8)
GENMASK           390 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EDCA_CFG_CWMIN		GENMASK(15, 12)
GENMASK           391 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EDCA_CFG_CWMAX		GENMASK(19, 16)
GENMASK           399 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_PIN_CFG_TXANT		GENMASK(3, 0)
GENMASK           400 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_PIN_CFG_RXANT		GENMASK(11, 8)
GENMASK           421 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TXOP_TRUN_EN			GENMASK(5, 0)
GENMASK           422 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TXOP_EXT_CCA_DLY		GENMASK(15, 8)
GENMASK           426 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_RTS_CFG_RETRY_LIMIT	GENMASK(7, 0)
GENMASK           427 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_RTS_CFG_THRESH		GENMASK(23, 8)
GENMASK           431 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_TIMEOUT_CFG_ACKTO		GENMASK(15, 8)
GENMASK           441 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CFG_RATE		GENMASK(15, 0)
GENMASK           442 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CFG_CTRL		GENMASK(17, 16)
GENMASK           443 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CFG_NAV			GENMASK(19, 18)
GENMASK           444 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_CFG_TXOP_ALLOW		GENMASK(25, 20)
GENMASK           454 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_RATE			GENMASK(15, 0)
GENMASK           471 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_TXOP_ALLOW_ALL		GENMASK(25, 20)
GENMASK           482 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_FBK_LIMIT_MPDU_FBK	GENMASK(7, 0)
GENMASK           483 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_FBK_LIMIT_AMPDU_FBK	GENMASK(15, 8)
GENMASK           494 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_0_CH_INIT_0	GENMASK(5, 0)
GENMASK           495 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_0_CH_INIT_1	GENMASK(13, 8)
GENMASK           496 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_0_LIMIT_0		GENMASK(21, 16)
GENMASK           497 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_0_LIMIT_1		GENMASK(29, 24)
GENMASK           500 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_1_TEMP_COMP	GENMASK(5, 0)
GENMASK           503 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_ALC_CFG_2_TEMP_COMP	GENMASK(5, 0)
GENMASK           549 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_CCA0		GENMASK(1, 0)
GENMASK           550 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_CCA1		GENMASK(3, 2)
GENMASK           551 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_CCA2		GENMASK(5, 4)
GENMASK           552 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_CCA3		GENMASK(7, 6)
GENMASK           553 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_CCA_MASK		GENMASK(11, 8)
GENMASK           554 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_EXT_CCA_CFG_ED_CCA_MASK	GENMASK(15, 12)
GENMASK           564 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_AUTO_TX_CFG_PROT_PADJ	GENMASK(11, 8)
GENMASK           565 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ	GENMASK(27, 24)
GENMASK           568 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_0_CRC_ERRORS		GENMASK(15, 0)
GENMASK           569 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_0_PHY_ERRORS		GENMASK(31, 16)
GENMASK           572 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_1_CCA_ERRORS		GENMASK(15, 0)
GENMASK           573 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_1_PLCP_ERRORS	GENMASK(31, 16)
GENMASK           576 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_2_DUP_ERRORS		GENMASK(15, 0)
GENMASK           577 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_RX_STAT_2_OVERFLOW_ERRORS	GENMASK(31, 16)
GENMASK           588 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_WCID		GENMASK(15, 8)
GENMASK           589 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_RATE		GENMASK(31, 16)
GENMASK           602 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_EXT_RETRY	GENMASK(7, 0)
GENMASK           603 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TX_STAT_FIFO_EXT_PKTID	GENMASK(15, 8)
GENMASK           625 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_CORE_R1_BW		GENMASK(4, 3)
GENMASK           627 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_R0_CTRL_CHAN		GENMASK(9, 8)
GENMASK           628 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_R0_BW		GENMASK(14, 12)
GENMASK           631 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_LNA_HIGH_GAIN	GENMASK(21, 16)
GENMASK           632 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_LNA_MID_GAIN		GENMASK(13, 8)
GENMASK           633 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_LNA_LOW_GAIN		GENMASK(5, 0)
GENMASK           636 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_LNA_ULOW_GAIN	GENMASK(5, 0)
GENMASK           639 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_LNA_GAIN_MODE	GENMASK(7, 6)
GENMASK           640 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC_GAIN			GENMASK(14, 8)
GENMASK           642 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC20_RSSI0		GENMASK(7, 0)
GENMASK           643 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_AGC20_RSSI1		GENMASK(15, 8)
GENMASK           645 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_BBP_TXBE_R0_CTRL_CHAN	GENMASK(1, 0)
GENMASK           662 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_PKEY_MODE		GENMASK(3, 1)
GENMASK           663 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_BSS_IDX		GENMASK(6, 4)
GENMASK           664 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_RXWI_UDF		GENMASK(9, 7)
GENMASK           668 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_WCID_ATTR_WAPI_KEYID		GENMASK(31, 24)
GENMASK           681 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_SKEY_MODE_MASK		GENMASK(3, 0)
GENMASK           687 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h #define MT_TEMP_SENSOR_VAL		GENMASK(6, 0)
GENMASK           313 drivers/net/wireless/mediatek/mt76/mt76x02_util.c 	    (((vif->addr[0] ^ dev->mt76.macaddr[0]) & ~GENMASK(4, 1)) ||
GENMASK            83 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);
GENMASK            85 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);
GENMASK            94 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);
GENMASK            96 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);
GENMASK           107 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20));
GENMASK           108 drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c 		mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9));
GENMASK            19 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_INFO_LEN			GENMASK(15, 0)
GENMASK            20 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_INFO_D_PORT		GENMASK(29, 27)
GENMASK            21 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_INFO_TYPE		GENMASK(31, 30)
GENMASK            45 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_PKT_INFO_QSEL		GENMASK(26, 25)
GENMASK            55 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_CMD_INFO_SEQ		GENMASK(19, 16)
GENMASK            56 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_TXD_CMD_INFO_TYPE		GENMASK(26, 20)
GENMASK            88 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_INFO_LEN			GENMASK(13, 0)
GENMASK            90 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_INFO_QSEL		GENMASK(26, 25)
GENMASK            91 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_INFO_PORT		GENMASK(29, 27)
GENMASK            92 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_INFO_TYPE		GENMASK(31, 30)
GENMASK           100 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_PKT_INFO_MAC_LEN		GENMASK(23, 21)
GENMASK           104 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_CMD_INFO_CMD_SEQ		GENMASK(19, 16)
GENMASK           105 drivers/net/wireless/mediatek/mt7601u/dma.h #define MT_RXD_CMD_INFO_EVT_TYPE	GENMASK(23, 20)
GENMASK            47 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_0_RX_PATH		GENMASK(3, 0)
GENMASK            48 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_0_TX_PATH		GENMASK(7, 4)
GENMASK            49 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_0_BOARD_TYPE		GENMASK(13, 12)
GENMASK            57 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_RX_STREAM		GENMASK(3, 0)
GENMASK            58 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_TX_STREAM		GENMASK(7, 4)
GENMASK            60 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_XTAL_OPTION		GENMASK(10, 9)
GENMASK            62 drivers/net/wireless/mediatek/mt7601u/eeprom.h #define MT_EE_NIC_CONF_2_COEX_METHOD		GENMASK(15, 13)
GENMASK           118 drivers/net/wireless/mediatek/mt7601u/eeprom.h 	WARN_ON(reg & ~GENMASK(5, 0));
GENMASK           119 drivers/net/wireless/mediatek/mt7601u/eeprom.h 	return reg & GENMASK(5, 0);
GENMASK            65 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXINFO_PN_LEN		GENMASK(21, 19)
GENMASK            72 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_WCID		GENMASK(7, 0)
GENMASK            73 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_KEY_IDX		GENMASK(9, 8)
GENMASK            74 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_BSS_IDX		GENMASK(12, 10)
GENMASK            75 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_UDF			GENMASK(15, 13)
GENMASK            76 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_MPDU_LEN		GENMASK(27, 16)
GENMASK            77 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_CTL_TID			GENMASK(31, 28)
GENMASK            79 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_FRAG			GENMASK(3, 0)
GENMASK            80 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_SN			GENMASK(15, 4)
GENMASK            82 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_MCS		GENMASK(6, 0)
GENMASK            85 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_STBC		GENMASK(10, 9)
GENMASK            89 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_RATE_PHY		GENMASK(15, 14)
GENMASK            91 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_GAIN_RSSI_VAL		GENMASK(5, 0)
GENMASK            92 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_GAIN_RSSI_LNA_ID	GENMASK(7, 6)
GENMASK            95 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_RXWI_EANT_ENC_ANT_ID		GENMASK(7, 0)
GENMASK           131 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_MPDU_DENSITY	GENMASK(7, 5)
GENMASK           132 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_TXOP		GENMASK(9, 8)
GENMASK           133 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_FLAGS_CWMIN		GENMASK(12, 10)
GENMASK           138 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_RATE_MCS		GENMASK(6, 0)
GENMASK           141 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_RATE_STBC		GENMASK(10, 9)
GENMASK           142 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_RATE_PHY_MODE		GENMASK(15, 14)
GENMASK           146 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_ACK_CTL_BA_WINDOW	GENMASK(7, 2)
GENMASK           148 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_LEN_BYTE_CNT		GENMASK(11, 0)
GENMASK           149 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_LEN_PKTID		GENMASK(15, 12)
GENMASK           151 drivers/net/wireless/mediatek/mt7601u/mac.h #define MT_TXWI_CTL_TX_POWER_ADJ	GENMASK(3, 0)
GENMASK           467 drivers/net/wireless/mediatek/mt7601u/phy.c #define BBP_R47_FLAG		GENMASK(2, 0)
GENMASK            22 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_AOUT		GENMASK(5, 0)
GENMASK            23 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_MODE		GENMASK(7, 6)
GENMASK            24 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_LDO_OFF_TIME	GENMASK(13, 8)
GENMASK            25 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_LDO_ON_TIME	GENMASK(15, 14)
GENMASK            26 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EFUSE_CTRL_AIN		GENMASK(25, 16)
GENMASK            52 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_GPIO_IN	GENMASK(15, 8) /* MT76x0 */
GENMASK            53 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_GPIO_OUT	GENMASK(23, 16) /* MT76x0 */
GENMASK            54 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN	GENMASK(31, 24) /* MT76x0 */
GENMASK            63 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XO_CTRL5_C2_VAL		GENMASK(14, 8)
GENMASK            66 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XO_CTRL6_C2_CTRL		GENMASK(14, 8)
GENMASK            74 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WLAN_MTC_CTRL_BBP_MEM_PD	GENMASK(19, 16)
GENMASK            88 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_RX_DONE_ALL		GENMASK(1, 0)
GENMASK            89 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TX_DONE_ALL		GENMASK(13, 4)
GENMASK           108 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE	GENMASK(5, 4)
GENMASK           111 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN	GENMASK(15, 8)
GENMASK           120 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WMM_AIFSN_MASK		GENMASK(3, 0)
GENMASK           124 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WMM_CWMIN_MASK		GENMASK(3, 0)
GENMASK           128 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WMM_CWMAX_MASK		GENMASK(3, 0)
GENMASK           134 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WMM_TXOP_MASK		GENMASK(15, 0)
GENMASK           140 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT	GENMASK(7, 0)
GENMASK           141 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT	GENMASK(15, 8)
GENMASK           149 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_USB_DMA_CFG_EP_OUT_VALID	GENMASK(29, 27)
GENMASK           157 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_US_CYC_CNT			GENMASK(7, 0)
GENMASK           191 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CSR_CFG_DATA		GENMASK(7, 0)
GENMASK           192 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CSR_CFG_REG_ID		GENMASK(13, 8)
GENMASK           193 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CSR_CFG_REG_BANK		GENMASK(17, 14)
GENMASK           204 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_RF_CTRL_ADDR			GENMASK(11, 0)
GENMASK           222 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN	GENMASK(15, 8)
GENMASK           223 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_TS_LEN_EN	GENMASK(23, 16)
GENMASK           224 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_FCE_L2_STUFF_OTHER_PORT	GENMASK(25, 24)
GENMASK           248 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_ADDR_DW1_U2ME_MASK	GENMASK(23, 16)
GENMASK           252 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_ADDR		GENMASK(15, 0)
GENMASK           253 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBSS_MODE	GENMASK(17, 16)
GENMASK           254 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBEACON_N	GENMASK(20, 18)
GENMASK           258 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE	GENMASK(26, 24)
GENMASK           261 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAX_LEN_CFG_AMPDU		GENMASK(13, 12)
GENMASK           264 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_VAL		GENMASK(7, 0)
GENMASK           265 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CSR_CFG_REG_NUM		GENMASK(15, 8)
GENMASK           286 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_MAC_APC_BSSID_H_ADDR		GENMASK(15, 0)
GENMASK           290 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XIFS_TIME_CFG_CCK_SIFS	GENMASK(7, 0)
GENMASK           291 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XIFS_TIME_CFG_OFDM_SIFS	GENMASK(15, 8)
GENMASK           292 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XIFS_TIME_CFG_OFDM_XIFS	GENMASK(19, 16)
GENMASK           293 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_XIFS_TIME_CFG_EIFS		GENMASK(28, 20)
GENMASK           297 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BKOFF_SLOT_CFG_SLOTTIME	GENMASK(7, 0)
GENMASK           298 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BKOFF_SLOT_CFG_CC_DELAY	GENMASK(11, 8)
GENMASK           301 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_INTVAL	GENMASK(15, 0)
GENMASK           303 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_SYNC_MODE	GENMASK(18, 17)
GENMASK           306 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BEACON_TIME_CFG_TSF_COMP	GENMASK(31, 24)
GENMASK           312 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TIMER_CFG_PRE_TBTT	GENMASK(15, 0)
GENMASK           313 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_INT_TIMER_CFG_GP_TIMER	GENMASK(31, 16)
GENMASK           338 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EDCA_CFG_TXOP		GENMASK(7, 0)
GENMASK           339 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EDCA_CFG_AIFSN		GENMASK(11, 8)
GENMASK           340 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EDCA_CFG_CWMIN		GENMASK(15, 12)
GENMASK           341 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EDCA_CFG_CWMAX		GENMASK(19, 16)
GENMASK           366 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TXOP_TRUN_EN			GENMASK(5, 0)
GENMASK           367 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TXOP_EXT_CCA_DLY		GENMASK(15, 8)
GENMASK           371 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_RTS_CFG_RETRY_LIMIT	GENMASK(7, 0)
GENMASK           372 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_RTS_CFG_THRESH		GENMASK(23, 8)
GENMASK           390 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_RATE			GENMASK(15, 0)
GENMASK           406 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_PROT_TXOP_ALLOW_ALL		GENMASK(25, 20)
GENMASK           417 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_FBK_LIMIT_MPDU_FBK	GENMASK(7, 0)
GENMASK           418 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_FBK_LIMIT_AMPDU_FBK	GENMASK(15, 8)
GENMASK           428 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_0_CH_INIT_0	GENMASK(5, 0)
GENMASK           429 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_0_CH_INIT_1	GENMASK(13, 8)
GENMASK           430 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_0_LIMIT_0		GENMASK(21, 16)
GENMASK           431 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_0_LIMIT_1		GENMASK(29, 24)
GENMASK           434 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_1_TEMP_COMP	GENMASK(5, 0)
GENMASK           437 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_ALC_CFG_2_TEMP_COMP	GENMASK(5, 0)
GENMASK           480 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_CCA0		GENMASK(1, 0)
GENMASK           481 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_CCA1		GENMASK(3, 2)
GENMASK           482 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_CCA2		GENMASK(5, 4)
GENMASK           483 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_CCA3		GENMASK(7, 6)
GENMASK           484 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_CCA_MASK		GENMASK(11, 8)
GENMASK           485 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_EXT_CCA_CFG_ED_CCA_MASK	GENMASK(15, 12)
GENMASK           512 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_PID_TYPE	GENMASK(4, 1)
GENMASK           516 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_WCID		GENMASK(15, 8)
GENMASK           517 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_RATE		GENMASK(31, 16)
GENMASK           532 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TX_STAT_FIFO_EXT_RETRY	GENMASK(7, 0)
GENMASK           551 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_CORE_R1_BW		GENMASK(4, 3)
GENMASK           553 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC_R0_CTRL_CHAN		GENMASK(9, 8)
GENMASK           554 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC_R0_BW		GENMASK(14, 12)
GENMASK           557 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC_LNA_GAIN		GENMASK(21, 16)
GENMASK           560 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC_GAIN			GENMASK(14, 8)
GENMASK           562 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC20_RSSI0		GENMASK(7, 0)
GENMASK           563 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_AGC20_RSSI1		GENMASK(15, 8)
GENMASK           565 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_BBP_TXBE_R0_CTRL_CHAN	GENMASK(1, 0)
GENMASK           582 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_PKEY_MODE		GENMASK(3, 1)
GENMASK           583 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_BSS_IDX		GENMASK(6, 4)
GENMASK           584 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_RXWI_UDF		GENMASK(9, 7)
GENMASK           588 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_WCID_ATTR_WAPI_KEYID		GENMASK(31, 24)
GENMASK           607 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_SKEY_MODE_MASK		GENMASK(3, 0)
GENMASK           613 drivers/net/wireless/mediatek/mt7601u/regs.h #define MT_TEMP_SENSOR_VAL		GENMASK(6, 0)
GENMASK            19 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            24 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            64 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(5, 0));
GENMASK            69 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(12, 8));
GENMASK            74 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(19, 16));
GENMASK            84 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(23, 22));
GENMASK            89 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(30, 26));
GENMASK           109 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 2, __val, GENMASK(22, 20));
GENMASK           124 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 3, __val, GENMASK(27, 16));
GENMASK           134 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(4, 0));
GENMASK           169 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(21, 20));
GENMASK           174 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(23, 22));
GENMASK           194 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(29, 28));
GENMASK           199 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(31, 30));
GENMASK           204 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(5, 0));
GENMASK           214 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(12, 8));
GENMASK           219 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(16, 13));
GENMASK           224 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 6, __val, GENMASK(15, 11));
GENMASK           234 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc + 7, __val, GENMASK(15, 0));
GENMASK           239 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 7), GENMASK(15, 0));
GENMASK           259 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(13, 0));
GENMASK           274 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(19, 16));
GENMASK           279 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(22, 20));
GENMASK           289 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(25, 24));
GENMASK           324 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           339 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(5, 0));
GENMASK           354 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(19, 16));
GENMASK           359 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(23, 20));
GENMASK           384 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(29, 28));
GENMASK           399 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 2), GENMASK(11, 0));
GENMASK           404 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 2), GENMASK(15, 12));
GENMASK           409 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));
GENMASK           444 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(13, 12));
GENMASK           449 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(15, 14));
GENMASK           501 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	return le32_get_bits(*(__status), GENMASK(8, 0));
GENMASK           516 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(3, 0));
GENMASK           521 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(15, 4));
GENMASK           526 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(27, 16));
GENMASK           531 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(31, 28));
GENMASK           536 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr + 1, __value, GENMASK(7, 0));
GENMASK           541 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr + 1, __value, GENMASK(19, 8));
GENMASK           546 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h 	le32p_replace_bits(__paddr + 1, __value, GENMASK(31, 20));
GENMASK            21 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            26 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            66 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
GENMASK            81 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
GENMASK            86 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));
GENMASK            91 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
GENMASK           101 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
GENMASK           106 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
GENMASK           111 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));
GENMASK           116 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));
GENMASK           156 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));
GENMASK           176 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));
GENMASK           181 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));
GENMASK           186 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
GENMASK           196 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));
GENMASK           201 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
GENMASK           206 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));
GENMASK           211 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
GENMASK           231 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(13, 0));
GENMASK           246 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(19, 16));
GENMASK           251 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(25, 24));
GENMASK           271 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           296 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h 	return le32_get_bits(*((__pdesc + 3)), GENMASK(5, 0));
GENMASK            78 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	return le32_get_bits(*__rxdesc, GENMASK(13, 0));
GENMASK            93 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	return le32_get_bits(*__rxdesc, GENMASK(19, 16));
GENMASK            98 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	return le32_get_bits(*__rxdesc, GENMASK(25, 24));
GENMASK           127 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0));
GENMASK           160 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits(__txdesc, __value, GENMASK(15, 0));
GENMASK           165 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits(__txdesc, __value, GENMASK(23, 16));
GENMASK           202 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0));
GENMASK           222 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8));
GENMASK           227 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16));
GENMASK           237 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22));
GENMASK           242 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26));
GENMASK           254 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20));
GENMASK           261 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16));
GENMASK           266 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28));
GENMASK           273 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0));
GENMASK           313 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20));
GENMASK           333 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28));
GENMASK           338 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30));
GENMASK           345 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
GENMASK           355 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8));
GENMASK           360 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13));
GENMASK           367 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11));
GENMASK           374 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h 	le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0));
GENMASK            19 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            24 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            64 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));
GENMASK            69 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
GENMASK            74 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));
GENMASK            79 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
GENMASK            84 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));
GENMASK           104 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
GENMASK           139 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));
GENMASK           145 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));
GENMASK           150 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));
GENMASK           155 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));
GENMASK           160 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));
GENMASK           166 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));
GENMASK           171 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 5));
GENMASK           181 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
GENMASK           187 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
GENMASK           193 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));
GENMASK           210 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__paddr, __val, GENMASK(3, 0));
GENMASK           215 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__paddr, __val, GENMASK(18, 4));
GENMASK           220 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__paddr, __val, GENMASK(17, 16));
GENMASK           225 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__paddr, __val, GENMASK(5, 2));
GENMASK           230 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__paddr + 1), __val, GENMASK(7, 0));
GENMASK           235 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 17));
GENMASK           240 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits((__paddr + 1), __val, GENMASK(31, 20));
GENMASK           250 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 			   GENMASK(15, 0));
GENMASK           290 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           295 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(30, 16));
GENMASK           324 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__status, __val, GENMASK(13, 0));
GENMASK           339 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	le32p_replace_bits(__status, __val, GENMASK(30, 16));
GENMASK           354 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*(__status), GENMASK(30, 16));
GENMASK           375 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*__pdesc, GENMASK(13, 0));
GENMASK           390 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*__pdesc, GENMASK(19, 16));
GENMASK           395 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*__pdesc, GENMASK(25, 24));
GENMASK           420 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));
GENMASK           435 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));
GENMASK            19 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            24 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            64 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
GENMASK            79 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
GENMASK            84 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));
GENMASK            89 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
GENMASK            99 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
GENMASK           104 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
GENMASK           109 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));
GENMASK           120 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__txdesc + 4), __value, GENMASK(7, 6));
GENMASK           125 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));
GENMASK           155 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));
GENMASK           175 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));
GENMASK           180 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));
GENMASK           185 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
GENMASK           195 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));
GENMASK           200 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
GENMASK           205 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));
GENMASK           210 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
GENMASK           230 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	return le32_get_bits(*__pdesc, GENMASK(13, 0));
GENMASK           245 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	return le32_get_bits(*__pdesc, GENMASK(19, 16));
GENMASK           250 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	return le32_get_bits(*__pdesc, GENMASK(25, 24));
GENMASK           270 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           295 drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));
GENMASK            19 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            24 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            64 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(6, 0));
GENMASK            69 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
GENMASK            74 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(20, 16));
GENMASK            79 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
GENMASK            84 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 1), __val, GENMASK(28, 24));
GENMASK           104 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
GENMASK           109 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(7, 6));
GENMASK           144 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 3), __val, GENMASK(21, 17));
GENMASK           149 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(6, 0));
GENMASK           154 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(12, 8));
GENMASK           159 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(16, 13));
GENMASK           164 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 24));
GENMASK           169 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(3, 0));
GENMASK           179 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(6, 5));
GENMASK           189 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
GENMASK           194 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
GENMASK           204 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__pdesc + 9), __val, GENMASK(23, 12));
GENMASK           224 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*__pdesc, GENMASK(13, 0));
GENMASK           239 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*__pdesc, GENMASK(19, 16));
GENMASK           244 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*__pdesc, GENMASK(25, 24));
GENMASK           264 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           279 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));
GENMASK           294 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));
GENMASK           324 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	return le32_get_bits(*(__pdesc + 4), GENMASK(5, 4));
GENMASK           356 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(3, 0));
GENMASK           361 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(15, 4));
GENMASK           366 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(27, 16));
GENMASK           371 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(31, 28));
GENMASK           376 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0));
GENMASK           381 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8));
GENMASK           386 drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h 	le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20));
GENMASK            19 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
GENMASK            24 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
GENMASK            64 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(6, 0));
GENMASK            69 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(12, 8));
GENMASK            74 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(20, 16));
GENMASK            79 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(23, 22));
GENMASK            84 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 1, __val, GENMASK(28, 24));
GENMASK           104 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 2, __val, GENMASK(22, 20));
GENMASK           109 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 3, __val, GENMASK(7, 6));
GENMASK           144 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 3, __val, GENMASK(21, 17));
GENMASK           149 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(27, 24));
GENMASK           154 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(6, 0));
GENMASK           159 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(12, 8));
GENMASK           164 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(16, 13));
GENMASK           169 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 4, __val, GENMASK(28, 24));
GENMASK           174 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(3, 0));
GENMASK           184 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(6, 5));
GENMASK           194 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 5, __val, GENMASK(16, 13));
GENMASK           199 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 7, __val, GENMASK(15, 0));
GENMASK           209 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc + 9, __val, GENMASK(23, 12));
GENMASK           229 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(13, 0));
GENMASK           244 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(19, 16));
GENMASK           249 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc), GENMASK(25, 24));
GENMASK           269 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
GENMASK           284 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc + 1), GENMASK(6, 0));
GENMASK           299 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc + 3), GENMASK(6, 0));
GENMASK           324 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	return le32_get_bits(*(__pdesc + 4), GENMASK(5, 4));
GENMASK           356 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(3, 0));
GENMASK           361 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(15, 4));
GENMASK           366 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(27, 16));
GENMASK           371 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(31, 28));
GENMASK           376 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits(__paddr, __value, GENMASK(7, 0));
GENMASK           381 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8));
GENMASK           386 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h 	le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20));
GENMASK            50 drivers/net/wireless/realtek/rtw88/coex.h 	le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
GENMASK           157 drivers/net/wireless/realtek/rtw88/coex.h 	COEX_SCBD_ALL		= GENMASK(15, 0),
GENMASK            14 drivers/net/wireless/realtek/rtw88/efuse.h 	le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(3, 0))
GENMASK            16 drivers/net/wireless/realtek/rtw88/efuse.h 	le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(18, 16))
GENMASK            18 drivers/net/wireless/realtek/rtw88/efuse.h 	le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(20, 19))
GENMASK            20 drivers/net/wireless/realtek/rtw88/efuse.h 	le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(23, 21))
GENMASK            22 drivers/net/wireless/realtek/rtw88/efuse.h 	le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(27, 26))
GENMASK           110 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
GENMASK           112 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           114 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
GENMASK           116 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
GENMASK           126 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
GENMASK           128 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
GENMASK           131 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
GENMASK           133 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
GENMASK           135 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
GENMASK           137 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
GENMASK           139 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
GENMASK           161 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
GENMASK           166 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
GENMASK           169 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
GENMASK           171 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
GENMASK           173 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
GENMASK           175 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           177 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
GENMASK           179 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
GENMASK           181 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           183 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           187 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           189 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
GENMASK           191 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
GENMASK           195 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
GENMASK           201 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
GENMASK           205 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
GENMASK           207 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
GENMASK           209 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
GENMASK           211 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
GENMASK           215 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           217 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
GENMASK           219 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           221 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
GENMASK           223 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
GENMASK           225 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           227 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
GENMASK           229 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
GENMASK           231 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           235 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           237 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
GENMASK           239 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           241 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
GENMASK           243 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
GENMASK           245 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
GENMASK           247 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
GENMASK           249 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
GENMASK           251 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
GENMASK           253 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
GENMASK           255 drivers/net/wireless/realtek/rtw88/fw.h 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
GENMASK           345 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_MASK		GENMASK(9, 0)
GENMASK           356 drivers/net/wireless/realtek/rtw88/reg.h #define DIS_DPD_RATEALL		GENMASK(9, 0)
GENMASK           359 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MASK_RFE_SEL89	GENMASK(7, 0)
GENMASK           361 drivers/net/wireless/realtek/rtw88/reg.h #define BIT_MASK_RFE_INV89	GENMASK(1, 0)
GENMASK           999 drivers/net/wireless/realtek/rtw88/rtw8822b.c 	iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
GENMASK           117 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
GENMASK           121 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
GENMASK           123 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
GENMASK           125 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
GENMASK           127 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
GENMASK           129 drivers/net/wireless/realtek/rtw88/rtw8822b.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
GENMASK          1839 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	parity_fail	= FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
GENMASK          1840 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	rate_illegal	= FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
GENMASK          1841 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	crc8_fail	= FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
GENMASK          1842 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	crc8_fail_vhta	= FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
GENMASK          1843 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	mcs_fail	= FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
GENMASK          1844 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	mcs_fail_vht	= FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
GENMASK          1845 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	fast_fsync	= FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
GENMASK          1846 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	sb_search_fail	= FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
GENMASK          2169 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
GENMASK          2170 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
GENMASK          2178 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
GENMASK          2179 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
GENMASK          2348 drivers/net/wireless/realtek/rtw88/rtw8822c.c 	dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
GENMASK          2869 drivers/net/wireless/realtek/rtw88/rtw8822c.c 				 GENMASK(31, 28), 0x9);
GENMASK          2871 drivers/net/wireless/realtek/rtw88/rtw8822c.c 				 GENMASK(31, 28), 0x1);
GENMASK          2873 drivers/net/wireless/realtek/rtw88/rtw8822c.c 				 GENMASK(31, 28), 0x0);
GENMASK          3112 drivers/net/wireless/realtek/rtw88/rtw8822c.c 			rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
GENMASK           135 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
GENMASK           137 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
GENMASK           139 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
GENMASK           141 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
GENMASK           145 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
GENMASK           147 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
GENMASK           149 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
GENMASK           151 drivers/net/wireless/realtek/rtw88/rtw8822c.h 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
GENMASK           166 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BITS_SUBTUNE		GENMASK(15, 12)
GENMASK           182 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BITS_RXAGC_CCK		GENMASK(15, 12)
GENMASK           183 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BITS_RXAGC_OFDM		GENMASK(8, 4)
GENMASK           277 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_SUBPAGE		GENMASK(3, 0)
GENMASK           278 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_TXAGC		GENMASK(4, 0)
GENMASK           279 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_GAIN_TXBB		GENMASK(4, 0)
GENMASK           280 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_LB_ATT		GENMASK(4, 2)
GENMASK           281 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_RXA_MIX_GAIN	GENMASK(4, 3)
GENMASK           282 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_IQ_SWITCH		GENMASK(5, 0)
GENMASK           283 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_DPD_CLK		GENMASK(7, 4)
GENMASK           284 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_RXAGC		GENMASK(9, 5)
GENMASK           285 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_BW_RXBB		GENMASK(11, 10)
GENMASK           286 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_LB_SW		GENMASK(13, 12)
GENMASK           287 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_BW_TXBB		GENMASK(14, 12)
GENMASK           288 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_GLOSS_DB		GENMASK(14, 12)
GENMASK           289 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_TXA_LB_ATT		GENMASK(15, 14)
GENMASK           290 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_TX_OFFSET_VAL	GENMASK(18, 14)
GENMASK           291 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_RPT_SEL		GENMASK(20, 16)
GENMASK           292 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_GS_PWSF		GENMASK(27, 0)
GENMASK           293 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_RPT_DGAIN		GENMASK(27, 16)
GENMASK           294 drivers/net/wireless/realtek/rtw88/rtw8822c.h #define BIT_TX_CFIR		GENMASK(31, 30)
GENMASK          13563 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x1d58, GENMASK(11, 3), 0x1ff,
GENMASK          13570 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x180c, GENMASK(1, 0), 0x0,
GENMASK          13571 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x410c, GENMASK(1, 0), 0x0,
GENMASK          13572 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x1a14, GENMASK(9, 8), 0x3,
GENMASK          13573 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x80c, GENMASK(3, 0), 0x8,
GENMASK          13574 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x824, GENMASK(19, 16), 0x3,
GENMASK          13575 drivers/net/wireless/realtek/rtw88/rtw8822c_table.c 	0x824, GENMASK(27, 24), 0x3,
GENMASK            19 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(13, 0))
GENMASK            21 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(19, 16))
GENMASK            23 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(25, 24))
GENMASK            25 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x03), GENMASK(6, 0))
GENMASK            27 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x01), GENMASK(6, 0))
GENMASK            29 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29))
GENMASK            31 drivers/net/wireless/realtek/rtw88/rx.h 	le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0))
GENMASK            13 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
GENMASK            15 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
GENMASK            17 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
GENMASK            19 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
GENMASK            23 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16))
GENMASK            25 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0))
GENMASK            31 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22))
GENMASK            33 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5))
GENMASK            35 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12))
GENMASK            37 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17))
GENMASK            39 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20))
GENMASK            41 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8))
GENMASK            53 drivers/net/wireless/realtek/rtw88/tx.h 	le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0))
GENMASK           342 drivers/ntb/test/ntb_msi_test.c 	ret = ntb_db_clear_mask(ntb, GENMASK(peers - 1, 0));
GENMASK           936 drivers/nvmem/core.c 	*p &= GENMASK((cell->nbits%BITS_PER_BYTE) - 1, 0);
GENMASK          1016 drivers/nvmem/core.c 		*b++ |= GENMASK(bit_offset - 1, 0) & v;
GENMASK          1036 drivers/nvmem/core.c 		*p |= GENMASK(7, (nbits + bit_offset) % BITS_PER_BYTE) & v;
GENMASK            27 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA			GENMASK(23, 16)
GENMASK            32 drivers/nvmem/meson-mx-efuse.c #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK			GENMASK(10, 0)
GENMASK            27 drivers/nvmem/sc27xx-efuse.c #define SC27XX_EFUSE_BLOCK_MASK		GENMASK(4, 0)
GENMASK            34 drivers/nvmem/vf610-ocotp.c #define OCOTP_CTRL_WR_UNLOCK_MASK		GENMASK(31, 16)
GENMASK            36 drivers/nvmem/vf610-ocotp.c #define OCOTP_CTRL_ADDR_MASK			GENMASK(6, 0)
GENMASK            42 drivers/nvmem/vf610-ocotp.c #define OCOTP_TIMING_STROBE_READ_MASK		GENMASK(21, 16)
GENMASK            44 drivers/nvmem/vf610-ocotp.c #define OCOTP_TIMING_RELAX_MASK			GENMASK(15, 12)
GENMASK            46 drivers/nvmem/vf610-ocotp.c #define OCOTP_TIMING_STROBE_PROG_MASK		GENMASK(11, 0)
GENMASK           562 drivers/pci/controller/dwc/pci-dra7xx.c 	.b1co_mode_sel_mask = GENMASK(3, 2),
GENMASK           572 drivers/pci/controller/dwc/pci-dra7xx.c 	.b1co_mode_sel_mask = GENMASK(3, 2),
GENMASK            40 drivers/pci/controller/dwc/pci-imx6.c #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
GENMASK           110 drivers/pci/controller/dwc/pci-imx6.c #define PCIE_PHY_CTRL_DATA(x)		FIELD_PREP(GENMASK(15, 0), (x))
GENMASK            28 drivers/pci/controller/dwc/pci-meson.c #define LINK_CAPABLE_MASK		GENMASK(21, 16)
GENMASK            32 drivers/pci/controller/dwc/pci-meson.c #define NUM_OF_LANES_MASK		GENMASK(12, 8)
GENMASK            47 drivers/pci/controller/dwc/pci-meson.c #define PCIE_CAP_MAX_PAYLOAD_MASK	GENMASK(7, 5)
GENMASK            49 drivers/pci/controller/dwc/pci-meson.c #define PCIE_CAP_MAX_READ_REQ_MASK	GENMASK(14, 12)
GENMASK           109 drivers/pci/controller/dwc/pcie-al.c #define DEVICE_REV_ID_DEV_ID_MASK	GENMASK(31, 16)
GENMASK           119 drivers/pci/controller/dwc/pcie-al.c #define CFG_TARGET_BUS_MASK_MASK	GENMASK(7, 0)
GENMASK           120 drivers/pci/controller/dwc/pcie-al.c #define CFG_TARGET_BUS_BUSNUM_MASK	GENMASK(15, 8)
GENMASK           123 drivers/pci/controller/dwc/pcie-al.c #define CFG_CONTROL_SUBBUS_MASK		GENMASK(15, 8)
GENMASK           124 drivers/pci/controller/dwc/pcie-al.c #define CFG_CONTROL_SEC_BUS_MASK	GENMASK(23, 16)
GENMASK            51 drivers/pci/controller/dwc/pcie-artpec6.c #define ACK_N_FTS_MASK			GENMASK(15, 8)
GENMASK            54 drivers/pci/controller/dwc/pcie-artpec6.c #define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)
GENMASK            62 drivers/pci/controller/dwc/pcie-artpec6.c #define  PCIECFG_DEVICE_TYPE_MASK	GENMASK(19, 16)
GENMASK            34 drivers/pci/controller/dwc/pcie-designware.h #define PORT_LINK_MODE_MASK		GENMASK(21, 16)
GENMASK            50 drivers/pci/controller/dwc/pcie-designware.h #define PORT_LOGIC_LINK_WIDTH_MASK	GENMASK(12, 8)
GENMASK            81 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_BUS(x)			FIELD_PREP(GENMASK(31, 24), x)
GENMASK            82 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
GENMASK            83 drivers/pci/controller/dwc/pcie-designware.h #define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
GENMASK            44 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_DEVICE_TYPE_MASK		GENMASK(31, 28)
GENMASK            49 drivers/pci/controller/dwc/pcie-histb.c #define PCIE_LTSSM_STATE_MASK		GENMASK(5, 0)
GENMASK            50 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CTRL_HW_HOT_RST_MODE_MASK		GENMASK(1, 0)
GENMASK            86 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK	GENMASK(11, 6)
GENMASK           123 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_DEBUG_LTSSM_STATE_MASK		GENMASK(8, 3)
GENMASK           131 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_DM_TYPE_MASK			GENMASK(3, 0)
GENMASK           136 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CFG_BASE_ADDR_MASK			GENMASK(31, 12)
GENMASK           139 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK	GENMASK(31, 18)
GENMASK           143 drivers/pci/controller/dwc/pcie-tegra194.c #define APPL_CFG_MISC_ARCACHE_MASK		GENMASK(13, 10)
GENMASK           165 drivers/pci/controller/dwc/pcie-tegra194.c #define EVENT_COUNTER_EVENT_SEL_MASK	GENMASK(7, 0)
GENMASK           178 drivers/pci/controller/dwc/pcie-tegra194.c #define L0S_ENTRANCE_LAT_MASK				GENMASK(26, 24)
GENMASK           180 drivers/pci/controller/dwc/pcie-tegra194.c #define L1_ENTRANCE_LAT_MASK				GENMASK(29, 27)
GENMASK           182 drivers/pci/controller/dwc/pcie-tegra194.c #define N_FTS_MASK					GENMASK(7, 0)
GENMASK           187 drivers/pci/controller/dwc/pcie-tegra194.c #define FTS_MASK					GENMASK(7, 0)
GENMASK           194 drivers/pci/controller/dwc/pcie-tegra194.c #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK	GENMASK(23, 8)
GENMASK           195 drivers/pci/controller/dwc/pcie-tegra194.c #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK	GENMASK(3, 0)
GENMASK           201 drivers/pci/controller/dwc/pcie-tegra194.c #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
GENMASK           205 drivers/pci/controller/dwc/pcie-tegra194.c #define AMBA_ERROR_RESPONSE_CRS_MASK		GENMASK(1, 0)
GENMASK           213 drivers/pci/controller/dwc/pcie-tegra194.c #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK	GENMASK(3, 0)
GENMASK           214 drivers/pci/controller/dwc/pcie-tegra194.c #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK	GENMASK(11, 8)
GENMASK            43 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_RCV_INT_ALL_ENABLE		GENMASK(20, 17)
GENMASK            50 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_RCV_INTX_ALL_ENABLE		GENMASK(19, 16)
GENMASK            51 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_RCV_INTX_ALL_MASK		GENMASK(11, 8)
GENMASK            53 drivers/pci/controller/dwc/pcie-uniphier.c #define PCL_RCV_INTX_ALL_STATUS		GENMASK(3, 0)
GENMASK            55 drivers/pci/controller/pci-aardvark.c #define   PIO_CTRL_TYPE_MASK			GENMASK(3, 0)
GENMASK            59 drivers/pci/controller/pci-aardvark.c #define   PIO_COMPLETION_STATUS_MASK		GENMASK(9, 7)
GENMASK           110 drivers/pci/controller/pci-aardvark.c #define	    PCIE_ISR0_ALL_MASK			GENMASK(26, 0)
GENMASK           116 drivers/pci/controller/pci-aardvark.c #define     PCIE_ISR1_ALL_MASK			GENMASK(11, 4)
GENMASK           643 drivers/pci/controller/pci-aardvark.c 	data_strobe = GENMASK(size - 1, 0) << offset;
GENMASK           328 drivers/pci/controller/pci-thunder-pem.c #define PEM_NODE_MASK		GENMASK(45, 44)
GENMASK           329 drivers/pci/controller/pci-thunder-pem.c #define PEM_INDX_MASK		GENMASK(26, 24)
GENMASK           162 drivers/pci/controller/pcie-cadence-host.c 		(lower_32_bits(cpu_addr) & GENMASK(31, 8));
GENMASK            27 drivers/pci/controller/pcie-cadence.c 		(lower_32_bits(pci_addr) & GENMASK(31, 8));
GENMASK            78 drivers/pci/controller/pcie-cadence.c 		(lower_32_bits(cpu_addr) & GENMASK(31, 8));
GENMASK           105 drivers/pci/controller/pcie-cadence.c 		(lower_32_bits(cpu_addr) & GENMASK(31, 8));
GENMASK            20 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_ID_VENDOR_MASK	GENMASK(15, 0)
GENMASK            24 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_ID_SUBSYS_MASK	GENMASK(31, 16)
GENMASK            31 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_RP_RID_MASK	GENMASK(15, 0)
GENMASK            38 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_EP_ID_DEV_MASK	GENMASK(4, 0)
GENMASK            40 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_EP_ID_BUS_MASK	GENMASK(15, 8)
GENMASK            49 drivers/pci/controller/pcie-cadence.h 	(GENMASK(4, 0) << ((b) * 8))
GENMASK            53 drivers/pci/controller/pcie-cadence.h 	(GENMASK(7, 5) << ((b) * 8))
GENMASK            62 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK	GENMASK(5, 0)
GENMASK            65 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK		GENMASK(8, 6)
GENMASK            68 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK	GENMASK(13, 9)
GENMASK            71 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK		GENMASK(16, 14)
GENMASK            94 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_EP_FUNC_BASE(fn)	(((fn) << 12) & GENMASK(19, 12))
GENMASK           112 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK	GENMASK(5, 0)
GENMASK           115 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK	GENMASK(19, 12)
GENMASK           118 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK	GENMASK(27, 20)
GENMASK           129 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK		GENMASK(3, 0)
GENMASK           138 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK	GENMASK(31, 24)
GENMASK           145 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK	GENMASK(7, 0)
GENMASK           152 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK	GENMASK(5, 0)
GENMASK           163 drivers/pci/controller/pcie-cadence.h #define  CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK	GENMASK(5, 0)
GENMASK           185 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK	GENMASK(7, 5)
GENMASK           188 drivers/pci/controller/pcie-cadence.h #define CDNS_PCIE_NORMAL_MSG_CODE_MASK		GENMASK(15, 8)
GENMASK            44 drivers/pci/controller/pcie-mediatek.c #define PCIE_BAR_MAP_MAX	GENMASK(31, 16)
GENMASK            49 drivers/pci/controller/pcie-mediatek.c #define PCIE_CONF_REG(regn)	(((regn) & GENMASK(7, 2)) | \
GENMASK            50 drivers/pci/controller/pcie-mediatek.c 				((((regn) >> 8) & GENMASK(3, 0)) << 24))
GENMASK            51 drivers/pci/controller/pcie-mediatek.c #define PCIE_CONF_FUN(fun)	(((fun) << 8) & GENMASK(10, 8))
GENMASK            52 drivers/pci/controller/pcie-mediatek.c #define PCIE_CONF_DEV(dev)	(((dev) << 11) & GENMASK(15, 11))
GENMASK            53 drivers/pci/controller/pcie-mediatek.c #define PCIE_CONF_BUS(bus)	(((bus) << 16) & GENMASK(23, 16))
GENMASK            60 drivers/pci/controller/pcie-mediatek.c #define PCIE_FTS_NUM_MASK	GENMASK(15, 8)
GENMASK            64 drivers/pci/controller/pcie-mediatek.c #define PCIE_FC_CREDIT_MASK	(GENMASK(31, 31) | GENMASK(28, 16))
GENMASK            80 drivers/pci/controller/pcie-mediatek.c #define INTX_MASK		GENMASK(19, 16)
GENMASK            91 drivers/pci/controller/pcie-mediatek.c #define AHB2PCIE_SIZE(x)	((x) & GENMASK(4, 0))
GENMASK           109 drivers/pci/controller/pcie-mediatek.c #define APP_CPL_STATUS		GENMASK(7, 5)
GENMASK           115 drivers/pci/controller/pcie-mediatek.c #define CFG_DW0_LENGTH(length)	((length) & GENMASK(9, 0))
GENMASK           116 drivers/pci/controller/pcie-mediatek.c #define CFG_DW0_TYPE(type)	(((type) << 24) & GENMASK(28, 24))
GENMASK           117 drivers/pci/controller/pcie-mediatek.c #define CFG_DW0_FMT(fmt)	(((fmt) << 29) & GENMASK(31, 29))
GENMASK           118 drivers/pci/controller/pcie-mediatek.c #define CFG_DW2_REGN(regn)	((regn) & GENMASK(11, 2))
GENMASK           119 drivers/pci/controller/pcie-mediatek.c #define CFG_DW2_FUN(fun)	(((fun) << 16) & GENMASK(18, 16))
GENMASK           120 drivers/pci/controller/pcie-mediatek.c #define CFG_DW2_DEV(dev)	(((dev) << 19) & GENMASK(23, 19))
GENMASK           121 drivers/pci/controller/pcie-mediatek.c #define CFG_DW2_BUS(bus)	(((bus) << 24) & GENMASK(31, 24))
GENMASK           125 drivers/pci/controller/pcie-mediatek.c 	(GENMASK(((size) - 1), 0) << ((where) & 0x3))
GENMASK           136 drivers/pci/controller/pcie-mediatek.c #define PCIE_LINKDOWN_RST_EN	GENMASK(15, 13)
GENMASK            96 drivers/pci/controller/pcie-rcar.c #define  MACCTLR_NFTS_MASK	GENMASK(23, 16)	/* The name is from SH7786 */
GENMASK           132 drivers/pci/controller/pcie-rockchip-ep.c 		u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
GENMASK           133 drivers/pci/controller/pcie-rockchip-ep.c 			       (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
GENMASK            94 drivers/pci/controller/pcie-rockchip-host.c 		return GENMASK(MAX_LANE_NUM - 1, 0);
GENMASK            41 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_DEBUG_LTSSM_MASK		GENMASK(5, 0)
GENMASK            49 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_INTR_MASK			GENMASK(8, 5)
GENMASK            86 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CORE_CTRL_PLC1_FTS_MASK		GENMASK(23, 8)
GENMASK           142 drivers/pci/controller/pcie-rockchip.h #define   PCIE_RC_CONFIG_DCSR_MPS_MASK		GENMASK(7, 5)
GENMASK           149 drivers/pci/controller/pcie-rockchip.h #define   PCIE_RC_CONFIG_THP_CAP_NEXT_MASK	GENMASK(31, 20)
GENMASK           198 drivers/pci/controller/pcie-rockchip.h #define RC_REGION_0_TYPE_MASK			GENMASK(3, 0)
GENMASK           215 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_MSG_ROUTING_MASK			GENMASK(7, 5)
GENMASK           218 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_MSG_CODE_MASK			GENMASK(15, 8)
GENMASK           227 drivers/pci/controller/pcie-rockchip.h #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK		GENMASK(19, 17)
GENMASK           229 drivers/pci/controller/pcie-rockchip.h #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK		GENMASK(22, 20)
GENMASK           234 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn)	(((fn) << 12) & GENMASK(19, 12))
GENMASK           241 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK	GENMASK(19, 12)
GENMASK           245 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK	GENMASK(27, 20)
GENMASK           251 drivers/pci/controller/pcie-rockchip.h #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK	GENMASK(31, 24)
GENMASK           268 drivers/pci/controller/pcie-rockchip.h 		(GENMASK(4, 0) << ((b) * 8))
GENMASK           273 drivers/pci/controller/pcie-rockchip.h 		(GENMASK(7, 5) << ((b) * 8))
GENMASK           109 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
GENMASK           110 drivers/pci/controller/pcie-xilinx-nwl.c #define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
GENMASK           125 drivers/pci/controller/pcie-xilinx-nwl.c #define E_ECAM_SIZE_LOC			GENMASK(20, 16)
GENMASK           131 drivers/pci/controller/pcie-xilinx-nwl.c #define CFG_DMA_REG_BAR			GENMASK(2, 0)
GENMASK            66 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPEFR_REQ_ID	GENMASK(15, 0)
GENMASK            72 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPIFR1_INTR_MASK	GENMASK(28, 27)
GENMASK            77 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_BIR_ECAM_SZ_MASK	GENMASK(18, 16)
GENMASK            81 drivers/pci/controller/pcie-xilinx.c #define XILINX_PCIE_RPIFR2_MSG_DATA	GENMASK(15, 0)
GENMASK            52 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
GENMASK            89 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(24, 0),
GENMASK            91 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(31, 24),
GENMASK            96 drivers/pci/pci-bridge-emul.c 		.rw = (GENMASK(15, 12) | GENMASK(7, 4)),
GENMASK           101 drivers/pci/pci-bridge-emul.c 		       GENMASK(11, 8) | GENMASK(3, 0)),
GENMASK           110 drivers/pci/pci-bridge-emul.c 		.rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
GENMASK           115 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(31, 20) | GENMASK(15, 4),
GENMASK           118 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(19, 16) | GENMASK(3, 0),
GENMASK           123 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(31, 20) | GENMASK(15, 4),
GENMASK           126 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(19, 16) | GENMASK(3, 0),
GENMASK           142 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(7, 0),
GENMASK           143 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(31, 8),
GENMASK           147 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(31, 11) | BIT(0),
GENMASK           148 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(10, 1),
GENMASK           158 drivers/pci/pci-bridge-emul.c 		.rw = (GENMASK(7, 0) |
GENMASK           168 drivers/pci/pci-bridge-emul.c 		.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
GENMASK           172 drivers/pci/pci-bridge-emul.c 		.rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
GENMASK           191 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(15, 0),
GENMASK           197 drivers/pci/pci-bridge-emul.c 		.w1c = GENMASK(19, 16),
GENMASK           198 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(20, 19),
GENMASK           199 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(31, 21),
GENMASK           215 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(11, 3) | GENMASK(1, 0),
GENMASK           216 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(13, 0) << 16,
GENMASK           217 drivers/pci/pci-bridge-emul.c 		.w1c = GENMASK(15, 14) << 16,
GENMASK           218 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(15, 12) | BIT(2),
GENMASK           233 drivers/pci/pci-bridge-emul.c 		.rw = GENMASK(12, 0),
GENMASK           239 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16),
GENMASK           253 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
GENMASK           257 drivers/pci/pci-bridge-emul.c 		.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
GENMASK           259 drivers/pci/pci-bridge-emul.c 		.rsvd = GENMASK(31, 18),
GENMASK            73 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CFGR_SIZE             GENMASK(13, 8)
GENMASK            74 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_CFGR_NCTR             GENMASK(5, 0)
GENMASK            90 drivers/perf/arm_smmuv3_pmu.c #define SMMU_PMCG_DEFAULT_FILTER_SID    GENMASK(31, 0)
GENMASK           199 drivers/perf/arm_spe_pmu.c 	((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
GENMASK            57 drivers/perf/qcom_l2_pmu.c #define L2PMRESR_GROUP_MASK     GENMASK(7, 0)
GENMASK           976 drivers/perf/qcom_l2_pmu.c 	l2_counter_present_mask = GENMASK(l2cache_pmu->num_counters - 2, 0) |
GENMASK            61 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK		GENMASK(27, 24)
GENMASK            67 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c #define SUN6I_DPHY_ANA3_EN_VTTD_MASK		GENMASK(31, 28)
GENMASK           125 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
GENMASK            27 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R3_SQUELCH_REF				GENMASK(1, 0)
GENMASK            28 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R3_HSDIC_REF				GENMASK(3, 2)
GENMASK            29 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R3_DISC_THRESH				GENMASK(7, 4)
GENMASK            32 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R4_CALIB_CODE_7_0			GENMASK(7, 0)
GENMASK            33 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R4_CALIB_CODE_15_8			GENMASK(15, 8)
GENMASK            34 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R4_CALIB_CODE_23_16			GENMASK(23, 16)
GENMASK            39 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0			GENMASK(29, 28)
GENMASK            40 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2			GENMASK(31, 30)
GENMASK            51 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R13_CUSTOM_PATTERN_19			GENMASK(7, 0)
GENMASK            54 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET		GENMASK(20, 16)
GENMASK            69 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R14_I_RPU_SW2_EN			GENMASK(2, 3)
GENMASK            73 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R14_BYPASS_CTRL_7_0			GENMASK(15, 8)
GENMASK            74 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R14_BYPASS_CTRL_15_8			GENMASK(23, 16)
GENMASK            78 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R16_MPLL_M				GENMASK(8, 0)
GENMASK            79 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R16_MPLL_N				GENMASK(14, 10)
GENMASK            84 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R16_MPLL_LOCK_LONG			GENMASK(25, 24)
GENMASK            93 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R17_MPLL_FRAC_IN			GENMASK(13, 0)
GENMASK            95 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R17_MPLL_LAMBDA1			GENMASK(19, 17)
GENMASK            96 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R17_MPLL_LAMBDA0			GENMASK(22, 20)
GENMASK            98 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R17_MPLL_FILTER_PVT2			GENMASK(27, 24)
GENMASK            99 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R17_MPLL_FILTER_PVT1			GENMASK(31, 28)
GENMASK           102 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_LKW_SEL			GENMASK(1, 0)
GENMASK           103 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_LK_W				GENMASK(5, 2)
GENMASK           104 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_LK_S				GENMASK(11, 6)
GENMASK           107 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_PFD_GAIN			GENMASK(15, 14)
GENMASK           108 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_ROU				GENMASK(18, 16)
GENMASK           109 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_DATA_SEL			GENMASK(21, 19)
GENMASK           110 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_BIAS_ADJ			GENMASK(23, 22)
GENMASK           111 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_BB_MODE			GENMASK(25, 24)
GENMASK           112 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_ALPHA				GENMASK(28, 26)
GENMASK           113 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R18_MPLL_ADJ_LDO			GENMASK(30, 29)
GENMASK           119 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0		GENMASK(3, 1)
GENMASK           125 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_DMON_SEL_3_0			GENMASK(12, 9)
GENMASK           127 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0		GENMASK(15, 14)
GENMASK           128 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_BGR_ADJ_4_0			GENMASK(20, 16)
GENMASK           130 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_BGR_VREF_4_0			GENMASK(28, 24)
GENMASK           131 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R20_USB2_BGR_DBG_1_0			GENMASK(30, 29)
GENMASK           139 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0		GENMASK(5, 4)
GENMASK           140 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R21_BYPASS_UTMI_CNTR			GENMASK(15, 6)
GENMASK           141 drivers/phy/amlogic/phy-meson-g12a-usb2.c 	#define PHY_CTRL_R21_BYPASS_UTMI_REG			GENMASK(25, 20)
GENMASK            22 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R0_PCIE_POWER_STATE				GENMASK(4, 0)
GENMASK            23 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R0_PCIE_USB3_SWITCH				GENMASK(6, 5)
GENMASK            26 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_TX1_TERM_OFFSET			GENMASK(4, 0)
GENMASK            27 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_TX0_TERM_OFFSET			GENMASK(9, 5)
GENMASK            28 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_RX1_EQ				GENMASK(12, 10)
GENMASK            29 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_RX0_EQ				GENMASK(15, 13)
GENMASK            30 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_LOS_LEVEL				GENMASK(20, 16)
GENMASK            31 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_LOS_BIAS				GENMASK(23, 21)
GENMASK            33 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R1_PHY_MPLL_MULTIPLIER			GENMASK(31, 25)
GENMASK            36 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB			GENMASK(5, 0)
GENMASK            37 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB			GENMASK(11, 6)
GENMASK            38 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R2_PCS_TX_DEEMPH_GEN1			GENMASK(17, 12)
GENMASK            39 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R2_PHY_TX_VBOOST_LVL			GENMASK(20, 18)
GENMASK            44 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R4_PHY_CR_DATA_IN				GENMASK(17, 2)
GENMASK            49 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c 	#define PHY_R5_PHY_CR_DATA_OUT				GENMASK(15, 0)
GENMASK            37 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R0_FSEL_MASK				GENMASK(19, 17)
GENMASK            38 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R0_REF_CLK_SEL_MASK				GENMASK(21, 20)
GENMASK            40 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R0_V_ATE_TEST_EN_B_MASK			GENMASK(24, 23)
GENMASK            56 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK			GENMASK(8, 7)
GENMASK            57 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_RES_TUNE_MASK				GENMASK(10, 9)
GENMASK            58 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_RISE_TUNE_MASK			GENMASK(12, 11)
GENMASK            59 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_VREF_TUNE_MASK			GENMASK(16, 13)
GENMASK            60 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_FSLS_TUNE_MASK			GENMASK(20, 17)
GENMASK            61 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_TX_HSXV_TUNE_MASK			GENMASK(22, 21)
GENMASK            62 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_OTG_TUNE_MASK				GENMASK(25, 23)
GENMASK            63 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_SQRX_TUNE_MASK				GENMASK(28, 26)
GENMASK            64 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R1_COMP_DIS_TUNE_MASK			GENMASK(31, 29)
GENMASK            68 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R2_TESTDATA_IN_MASK				GENMASK(7, 0)
GENMASK            69 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R2_TESTADDR_MASK				GENMASK(11, 8)
GENMASK            72 drivers/phy/amlogic/phy-meson-gxl-usb2.c 	#define U2P_R2_TESTDATA_OUT_MASK			GENMASK(17, 14)
GENMASK            19 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R0_P30_FSEL_MASK				GENMASK(5, 0)
GENMASK            23 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R0_P30_ACJT_LEVEL_MASK			GENMASK(13, 9)
GENMASK            24 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R0_P30_TX_BOOST_LEVEL_MASK			GENMASK(16, 14)
GENMASK            27 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
GENMASK            28 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
GENMASK            34 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(6, 2)
GENMASK            35 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(11, 7)
GENMASK            36 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(15, 12)
GENMASK            40 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
GENMASK            41 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
GENMASK            44 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R2_P30_CR_DATA_IN_MASK			GENMASK(15, 0)
GENMASK            49 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
GENMASK            50 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
GENMASK            54 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
GENMASK            55 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
GENMASK            57 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R3_P30_LOS_BIAS_MASK			GENMASK(18, 16)
GENMASK            58 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R3_P30_LOS_LEVEL_MASK			GENMASK(23, 19)
GENMASK            59 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R3_P30_MPLL_MULTIPLIER_MASK			GENMASK(30, 24)
GENMASK            64 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
GENMASK            70 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
GENMASK            75 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
GENMASK            76 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
GENMASK            80 drivers/phy/amlogic/phy-meson-gxl-usb3.c 	#define USB_R6_P30_CR_DATA_OUT_MASK			GENMASK(15, 0)
GENMASK            20 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CONFIG_CLK_SEL_MASK			GENMASK(3, 1)
GENMASK            21 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CONFIG_CLK_DIV_MASK			GENMASK(10, 4)
GENMASK            28 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CTRL_SS_SCALEDOWN_MODE_MASK		GENMASK(3, 2)
GENMASK            39 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CTRL_REF_CLK_SEL_MASK		GENMASK(21, 20)
GENMASK            41 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CTRL_FSEL_MASK			GENMASK(24, 22)
GENMASK            44 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_CTRL_THREAD_ID_MASK			GENMASK(31, 26)
GENMASK            81 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TEST_DATA_IN_MASK			GENMASK(3, 0)
GENMASK            82 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TEST_EN_MASK			GENMASK(7, 4)
GENMASK            83 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TEST_ADDR_MASK			GENMASK(11, 8)
GENMASK            86 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TEST_VA_TEST_EN_B_MASK		GENMASK(15, 14)
GENMASK            87 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TEST_DATA_OUT_MASK			GENMASK(19, 16)
GENMASK            91 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_RES_TUNE_MASK		GENMASK(1, 0)
GENMASK            92 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_HSXV_TUNE_MASK		GENMASK(3, 2)
GENMASK            93 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_VREF_TUNE_MASK		GENMASK(7, 4)
GENMASK            94 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_RISE_TUNE_MASK		GENMASK(9, 8)
GENMASK            96 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK	GENMASK(12, 11)
GENMASK            97 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_TX_FSLS_TUNE_MASK		GENMASK(16, 13)
GENMASK            98 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_SQRX_TUNE_MASK			GENMASK(19, 17)
GENMASK            99 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_OTG_TUNE			GENMASK(22, 20)
GENMASK           100 drivers/phy/amlogic/phy-meson8b-usb2.c 	#define REG_TUNE_COMP_DIS_TUNE			GENMASK(25, 23)
GENMASK            23 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_DATA		GENMASK(7, 0)
GENMASK            24 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_ADDR		GENMASK(15, 8)
GENMASK            25 drivers/phy/hisilicon/phy-hisi-inno-usb2.c #define PHY_TEST_PORT		GENMASK(18, 16)
GENMASK            30 drivers/phy/hisilicon/phy-histb-combphy.c #define COMBPHY_TEST_DATA_MASK		GENMASK(23, 20)
GENMASK            32 drivers/phy/hisilicon/phy-histb-combphy.c #define COMBPHY_TEST_ADDR_MASK		GENMASK(16, 12)
GENMASK            32 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK		GENMASK(7, 0)
GENMASK            38 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK	GENMASK(6, 4)
GENMASK            50 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK			GENMASK(15, 13)
GENMASK           122 drivers/phy/marvell/phy-berlin-sata.c 	regval &= ~GENMASK(7, 4);
GENMASK            24 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define   PLL_REF_DIV_MASK			GENMASK(6, 0)
GENMASK            27 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define   PLL_FB_DIV_MASK			GENMASK(24, 16)
GENMASK            30 drivers/phy/marvell/phy-mvebu-a3700-utmi.c #define   PLL_SEL_LPFR_MASK			GENMASK(29, 28)
GENMASK           138 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define COMPHY_FW_POL_MASK	GENMASK(1, 0)
GENMASK           140 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define COMPHY_FW_SPEED_MASK	GENMASK(7, 2)
GENMASK           147 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define COMPHY_FW_PORT_MASK	GENMASK(11, 8)
GENMASK           149 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define COMPHY_FW_MODE_MASK	GENMASK(16, 12)
GENMASK           151 drivers/phy/marvell/phy-mvebu-cp110-comphy.c #define COMPHY_FW_WIDTH_MASK	GENMASK(20, 18)
GENMASK            46 drivers/phy/mediatek/phy-mtk-tphy.c #define PA1_RG_VRT_SEL			GENMASK(14, 12)
GENMASK            48 drivers/phy/mediatek/phy-mtk-tphy.c #define PA1_RG_TERM_SEL		GENMASK(10, 8)
GENMASK            56 drivers/phy/mediatek/phy-mtk-tphy.c #define PA5_RG_U2_HSTX_SRCTRL		GENMASK(14, 12)
GENMASK            63 drivers/phy/mediatek/phy-mtk-tphy.c #define PA6_RG_U2_SQTH		GENMASK(3, 0)
GENMASK            82 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_DATAIN			GENMASK(13, 10)
GENMASK            86 drivers/phy/mediatek/phy-mtk-tphy.c #define P2C_RG_XCVRSEL			GENMASK(5, 4)
GENMASK           117 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_CLKDRV_OFF		GENMASK(3, 2)
GENMASK           121 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_CLKDRV_AMP		GENMASK(31, 29)
GENMASK           125 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_TX_EIDLE_CM		GENMASK(31, 28)
GENMASK           129 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_RX_DAC_MUX		GENMASK(5, 1)
GENMASK           133 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_XTAL_EXT_PE2H		GENMASK(17, 16)
GENMASK           135 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_XTAL_EXT_PE1H		GENMASK(13, 12)
GENMASK           137 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
GENMASK           141 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_DIVEN_PE2H		GENMASK(21, 19)
GENMASK           142 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_BC_PE2H		GENMASK(7, 6)
GENMASK           146 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_BR_PE2H		GENMASK(29, 28)
GENMASK           148 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_IC_PE2H		GENMASK(15, 12)
GENMASK           152 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_IR_PE2H		GENMASK(19, 16)
GENMASK           156 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_BP_PE2H		GENMASK(19, 16)
GENMASK           160 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_DELTA1_PE2H		GENMASK(31, 16)
GENMASK           164 drivers/phy/mediatek/phy-mtk-tphy.c #define P3A_RG_PLL_DELTA_PE2H		GENMASK(15, 0)
GENMASK           168 drivers/phy/mediatek/phy-mtk-tphy.c #define P3D_RG_FWAKE_TH		GENMASK(21, 16)
GENMASK           172 drivers/phy/mediatek/phy-mtk-tphy.c #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
GENMASK           174 drivers/phy/mediatek/phy-mtk-tphy.c #define P3D_RG_CDR_BIR_LTD0		GENMASK(12, 8)
GENMASK           178 drivers/phy/mediatek/phy-mtk-tphy.c #define P3D_RG_RXDET_STB2_SET		GENMASK(17, 9)
GENMASK           182 drivers/phy/mediatek/phy-mtk-tphy.c #define P3D_RG_RXDET_STB2_SET_P3	GENMASK(8, 0)
GENMASK           190 drivers/phy/mediatek/phy-mtk-tphy.c #define P2F_RG_MONCLK_SEL	GENMASK(27, 26)
GENMASK           193 drivers/phy/mediatek/phy-mtk-tphy.c #define P2F_RG_CYCLECNT		GENMASK(23, 0)
GENMASK           210 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BICLTD1_GEN1_MSK		GENMASK(23, 20)
GENMASK           212 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BICLTD0_GEN1_MSK		GENMASK(11, 8)
GENMASK           217 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_LOCK_CNT_SEL_MSK		GENMASK(5, 4)
GENMASK           222 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_TG_MAX_MSK		GENMASK(20, 16)
GENMASK           225 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_T2_MAX_MSK		GENMASK(13, 8)
GENMASK           228 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_TG_MIN_MSK		GENMASK(7, 5)
GENMASK           231 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_T2_MIN_MSK		GENMASK(4, 0)
GENMASK           236 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_IDRV_0DB_GEN1_MSK		GENMASK(13, 8)
GENMASK           240 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BICLTR_GEN1_MSK		GENMASK(23, 20)
GENMASK           243 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BR_GEN2_MSK		GENMASK(10, 8)
GENMASK           248 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BC_GEN1_MSK		GENMASK(28, 24)
GENMASK           250 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BIRLTR_GEN1_MSK		GENMASK(4, 0)
GENMASK           255 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_EQ_DLEQ_LFI_GEN1_MSK		GENMASK(11, 8)
GENMASK           259 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BIRLTD0_GEN1_MSK		GENMASK(20, 16)
GENMASK           263 drivers/phy/mediatek/phy-mtk-tphy.c #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
GENMASK            38 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2F_RG_CYCLECNT		GENMASK(23, 0)
GENMASK            51 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A1_RG_INTR_CAL		GENMASK(23, 19)
GENMASK            53 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A1_RG_VRT_SEL			GENMASK(14, 12)
GENMASK            55 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A1_RG_TERM_SEL		GENMASK(10, 8)
GENMASK            60 drivers/phy/mediatek/phy-mtk-xsphy.c #define P2A5_RG_HSTX_SRCTRL		GENMASK(14, 12)
GENMASK            75 drivers/phy/mediatek/phy-mtk-xsphy.c #define RG_XTP_GLB_BIAS_INTR_CTRL		GENMASK(21, 16)
GENMASK            79 drivers/phy/mediatek/phy-mtk-xsphy.c #define RG_XTP_LN0_TX_IMPSEL		GENMASK(4, 0)
GENMASK            83 drivers/phy/mediatek/phy-mtk-xsphy.c #define RG_XTP_LN0_RX_IMPSEL		GENMASK(4, 0)
GENMASK            24 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define __set(v, a, b)	(((v) << (b)) & GENMASK(a, b))
GENMASK            28 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK	GENMASK(17, 12)
GENMASK            30 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK	GENMASK(11, 6)
GENMASK            32 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK	GENMASK(5, 0)
GENMASK            37 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK	GENMASK(20, 14)
GENMASK            39 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK	GENMASK(13, 7)
GENMASK            41 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK	GENMASK(6, 0)
GENMASK            45 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c #define SATA_PHY_P0_PARAM2_RX_EQ_MASK	GENMASK(20, 18)
GENMASK            66 drivers/phy/qualcomm/phy-qcom-qusb2.c #define IMP_RES_OFFSET_MASK			GENMASK(5, 0)
GENMASK            70 drivers/phy/qualcomm/phy-qcom-qusb2.c #define HSTX_TRIM_MASK				GENMASK(7, 4)
GENMASK            73 drivers/phy/qualcomm/phy-qcom-qusb2.c #define PREEMPHASIS_EN_MASK			GENMASK(1, 0)
GENMASK            24 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
GENMASK            51 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DRIVER_ENABLE			GENMASK(3, 0)
GENMASK            57 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PRE_DIV_MASK			GENMASK(4, 0)
GENMASK            62 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_B_MASK			GENMASK(6, 5)
GENMASK            65 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_A_MASK			GENMASK(4, 0)
GENMASK            68 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_C_MASK			GENMASK(6, 5)
GENMASK            70 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_D_MASK			GENMASK(4, 0)
GENMASK            73 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK		GENMASK(5, 4)
GENMASK            75 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK		GENMASK(3, 2)
GENMASK            77 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK		GENMASK(1, 0)
GENMASK            83 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_PRE_DIV_MASK			GENMASK(4, 0)
GENMASK            90 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_POST_DIV_MASK			GENMASK(5, 4)
GENMASK            94 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_CH_TA_ENABLE			GENMASK(7, 4)
GENMASK           101 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK		GENMASK(5, 4)
GENMASK           103 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK		GENMASK(3, 2)
GENMASK           105 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK		GENMASK(1, 0)
GENMASK           138 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PRE_DIV_MASK			GENMASK(5, 0)
GENMASK           145 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FB_DIV_11_8_MASK			GENMASK(3, 0)
GENMASK           150 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK		GENMASK(1, 0)
GENMASK           152 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK		GENMASK(3, 2)
GENMASK           154 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK		GENMASK(5, 4)
GENMASK           158 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_B_MASK			GENMASK(6, 5)
GENMASK           160 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_A_MASK			GENMASK(4, 0)
GENMASK           164 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_C_MASK			GENMASK(6, 5)
GENMASK           166 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_D_MASK			GENMASK(4, 0)
GENMASK           171 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_POST_DIV_ENABLE			GENMASK(3, 2)
GENMASK           180 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_POST_DIV_MASK			GENMASK(1, 0)
GENMASK           208 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_ESD_DETECT_MASK				GENMASK(7, 6)
GENMASK           214 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TMDS_TERM_RESIST_MASK			GENMASK(5, 0)
GENMASK           236 drivers/phy/rockchip/phy-rockchip-inno-usb2.c 	mask = GENMASK(reg->bitend, reg->bitstart);
GENMASK           247 drivers/phy/rockchip/phy-rockchip-inno-usb2.c 	unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
GENMASK           810 drivers/phy/rockchip/phy-rockchip-inno-usb2.c 	uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
GENMASK           812 drivers/phy/rockchip/phy-rockchip-inno-usb2.c 	ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
GENMASK           122 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_CALIB_CODE_MASK	GENMASK(CMN_CALIB_CODE_WIDTH, 0)
GENMASK           126 drivers/phy/rockchip/phy-rockchip-typec.c #define CMN_CALIB_CODE_POS_MASK	GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
GENMASK            24 drivers/phy/socionext/phy-uniphier-pcie.c #define TESTI_DAT_MASK		GENMASK(13, 6)
GENMASK            25 drivers/phy/socionext/phy-uniphier-pcie.c #define TESTI_ADR_MASK		GENMASK(5, 1)
GENMASK            39 drivers/phy/socionext/phy-uniphier-pcie.c #define   RX_EQ_ADJ		GENMASK(5, 0)	/* EQ adjustment value */
GENMASK            42 drivers/phy/socionext/phy-uniphier-pcie.c #define   VCO_CTRL		GENMASK(7, 4)	/* Tx VCO adjustment value */
GENMASK            27 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG0_HS_I_MASK	GENMASK(31, 28)
GENMASK            28 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG0_HSDISC_MASK	GENMASK(27, 26)
GENMASK            29 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG0_SWING_MASK	GENMASK(17, 16)
GENMASK            30 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG0_SEL_T_MASK	GENMASK(15, 12)
GENMASK            31 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG0_RTERM_MASK	GENMASK(7, 6)
GENMASK            39 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG1_ADR_MASK	GENMASK(27, 16)
GENMASK            40 drivers/phy/socionext/phy-uniphier-usb3hs.c #define HSPHY_CFG1_DAT_MASK	GENMASK(23, 16)
GENMASK           176 drivers/phy/socionext/phy-uniphier-usb3hs.c 	u32 field_mask = GENMASK(p->field.msb, p->field.lsb);
GENMASK            26 drivers/phy/socionext/phy-uniphier-usb3ss.c #define TESTI_DAT_MASK		GENMASK(13, 6)
GENMASK            27 drivers/phy/socionext/phy-uniphier-usb3ss.c #define TESTI_ADR_MASK		GENMASK(5, 1)
GENMASK            80 drivers/phy/socionext/phy-uniphier-usb3ss.c 	u8 field_mask = GENMASK(p->field.msb, p->field.lsb);
GENMASK            23 drivers/phy/st/phy-stm32-usbphyc.c #define PLLNDIV			GENMASK(6, 0)
GENMASK            24 drivers/phy/st/phy-stm32-usbphyc.c #define PLLFRACIN		GENMASK(25, 10)
GENMASK            36 drivers/phy/st/phy-stm32-usbphyc.c #define MINREV			GENMASK(3, 0)
GENMASK            37 drivers/phy/st/phy-stm32-usbphyc.c #define MAJREV			GENMASK(7, 4)
GENMASK            61 drivers/phy/ti/phy-am654-serdes.c #define AM654_SERDES_CTRL_CLKSEL_MASK	GENMASK(7, 4)
GENMASK            49 drivers/phy/ti/phy-ti-pipe3.c #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK	GENMASK(21, 14)
GENMASK            52 drivers/phy/ti/phy-ti-pipe3.c #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK	GENMASK(31, 22)
GENMASK            62 drivers/phy/ti/phy-ti-pipe3.c #define INTERFACE_MASK			GENMASK(31, 27)
GENMASK            69 drivers/phy/ti/phy-ti-pipe3.c #define LOSD_MASK			GENMASK(17, 14)
GENMASK            71 drivers/phy/ti/phy-ti-pipe3.c #define MEM_PLLDIV			GENMASK(6, 5)
GENMASK            74 drivers/phy/ti/phy-ti-pipe3.c #define MEM_DLL_TRIM_SEL_MASK		GENMASK(31, 30)
GENMASK            78 drivers/phy/ti/phy-ti-pipe3.c #define MEM_DLL_PHINT_RATE_MASK		GENMASK(31, 30)
GENMASK            82 drivers/phy/ti/phy-ti-pipe3.c #define MEM_HS_RATE_MASK		GENMASK(28, 27)
GENMASK            88 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_LBW_MASK		GENMASK(22, 21)
GENMASK            90 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_STEPCNT_MASK		GENMASK(20, 19)
GENMASK            92 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_STL_MASK		GENMASK(18, 16)
GENMASK            94 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_THR_MASK		GENMASK(15, 13)
GENMASK           102 drivers/phy/ti/phy-ti-pipe3.c #define MEM_EQLEV_MASK			GENMASK(31, 16)
GENMASK           104 drivers/phy/ti/phy-ti-pipe3.c #define MEM_EQFTC_MASK			GENMASK(15, 11)
GENMASK           106 drivers/phy/ti/phy-ti-pipe3.c #define MEM_EQCTL_MASK			GENMASK(10, 7)
GENMASK           114 drivers/phy/ti/phy-ti-pipe3.c #define MEM_CDR_LOS_SOURCE_MASK		GENMASK(10, 9)
GENMASK           469 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define BOOT_SRC_NOR	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
GENMASK           530 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
GENMASK           532 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
GENMASK           534 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
GENMASK           690 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPI18_DESC	{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
GENMASK           691 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPI24_DESC	{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
GENMASK           692 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPI30_DESC	{ ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
GENMASK          1120 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPOOFF0_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
GENMASK          1121 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPO12_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
GENMASK          1122 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPO24_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
GENMASK          1123 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c #define VPOOFF1_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
GENMASK            60 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define COND2		{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
GENMASK           516 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
GENMASK           518 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
GENMASK           520 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
GENMASK           694 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPIOFF0_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
GENMASK           695 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPIOFF1_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
GENMASK           696 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPI24_DESC      { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
GENMASK           697 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPIRSVD_DESC    { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
GENMASK          1023 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPOOFF0_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
GENMASK          1024 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPO_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
GENMASK          1025 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPOOFF1_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
GENMASK          1026 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define VPOOFF2_DESC	{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
GENMASK          1541 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
GENMASK          1544 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
GENMASK          1547 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
GENMASK          1550 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
GENMASK          1867 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define USB11BHID_DESC  { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
GENMASK          1868 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define USB2BD_DESC   { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
GENMASK          1869 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
GENMASK          1870 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
GENMASK           165 drivers/pinctrl/berlin/berlin.c 	mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1,
GENMASK            40 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_TRIG_MASK		GENMASK(26, 24)
GENMASK            49 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_PULL_STR_MASK	GENMASK(10, 9)
GENMASK            55 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_PULL_ASSIGN_MASK	GENMASK(8, 7)
GENMASK            58 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_PIN_MUX		GENMASK(2, 0)
GENMASK            61 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_DIR_MASK		GENMASK(2, 1)
GENMASK            70 drivers/pinctrl/intel/pinctrl-baytrail.c #define BYT_DEBOUNCE_PULSE_MASK		GENMASK(2, 0)
GENMASK          1608 drivers/pinctrl/intel/pinctrl-cherryview.c 		chv_writel(GENMASK(31, pctrl->community->nirqs),
GENMASK            30 drivers/pinctrl/intel/pinctrl-intel.c #define REVID_MASK			GENMASK(31, 16)
GENMASK            36 drivers/pinctrl/intel/pinctrl-intel.c #define PADOWN_MASK(p)			(GENMASK(3, 0) << PADOWN_SHIFT(p))
GENMASK            42 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_RXEVCFG_MASK		GENMASK(26, 25)
GENMASK            54 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG0_PMODE_MASK		GENMASK(13, 10)
GENMASK            64 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG1_TERM_MASK		GENMASK(12, 10)
GENMASK            73 drivers/pinctrl/intel/pinctrl-intel.c #define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)
GENMASK            30 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_PINMODE_MASK		GENMASK(2, 0)
GENMASK            33 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_PUPD_VAL_MASK		GENMASK(5, 4)
GENMASK            40 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_Px_EN_MASK		GENMASK(9, 8)
GENMASK            44 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVINEN_MASK		GENMASK(13, 12)
GENMASK            47 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OVOUTEN_MASK		GENMASK(15, 14)
GENMASK            50 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_INDATAOV_MASK		GENMASK(17, 16)
GENMASK            53 drivers/pinctrl/intel/pinctrl-merrifield.c #define BUFCFG_OUTDATAOV_MASK		GENMASK(19, 18)
GENMASK            35 drivers/pinctrl/pinctrl-at91-pio4.c #define		ATMEL_PIO_CFGR_FUNC_MASK	GENMASK(2, 0)
GENMASK            43 drivers/pinctrl/pinctrl-at91-pio4.c #define		ATMEL_PIO_DRVSTR_MASK		GENMASK(17, 16)
GENMASK            45 drivers/pinctrl/pinctrl-at91-pio4.c #define		ATMEL_PIO_CFGR_EVTSEL_MASK	GENMASK(26, 24)
GENMASK           104 drivers/pinctrl/pinctrl-gemini.c #define GEMINI_GMAC_IOSEL_MASK	GENMASK(28, 27)
GENMASK           124 drivers/pinctrl/pinctrl-gemini.c #define PADS_MASK		(GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
GENMASK           749 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(21, 20),
GENMASK           765 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(17, 16),
GENMASK           773 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(19, 18),
GENMASK           781 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(23, 22),
GENMASK          1698 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(21, 20),
GENMASK          1715 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(17, 16),
GENMASK          1724 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(19, 18),
GENMASK          1732 drivers/pinctrl/pinctrl-gemini.c 		.driving_mask = GENMASK(23, 22),
GENMASK          2306 drivers/pinctrl/pinctrl-gemini.c 	.mask = GENMASK(_hb, _lb)		\
GENMASK            59 drivers/pinctrl/pinctrl-rza1.c #define MUX_PIN_ID_MASK			GENMASK(15, 0)
GENMASK            60 drivers/pinctrl/pinctrl-rza1.c #define MUX_FUNC_MASK			GENMASK(31, 16)
GENMASK            33 drivers/pinctrl/pinctrl-rza2.c #define MUX_PIN_ID_MASK		GENMASK(15, 0)
GENMASK            34 drivers/pinctrl/pinctrl-rza2.c #define MUX_FUNC_MASK		GENMASK(31, 16)
GENMASK           571 drivers/pinctrl/pinctrl-stmfx.c 	pctl->gpio_valid_mask = GENMASK(15, 0);
GENMASK           576 drivers/pinctrl/pinctrl-stmfx.c 		pctl->gpio_valid_mask |= GENMASK(19, 16);
GENMASK           582 drivers/pinctrl/pinctrl-stmfx.c 		pctl->gpio_valid_mask |= GENMASK(23, 20);
GENMASK           168 drivers/pinctrl/qcom/pinctrl-msm.c 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
GENMASK           523 drivers/pinctrl/sh-pfc/pinctrl.c 	val = (val >> offset) & GENMASK(size - 1, 0);
GENMASK           558 drivers/pinctrl/sh-pfc/pinctrl.c 	val &= ~GENMASK(offset + size - 1, offset);
GENMASK            44 drivers/pinctrl/sprd/pinctrl-sprd.c #define SLEEP_MODE_MASK			GENMASK(3, 0)
GENMASK            55 drivers/pinctrl/sprd/pinctrl-sprd.c #define DRIVE_STRENGTH_MASK		GENMASK(3, 0)
GENMASK            49 drivers/pinctrl/stm32/pinctrl-stm32.c #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
GENMASK            51 drivers/pinctrl/stm32/pinctrl-stm32.c #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
GENMASK            53 drivers/pinctrl/stm32/pinctrl-stm32.c #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
GENMASK            55 drivers/pinctrl/stm32/pinctrl-stm32.c #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
GENMASK            62 drivers/pinctrl/stm32/pinctrl-stm32.c #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
GENMASK           711 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= ~GENMASK(alt_shift + 3, alt_shift);
GENMASK           716 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
GENMASK           744 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= GENMASK(alt_shift + 3, alt_shift);
GENMASK           748 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= GENMASK(pin * 2 + 1, pin * 2);
GENMASK           884 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
GENMASK           910 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= GENMASK(offset * 2 + 1, offset * 2);
GENMASK           938 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
GENMASK           964 drivers/pinctrl/stm32/pinctrl-stm32.c 	val &= GENMASK(offset * 2 + 1, offset * 2);
GENMASK            84 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define IO_BIAS_MASK		GENMASK(3, 0)
GENMASK           196 drivers/platform/olpc/olpc-xo175-ec.c #define EC_ALL_EVENTS		GENMASK(15, 0)
GENMASK            18 drivers/platform/x86/i2c-multi-instantiate.c #define IRQ_RESOURCE_TYPE	GENMASK(1, 0)
GENMASK           180 drivers/platform/x86/intel_pmc_core.h #define LTR_DECODED_VAL				GENMASK(9, 0)
GENMASK           181 drivers/platform/x86/intel_pmc_core.h #define LTR_DECODED_SCALE			GENMASK(12, 10)
GENMASK            28 drivers/platform/x86/intel_punit_ipc.c #define	CMD_ERRCODE_MASK	GENMASK(7, 0)
GENMASK           103 drivers/platform/x86/intel_speed_select_if/isst_if_mmio.c 	pcu_base &= GENMASK(10, 0);
GENMASK           113 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_PSU_MASK		GENMASK(1, 0)
GENMASK           114 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_PWR_MASK		GENMASK(1, 0)
GENMASK           115 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_FAN_MASK		GENMASK(3, 0)
GENMASK           116 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_ASIC_MASK		GENMASK(1, 0)
GENMASK           117 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_FAN_NG_MASK	GENMASK(5, 0)
GENMASK           118 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK	GENMASK(7, 4)
GENMASK           119 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK	GENMASK(3, 0)
GENMASK           147 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD1_CLEAR_MASK	GENMASK(7, 1)
GENMASK           148 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD2_CLEAR_MASK	(GENMASK(7, 0) & ~BIT(1))
GENMASK           150 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK	GENMASK(7, 4)
GENMASK           152 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_RESET_ACT_MASK	GENMASK(7, 1)
GENMASK           153 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_FAN_ACT_MASK	(GENMASK(7, 0) & ~BIT(4))
GENMASK           154 drivers/platform/x86/mlx-platform.c #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK	(GENMASK(7, 0) & ~BIT(7))
GENMASK           972 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK           978 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK           984 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK           990 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK           996 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1002 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1008 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(4),
GENMASK          1014 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(5),
GENMASK          1020 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1026 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(7),
GENMASK          1032 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1038 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1044 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1050 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1056 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1078 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1084 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1090 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1096 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1102 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1108 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1114 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(4),
GENMASK          1120 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(5),
GENMASK          1126 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1132 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1138 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1144 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1150 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1156 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1178 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1184 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1190 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1196 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1202 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1208 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1214 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1220 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(4),
GENMASK          1226 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(5),
GENMASK          1232 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1238 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(7),
GENMASK          1244 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1250 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1256 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1262 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1268 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1274 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(5),
GENMASK          1280 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(0),
GENMASK          1286 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(1),
GENMASK          1292 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(2),
GENMASK          1298 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(3),
GENMASK          1304 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(4),
GENMASK          1317 drivers/platform/x86/mlx-platform.c 		.bit = GENMASK(7, 0),
GENMASK          1336 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1343 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1350 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1357 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1364 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1371 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1378 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1385 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1392 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1399 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1406 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1413 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0),
GENMASK          1453 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK          1524 drivers/platform/x86/mlx-platform.c 		.mask = GENMASK(7, 0) & ~BIT(6),
GENMASK            28 drivers/power/reset/at91-poweroff.c #define AT91_SHDW_WKMODE0	GENMASK(2, 0)		/* Wake-up 0 Mode Selection */
GENMASK            32 drivers/power/reset/at91-reset.c #define AT91_RSTC_RSTTYP	GENMASK(10, 8)	/* Reset Type */
GENMASK            39 drivers/power/reset/at91-reset.c #define AT91_RSTC_ERSTL		GENMASK(11, 8)	/* External Reset Length */
GENMASK            40 drivers/power/reset/at91-sama5d2_shdwc.c #define AT91_SHDW_WKUPDBC_MASK	GENMASK(31, 16)
GENMASK            46 drivers/power/reset/at91-sama5d2_shdwc.c #define AT91_SHDW_WKUPIS_MASK	GENMASK(31, 16)
GENMASK            51 drivers/power/reset/at91-sama5d2_shdwc.c #define AT91_SHDW_WKUPEN_MASK	GENMASK(15, 0)
GENMASK            54 drivers/power/reset/at91-sama5d2_shdwc.c #define AT91_SHDW_WKUPT_MASK	GENMASK(31, 16)
GENMASK            30 drivers/power/reset/ocelot-reset.c #define IF_SI_OWNER_MASK			GENMASK(1, 0)
GENMASK            39 drivers/power/supply/adp5061.c #define ADP5061_VINX_SET_ILIM_MSK		GENMASK(3, 0)
GENMASK            43 drivers/power/supply/adp5061.c #define ADP5061_TERM_SET_VTRM_MSK		GENMASK(7, 2)
GENMASK            45 drivers/power/supply/adp5061.c #define ADP5061_TERM_SET_CHG_VLIM_MSK		GENMASK(1, 0)
GENMASK            49 drivers/power/supply/adp5061.c #define ADP5061_CHG_CURR_ICHG_MSK		GENMASK(6, 2)
GENMASK            51 drivers/power/supply/adp5061.c #define ADP5061_CHG_CURR_ITRK_DEAD_MSK		GENMASK(1, 0)
GENMASK            57 drivers/power/supply/adp5061.c #define ADP5061_VOLTAGE_TH_VRCH_MSK		GENMASK(6, 5)
GENMASK            59 drivers/power/supply/adp5061.c #define ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK	GENMASK(4, 3)
GENMASK            61 drivers/power/supply/adp5061.c #define ADP5061_VOLTAGE_TH_VWEAK_MSK		GENMASK(2, 0)
GENMASK            78 drivers/power/supply/adp5061.c #define ADP5061_IEND_IEND_MSK			GENMASK(7, 5)
GENMASK            28 drivers/power/supply/axp20x_ac_power.c #define AXP813_VHOLD_MASK		GENMASK(5, 3)
GENMASK            33 drivers/power/supply/axp20x_ac_power.c #define AXP813_CURR_LIMIT_MASK		GENMASK(2, 0)
GENMASK            40 drivers/power/supply/axp20x_battery.c #define AXP209_FG_PERCENT		GENMASK(6, 0)
GENMASK            43 drivers/power/supply/axp20x_battery.c #define AXP20X_CHRG_CTRL1_TGT_VOLT	GENMASK(6, 5)
GENMASK            54 drivers/power/supply/axp20x_battery.c #define AXP20X_CHRG_CTRL1_TGT_CURR	GENMASK(3, 0)
GENMASK            56 drivers/power/supply/axp20x_battery.c #define AXP20X_V_OFF_MASK		GENMASK(2, 0)
GENMASK            33 drivers/power/supply/axp20x_usb_power.c #define AXP20X_VBUS_VHOLD_MASK		GENMASK(5, 3)
GENMASK            20 drivers/power/supply/max77650-charger.c #define MAX77650_CHG_DETAILS_MASK		GENMASK(7, 4)
GENMASK            51 drivers/power/supply/max77650-charger.c #define MAX77650_CHGIN_DETAILS_MASK		GENMASK(3, 2)
GENMASK            32 drivers/power/supply/sbs-manager.c #define SBSM_MASK_BAT_SUPPORTED  GENMASK(3, 0)
GENMASK            33 drivers/power/supply/sbs-manager.c #define SBSM_MASK_CHARGE_BAT     GENMASK(7, 4)
GENMASK            28 drivers/power/supply/sc2731_charger.c #define SC2731_PRECHG_RNG_MASK		GENMASK(12, 11)
GENMASK            30 drivers/power/supply/sc2731_charger.c #define SC2731_TERMINATION_VOL_MASK	GENMASK(2, 1)
GENMASK            32 drivers/power/supply/sc2731_charger.c #define SC2731_TERMINATION_VOL_CAL_MASK	GENMASK(8, 3)
GENMASK            34 drivers/power/supply/sc2731_charger.c #define SC2731_TERMINATION_CUR_MASK	GENMASK(2, 0)
GENMASK            40 drivers/power/supply/sc2731_charger.c #define SC2731_CUR_MASK			GENMASK(5, 0)
GENMASK            44 drivers/power/supply/sc2731_charger.c #define SC2731_CUR_LIMIT_MASK		GENMASK(9, 8)
GENMASK            47 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_CLBCNT_MASK		GENMASK(15, 0)
GENMASK            49 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_LOW_OVERLOAD_MASK	GENMASK(12, 0)
GENMASK            51 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_INT_MASK		GENMASK(9, 0)
GENMASK            55 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_MODE_AREA_MASK	GENMASK(15, 12)
GENMASK            56 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_CAP_AREA_MASK	GENMASK(11, 0)
GENMASK            59 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_FIRST_POWERTON	GENMASK(3, 0)
GENMASK            60 drivers/power/supply/sc27xx_fuel_gauge.c #define SC27XX_FGU_DEFAULT_CAP		GENMASK(11, 0)
GENMASK            57 drivers/power/supply/ucs1002_power.c #  define F_ACTIVE_MODE_MASK		GENMASK(5, 3)
GENMASK            80 drivers/power/supply/ucs1002_power.c #  define V_SET_ACTIVE_MODE_MASK	GENMASK(5, 3)
GENMASK            89 drivers/power/supply/ucs1002_power.c #  define UCS1002_ILIM_SW_MASK		GENMASK(3, 0)
GENMASK            17 drivers/pwm/pwm-atmel-hlcdc.c #define ATMEL_HLCDC_PWMCVAL_MASK	GENMASK(15, 8)
GENMASK            20 drivers/pwm/pwm-atmel-hlcdc.c #define ATMEL_HLCDC_PWMPS_MASK		GENMASK(2, 0)
GENMASK            32 drivers/pwm/pwm-hibvt.c #define PWM_PERIOD_MASK     GENMASK(31, 0)
GENMASK            33 drivers/pwm/pwm-hibvt.c #define PWM_DUTY_MASK       GENMASK(31, 0)
GENMASK            37 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_PARAM_CHAN			GENMASK(7, 0)
GENMASK            39 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_SC_PS			GENMASK(2, 0)
GENMASK            40 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_SC_CMOD			GENMASK(4, 3)
GENMASK            53 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_CnSC_ELS	GENMASK(3, 2)
GENMASK            59 drivers/pwm/pwm-imx-tpm.c #define PWM_IMX_TPM_MOD_MOD	GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
GENMASK            31 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_FWM			GENMASK(27, 26)
GENMASK            39 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_POUTC			GENMASK(19, 18)
GENMASK            44 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_CLKSRC		GENMASK(17, 16)
GENMASK            50 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_PRESCALER		GENMASK(15, 4)
GENMASK            54 drivers/pwm/pwm-imx27.c #define MX3_PWMCR_REPEAT		GENMASK(2, 1)
GENMASK            67 drivers/pwm/pwm-imx27.c #define MX3_PWMSR_FIFOAV		GENMASK(2, 0)
GENMASK            48 drivers/pwm/pwm-meson.c #define PWM_LOW_MASK		GENMASK(15, 0)
GENMASK            49 drivers/pwm/pwm-meson.c #define PWM_HIGH_MASK		GENMASK(31, 16)
GENMASK            29 drivers/pwm/pwm-sifive.c #define PWM_SIFIVE_PWMCFG_SCALE		GENMASK(3, 0)
GENMASK            19 drivers/pwm/pwm-sprd.c #define SPRD_PWM_MOD_MAX	GENMASK(7, 0)
GENMASK            20 drivers/pwm/pwm-sprd.c #define SPRD_PWM_DUTY_MSK	GENMASK(15, 0)
GENMASK            21 drivers/pwm/pwm-sprd.c #define SPRD_PWM_PRESCALE_MSK	GENMASK(7, 0)
GENMASK            30 drivers/pwm/pwm-sun4i.c #define PWM_PRESCAL_MASK	GENMASK(3, 0)
GENMASK            44 drivers/pwm/pwm-sun4i.c #define PWM_PRD_MASK		GENMASK(15, 0)
GENMASK            46 drivers/pwm/pwm-sun4i.c #define PWM_DTY_MASK		GENMASK(15, 0)
GENMASK            18 drivers/pwm/pwm-zx.c #define ZX_PWM_CLKDIV_MASK	GENMASK(11, 2)
GENMASK            30 drivers/regulator/axp20x-regulator.c #define AXP20X_GPIO0_FUNC_MASK		GENMASK(3, 0)
GENMASK            31 drivers/regulator/axp20x-regulator.c #define AXP20X_GPIO1_FUNC_MASK		GENMASK(3, 0)
GENMASK            39 drivers/regulator/axp20x-regulator.c #define AXP20X_FREQ_DCDC_MASK		GENMASK(3, 0)
GENMASK            43 drivers/regulator/axp20x-regulator.c #define AXP20X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
GENMASK            44 drivers/regulator/axp20x-regulator.c #define AXP20X_DCDC3_V_OUT_MASK		GENMASK(7, 0)
GENMASK            45 drivers/regulator/axp20x-regulator.c #define AXP20X_LDO24_V_OUT_MASK		GENMASK(7, 4)
GENMASK            46 drivers/regulator/axp20x-regulator.c #define AXP20X_LDO3_V_OUT_MASK		GENMASK(6, 0)
GENMASK            47 drivers/regulator/axp20x-regulator.c #define AXP20X_LDO5_V_OUT_MASK		GENMASK(7, 4)
GENMASK            96 drivers/regulator/axp20x-regulator.c #define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
GENMASK            97 drivers/regulator/axp20x-regulator.c #define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
GENMASK            98 drivers/regulator/axp20x-regulator.c #define AXP22X_DCDC3_V_OUT_MASK		GENMASK(5, 0)
GENMASK            99 drivers/regulator/axp20x-regulator.c #define AXP22X_DCDC4_V_OUT_MASK		GENMASK(5, 0)
GENMASK           100 drivers/regulator/axp20x-regulator.c #define AXP22X_DCDC5_V_OUT_MASK		GENMASK(4, 0)
GENMASK           101 drivers/regulator/axp20x-regulator.c #define AXP22X_DC5LDO_V_OUT_MASK	GENMASK(2, 0)
GENMASK           102 drivers/regulator/axp20x-regulator.c #define AXP22X_ALDO1_V_OUT_MASK		GENMASK(4, 0)
GENMASK           103 drivers/regulator/axp20x-regulator.c #define AXP22X_ALDO2_V_OUT_MASK		GENMASK(4, 0)
GENMASK           104 drivers/regulator/axp20x-regulator.c #define AXP22X_ALDO3_V_OUT_MASK		GENMASK(4, 0)
GENMASK           105 drivers/regulator/axp20x-regulator.c #define AXP22X_DLDO1_V_OUT_MASK		GENMASK(4, 0)
GENMASK           106 drivers/regulator/axp20x-regulator.c #define AXP22X_DLDO2_V_OUT_MASK		GENMASK(4, 0)
GENMASK           107 drivers/regulator/axp20x-regulator.c #define AXP22X_DLDO3_V_OUT_MASK		GENMASK(4, 0)
GENMASK           108 drivers/regulator/axp20x-regulator.c #define AXP22X_DLDO4_V_OUT_MASK		GENMASK(4, 0)
GENMASK           109 drivers/regulator/axp20x-regulator.c #define AXP22X_ELDO1_V_OUT_MASK		GENMASK(4, 0)
GENMASK           110 drivers/regulator/axp20x-regulator.c #define AXP22X_ELDO2_V_OUT_MASK		GENMASK(4, 0)
GENMASK           111 drivers/regulator/axp20x-regulator.c #define AXP22X_ELDO3_V_OUT_MASK		GENMASK(4, 0)
GENMASK           112 drivers/regulator/axp20x-regulator.c #define AXP22X_LDO_IO0_V_OUT_MASK	GENMASK(4, 0)
GENMASK           113 drivers/regulator/axp20x-regulator.c #define AXP22X_LDO_IO1_V_OUT_MASK	GENMASK(4, 0)
GENMASK           146 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC1_V_OUT_MASK		GENMASK(4, 0)
GENMASK           147 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC2_V_OUT_MASK		GENMASK(6, 0)
GENMASK           148 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC3_V_OUT_MASK		GENMASK(6, 0)
GENMASK           149 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC4_V_OUT_MASK		GENMASK(6, 0)
GENMASK           150 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC5_V_OUT_MASK		GENMASK(6, 0)
GENMASK           151 drivers/regulator/axp20x-regulator.c #define AXP803_DCDC6_V_OUT_MASK		GENMASK(6, 0)
GENMASK           153 drivers/regulator/axp20x-regulator.c #define AXP803_FLDO1_V_OUT_MASK		GENMASK(3, 0)
GENMASK           154 drivers/regulator/axp20x-regulator.c #define AXP803_FLDO2_V_OUT_MASK		GENMASK(3, 0)
GENMASK           199 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCA_V_CTRL_MASK	GENMASK(6, 0)
GENMASK           200 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCB_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           201 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCC_V_CTRL_MASK	GENMASK(6, 0)
GENMASK           202 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCD_V_CTRL_MASK	GENMASK(5, 0)
GENMASK           203 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCE_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           204 drivers/regulator/axp20x-regulator.c #define AXP806_ALDO1_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           205 drivers/regulator/axp20x-regulator.c #define AXP806_ALDO2_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           206 drivers/regulator/axp20x-regulator.c #define AXP806_ALDO3_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           207 drivers/regulator/axp20x-regulator.c #define AXP806_BLDO1_V_CTRL_MASK	GENMASK(3, 0)
GENMASK           208 drivers/regulator/axp20x-regulator.c #define AXP806_BLDO2_V_CTRL_MASK	GENMASK(3, 0)
GENMASK           209 drivers/regulator/axp20x-regulator.c #define AXP806_BLDO3_V_CTRL_MASK	GENMASK(3, 0)
GENMASK           210 drivers/regulator/axp20x-regulator.c #define AXP806_BLDO4_V_CTRL_MASK	GENMASK(3, 0)
GENMASK           211 drivers/regulator/axp20x-regulator.c #define AXP806_CLDO1_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           212 drivers/regulator/axp20x-regulator.c #define AXP806_CLDO2_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           213 drivers/regulator/axp20x-regulator.c #define AXP806_CLDO3_V_CTRL_MASK	GENMASK(4, 0)
GENMASK           234 drivers/regulator/axp20x-regulator.c #define AXP806_DCDCABC_POLYPHASE_MASK	GENMASK(7, 6)
GENMASK           268 drivers/regulator/axp20x-regulator.c #define AXP813_DCDC7_V_OUT_MASK		GENMASK(6, 0)
GENMASK            50 drivers/regulator/bcm590xx-regulator.c #define BCM590XX_LDO_VSEL_MASK	GENMASK(5, 3)
GENMASK            51 drivers/regulator/bcm590xx-regulator.c #define BCM590XX_SR_VSEL_MASK	GENMASK(5, 0)
GENMASK            15 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_EN_CTRL_MASK		GENMASK(3, 0)
GENMASK            18 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_ENABLED		GENMASK(2, 1)
GENMASK            21 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_V_LDO_MASK		GENMASK(6, 0)
GENMASK            22 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_V_SBB_MASK		GENMASK(5, 0)
GENMASK            23 drivers/regulator/max77650-regulator.c #define MAX77651_REGULATOR_V_SBB1_MASK		GENMASK(5, 2)
GENMASK            24 drivers/regulator/max77650-regulator.c #define MAX77651_REGULATOR_V_SBB1_RANGE_MASK	GENMASK(1, 0)
GENMASK            30 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_CURR_LIM_MASK	GENMASK(7, 6)
GENMASK            83 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_CPU0_VOL_MASK	GENMASK(8, 0)
GENMASK            84 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_CPU1_VOL_MASK	GENMASK(8, 0)
GENMASK            85 drivers/regulator/sc2731-regulator.c #define SC2731_DCDC_RF_VOL_MASK		GENMASK(8, 0)
GENMASK            86 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMA0_VOL_MASK	GENMASK(7, 0)
GENMASK            87 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMA1_VOL_MASK	GENMASK(7, 0)
GENMASK            88 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMMOT_VOL_MASK	GENMASK(7, 0)
GENMASK            89 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_VLDO_VOL_MASK	GENMASK(7, 0)
GENMASK            90 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_EMMCCORE_VOL_MASK	GENMASK(7, 0)
GENMASK            91 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SDCORE_VOL_MASK	GENMASK(7, 0)
GENMASK            92 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SDIO_VOL_MASK	GENMASK(7, 0)
GENMASK            93 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_WIFIPA_VOL_MASK	GENMASK(7, 0)
GENMASK            94 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_USB33_VOL_MASK	GENMASK(7, 0)
GENMASK            95 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMD0_VOL_MASK	GENMASK(6, 0)
GENMASK            96 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMD1_VOL_MASK	GENMASK(6, 0)
GENMASK            97 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CON_VOL_MASK		GENMASK(6, 0)
GENMASK            98 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_CAMIO_VOL_MASK	GENMASK(6, 0)
GENMASK            99 drivers/regulator/sc2731-regulator.c #define SC2731_LDO_SRAM_VOL_MASK	GENMASK(6, 0)
GENMASK            23 drivers/regulator/stm32-vrefbuf.c #define STM32_VRS			GENMASK(6, 4)
GENMASK            36 drivers/remoteproc/qcom_q6v5_adsp.c #define EVB_MASK			GENMASK(27, 4)
GENMASK            54 drivers/remoteproc/qcom_q6v5_wcss.c #define Q6SS_XO_CBCR		GENMASK(5, 3)
GENMASK            67 drivers/remoteproc/qcom_q6v5_wcss.c #define SSCAON_BUS_MUX_MASK	GENMASK(18, 16)
GENMASK            49 drivers/remoteproc/qcom_wcnss.c #define WCNSS_PMU_XO_MODE_MASK		GENMASK(2, 1)
GENMASK           264 drivers/remoteproc/st_remoteproc.c 	.bootaddr_mask = GENMASK(28, 1),
GENMASK           270 drivers/remoteproc/st_remoteproc.c 	.bootaddr_mask = GENMASK(31, 6),
GENMASK            36 drivers/remoteproc/st_slim_rproc.c #define SLIM_REV_ID_MIN_MASK		GENMASK(15, 8)
GENMASK            38 drivers/remoteproc/st_slim_rproc.c #define SLIM_REV_ID_MAJ_MASK		GENMASK(23, 16)
GENMASK            47 drivers/reset/reset-hsdk.c #define CGU_IP_SW_RESET_DELAY_MASK	GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
GENMASK            18 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_CTRL1_MASK		GENMASK(7, 0)
GENMASK            65 drivers/rtc/rtc-ab-eoz9.c #define ABEOZ9_REG_EEPROM_MASK		GENMASK(8, 0)
GENMASK            37 drivers/rtc/rtc-ac100.c #define AC100_RTC_SEC_MASK	GENMASK(6, 0)
GENMASK            38 drivers/rtc/rtc-ac100.c #define AC100_RTC_MIN_MASK	GENMASK(6, 0)
GENMASK            39 drivers/rtc/rtc-ac100.c #define AC100_RTC_HOU_MASK	GENMASK(5, 0)
GENMASK            40 drivers/rtc/rtc-ac100.c #define AC100_RTC_WEE_MASK	GENMASK(2, 0)
GENMASK            41 drivers/rtc/rtc-ac100.c #define AC100_RTC_DAY_MASK	GENMASK(5, 0)
GENMASK            42 drivers/rtc/rtc-ac100.c #define AC100_RTC_MON_MASK	GENMASK(4, 0)
GENMASK            43 drivers/rtc/rtc-ac100.c #define AC100_RTC_YEA_MASK	GENMASK(7, 0)
GENMASK            50 drivers/rtc/rtc-ac100.c #define AC100_ALM_SEC_MASK	GENMASK(6, 0)
GENMASK            51 drivers/rtc/rtc-ac100.c #define AC100_ALM_MIN_MASK	GENMASK(6, 0)
GENMASK            52 drivers/rtc/rtc-ac100.c #define AC100_ALM_HOU_MASK	GENMASK(5, 0)
GENMASK            53 drivers/rtc/rtc-ac100.c #define AC100_ALM_WEE_MASK	GENMASK(2, 0)
GENMASK            54 drivers/rtc/rtc-ac100.c #define AC100_ALM_DAY_MASK	GENMASK(5, 0)
GENMASK            55 drivers/rtc/rtc-ac100.c #define AC100_ALM_MON_MASK	GENMASK(4, 0)
GENMASK            56 drivers/rtc/rtc-ac100.c #define AC100_ALM_YEA_MASK	GENMASK(7, 0)
GENMASK            62 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_H		GENMASK(7, 0)
GENMASK            63 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_S		GENMASK(14, 8)
GENMASK            64 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_M		GENMASK(22, 16)
GENMASK            65 drivers/rtc/rtc-cadence.c #define CDNS_RTC_TIME_HR	GENMASK(29, 24)
GENMASK            70 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_DAY	GENMASK(2, 0)
GENMASK            71 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_M		GENMASK(7, 3)
GENMASK            72 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_D		GENMASK(13, 8)
GENMASK            73 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_Y		GENMASK(23, 16)
GENMASK            74 drivers/rtc/rtc-cadence.c #define CDNS_RTC_CAL_C		GENMASK(29, 24)
GENMASK           145 drivers/rtc/rtc-ds1307.c #	define M41TXX_M_CALIBRATION	GENMASK(4, 0)
GENMASK            34 drivers/rtc/rtc-meson.c 	#define RTC_ADDR0_DATA			GENMASK(31, 24)
GENMASK            44 drivers/rtc/rtc-meson.c 	#define RTC_REG4_STATIC_VALUE		GENMASK(7, 0)
GENMASK            43 drivers/rtc/rtc-mt7622.c #define	RTC_DEBNCE_MASK		GENMASK(2, 0)
GENMASK            56 drivers/rtc/rtc-mt7622.c #define	RTC_AL_ALL		GENMASK(7, 0)
GENMASK            98 drivers/rtc/rtc-pcf2123.c #define OFFSET_MASK		GENMASK(6, 0)	/* Offset value */
GENMASK            98 drivers/rtc/rtc-pcf85363.c #define PIN_IO_INTAPM	GENMASK(1, 0)
GENMASK            75 drivers/rtc/rtc-rv3028.c #define RV3028_BACKUP_TCR_MASK		GENMASK(1,0)
GENMASK            62 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_INT_MASK		GENMASK(15, 0)
GENMASK            78 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_SEC_MASK		GENMASK(5, 0)
GENMASK            79 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_MIN_MASK		GENMASK(5, 0)
GENMASK            80 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_HOUR_MASK		GENMASK(4, 0)
GENMASK            81 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_DAY_MASK		GENMASK(15, 0)
GENMASK            84 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_ALMLOCK_MASK		GENMASK(7, 0)
GENMASK            94 drivers/rtc/rtc-sc27xx.c #define SPRD_RTC_POWER_STS_CLEAR	GENMASK(7, 0)
GENMASK            22 drivers/rtc/rtc-stm32.c #define STM32_RTC_TR_SEC		GENMASK(6, 0)
GENMASK            24 drivers/rtc/rtc-stm32.c #define STM32_RTC_TR_MIN		GENMASK(14, 8)
GENMASK            26 drivers/rtc/rtc-stm32.c #define STM32_RTC_TR_HOUR		GENMASK(21, 16)
GENMASK            30 drivers/rtc/rtc-stm32.c #define STM32_RTC_DR_DATE		GENMASK(5, 0)
GENMASK            32 drivers/rtc/rtc-stm32.c #define STM32_RTC_DR_MONTH		GENMASK(12, 8)
GENMASK            34 drivers/rtc/rtc-stm32.c #define STM32_RTC_DR_WDAY		GENMASK(15, 13)
GENMASK            36 drivers/rtc/rtc-stm32.c #define STM32_RTC_DR_YEAR		GENMASK(23, 16)
GENMASK            53 drivers/rtc/rtc-stm32.c #define STM32_RTC_PRER_PRED_S		GENMASK(14, 0)
GENMASK            55 drivers/rtc/rtc-stm32.c #define STM32_RTC_PRER_PRED_A		GENMASK(22, 16)
GENMASK            59 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_SEC		GENMASK(6, 0)
GENMASK            62 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_MIN		GENMASK(14, 8)
GENMASK            65 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_HOUR		GENMASK(21, 16)
GENMASK            69 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_DATE		GENMASK(29, 24)
GENMASK            72 drivers/rtc/rtc-stm32.c #define STM32_RTC_ALRMXR_WDAY		GENMASK(27, 24)
GENMASK            80 drivers/rtc/rtc-stm32.c #define STM32_RTC_VERR_MINREV		GENMASK(3, 0)
GENMASK            82 drivers/rtc/rtc-stm32.c #define STM32_RTC_VERR_MAJREV		GENMASK(7, 4)
GENMASK            41 drivers/rtc/rtc-sun6i.c #define SUN6I_LOSC_CTRL_ACC_MASK		GENMASK(9, 7)
GENMASK           170 drivers/rtc/rtc-sun6i.c 		val &= GENMASK(4, 0);
GENMASK            91 drivers/scsi/ufs/ufs-qcom.h #define TEST_BUS_SEL		GENMASK(22, 19)
GENMASK           124 drivers/scsi/ufs/ufshci.h #define UFSHCI_AHIBERN8_TIMER_MASK		GENMASK(9, 0)
GENMASK           125 drivers/scsi/ufs/ufshci.h #define UFSHCI_AHIBERN8_SCALE_MASK		GENMASK(12, 10)
GENMASK            29 drivers/slimbus/slimbus.h #define SLIM_MSG_MT_MASK	GENMASK(2, 0)
GENMASK            31 drivers/slimbus/slimbus.h #define SLIM_MSG_RL_MASK	GENMASK(4, 0)
GENMASK            33 drivers/slimbus/slimbus.h #define SLIM_MSG_MC_MASK	GENMASK(6, 0)
GENMASK            35 drivers/slimbus/slimbus.h #define SLIM_MSG_DT_MASK	GENMASK(1, 0)
GENMASK            21 drivers/soc/amlogic/meson-clk-measure.c #define MSR_DURATION		GENMASK(15, 0)
GENMASK            26 drivers/soc/amlogic/meson-clk-measure.c #define MSR_CLK_SRC		GENMASK(26, 20)
GENMASK            29 drivers/soc/amlogic/meson-clk-measure.c #define MSR_VAL_MASK		GENMASK(15, 0)
GENMASK            93 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(1, 0) },				\
GENMASK            94 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(3, 2) },				\
GENMASK            95 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(5, 4) },				\
GENMASK            96 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(7, 6) },				\
GENMASK            97 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(9, 8) },				\
GENMASK            98 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(11, 10) },				\
GENMASK            99 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(13, 12) },				\
GENMASK           100 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(15, 14) },				\
GENMASK           101 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(17, 16) },				\
GENMASK           102 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(19, 18) },				\
GENMASK           103 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(21, 20) },				\
GENMASK           104 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(23, 22) },				\
GENMASK           105 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(25, 24) },				\
GENMASK           106 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(27, 26) },				\
GENMASK           107 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(29, 28) },				\
GENMASK           108 drivers/soc/amlogic/meson-ee-pwrc.c 	{ __reg, GENMASK(31, 30) }
GENMASK           128 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_MEM_PD_REG0, GENMASK(3, 2) },
GENMASK           136 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
GENMASK           137 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
GENMASK           138 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
GENMASK           139 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
GENMASK           149 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_MEM_PD_REG0, GENMASK(31, 30) },
GENMASK           153 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_MEM_PD_REG0, GENMASK(29, 26) },
GENMASK           157 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_MEM_PD_REG0, GENMASK(25, 18) },
GENMASK           161 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
GENMASK           162 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
GENMASK           163 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
GENMASK           164 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
GENMASK           165 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
GENMASK           166 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
GENMASK           167 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
GENMASK           168 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
GENMASK           169 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
GENMASK           170 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
GENMASK           171 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
GENMASK           172 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
GENMASK           173 drivers/soc/amlogic/meson-ee-pwrc.c 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
GENMASK            22 drivers/soc/amlogic/meson-gx-socinfo.c #define SOCINFO_MAJOR	GENMASK(31, 24)
GENMASK            23 drivers/soc/amlogic/meson-gx-socinfo.c #define SOCINFO_PACK	GENMASK(23, 16)
GENMASK            24 drivers/soc/amlogic/meson-gx-socinfo.c #define SOCINFO_MINOR	GENMASK(15, 8)
GENMASK            25 drivers/soc/amlogic/meson-gx-socinfo.c #define SOCINFO_MISC	GENMASK(7, 0)
GENMASK            41 drivers/soc/aspeed/aspeed-lpc-snoop.c #define SNPWADR_CH0_MASK	GENMASK(15, 0)
GENMASK            43 drivers/soc/aspeed/aspeed-lpc-snoop.c #define SNPWADR_CH1_MASK	GENMASK(31, 16)
GENMASK            46 drivers/soc/aspeed/aspeed-lpc-snoop.c #define SNPWDR_CH0_MASK		GENMASK(7, 0)
GENMASK            48 drivers/soc/aspeed/aspeed-lpc-snoop.c #define SNPWDR_CH1_MASK		GENMASK(15, 8)
GENMASK            20 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_BURST_MASK			GENMASK(21, 16)
GENMASK            23 drivers/soc/gemini/soc-gemini.c #define GEMINI_ARB1_PRIO_MASK			GENMASK(9, 0)
GENMASK           492 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           501 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           502 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           510 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           511 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           519 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           520 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(13, 12),
GENMASK           528 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           536 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           537 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           545 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           546 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           567 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           568 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           576 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           577 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           585 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           586 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           594 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           595 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(13, 12),
GENMASK           603 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           604 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           612 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(10, 8),
GENMASK           613 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(14, 12),
GENMASK           621 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(10, 8),
GENMASK           622 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(14, 12),
GENMASK           630 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           631 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(16, 16),
GENMASK           640 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           641 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(16, 16),
GENMASK           649 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           650 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(16, 16),
GENMASK           658 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           659 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(16, 16),
GENMASK           683 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           684 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           691 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           692 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           699 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(9, 8),
GENMASK           700 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(13, 12),
GENMASK           707 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           708 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           716 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           717 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           732 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(8, 8),
GENMASK           733 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           757 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           758 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           767 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           768 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           777 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           778 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           813 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           814 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           822 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           823 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           845 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           846 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           853 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           854 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           861 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           862 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(13, 12),
GENMASK           869 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           870 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(12, 12),
GENMASK           879 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           880 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           887 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           888 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           895 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           896 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(15, 12),
GENMASK           904 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           912 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(11, 8),
GENMASK           913 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(13, 12),
GENMASK           920 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_bits = GENMASK(13, 8),
GENMASK           921 drivers/soc/mediatek/mtk-scpsys.c 		.sram_pdn_ack_bits = GENMASK(21, 16),
GENMASK            30 drivers/soc/qcom/llcc-slice.c #define ATTR0_RES_WAYS_MASK           GENMASK(11, 0)
GENMASK            31 drivers/soc/qcom/llcc-slice.c #define ATTR0_BONUS_WAYS_MASK         GENMASK(27, 16)
GENMASK            38 drivers/soc/qcom/llcc-slice.c #define LLCC_LB_CNT_MASK              GENMASK(31, 28)
GENMASK           136 drivers/soc/qcom/qcom-geni-se.c #define DEFAULT_IO_OUTPUT_CTRL_MSK	GENMASK(6, 0)
GENMASK           148 drivers/soc/qcom/qcom-geni-se.c #define DEFAULT_CGC_EN			GENMASK(6, 0)
GENMASK           169 drivers/soc/qcom/qcom-geni-se.c #define RX_DMA_IRQ_DELAY_MSK		GENMASK(8, 6)
GENMASK            36 drivers/soc/qcom/qcom_aoss.c #define QMP_STATE_UP			GENMASK(15, 0)
GENMASK            37 drivers/soc/qcom/qcom_aoss.c #define QMP_STATE_DOWN			GENMASK(31, 16)
GENMASK           143 drivers/soc/sunxi/sunxi_sram.c 			val &= GENMASK(sram_data->width - 1, 0);
GENMASK           250 drivers/soc/sunxi/sunxi_sram.c 	mask = GENMASK(sram_data->offset + sram_data->width - 1,
GENMASK            40 drivers/soc/ti/knav_dma.c #define DMA_PRIO_MASK		GENMASK(3, 0)
GENMASK            43 drivers/soc/ti/knav_dma.c #define DMA_RX_TIMEOUT_MASK	GENMASK(16, 0)
GENMASK            51 drivers/soc/ti/knav_dma.c #define CHAN_SOP_OFF_MASK	GENMASK(9, 0)
GENMASK            53 drivers/soc/ti/knav_dma.c #define DESC_TYPE_MASK		GENMASK(2, 0)
GENMASK            60 drivers/soc/ti/knav_dma.c #define CHAN_QNUM_MASK		GENMASK(14, 0)
GENMASK            62 drivers/soundwire/bus.c 	*bus->assigned = ~GENMASK(SDW_BROADCAST_DEV_NUM, SDW_ENUM_DEV_NUM);
GENMASK           508 drivers/soundwire/bus.c 	id->sdw_version = (addr >> 44) & GENMASK(3, 0);
GENMASK           509 drivers/soundwire/bus.c 	id->unique_id = (addr >> 40) & GENMASK(3, 0);
GENMASK           510 drivers/soundwire/bus.c 	id->mfg_id = (addr >> 24) & GENMASK(15, 0);
GENMASK           511 drivers/soundwire/bus.c 	id->part_id = (addr >> 8) & GENMASK(15, 0);
GENMASK           512 drivers/soundwire/bus.c 	id->class_id = addr & GENMASK(7, 0);
GENMASK            29 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_MCMD_RETRY		GENMASK(27, 24)
GENMASK            30 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_MPREQ_DELAY		GENMASK(20, 16)
GENMASK            36 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONFIG_OP			GENMASK(2, 0)
GENMASK            41 drivers/soundwire/cadence_master.c #define CDNS_MCP_CONTROL_RST_DELAY		GENMASK(10, 8)
GENMASK            55 drivers/soundwire/cadence_master.c #define CDNS_MCP_FRAME_SHAPE_COL_MASK		GENMASK(2, 0)
GENMASK            66 drivers/soundwire/cadence_master.c #define CDNS_MCP_CLK_MCLKD_MASK		GENMASK(7, 0)
GENMASK            82 drivers/soundwire/cadence_master.c #define CDNS_MCP_INT_SLAVE_MASK			GENMASK(15, 12)
GENMASK            96 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_STAT_MASK		GENMASK(1, 0)
GENMASK           104 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_STATUS_BITS		GENMASK(3, 0)
GENMASK           110 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTMASK0_MASK		GENMASK(31, 0)
GENMASK           111 drivers/soundwire/cadence_master.c #define CDNS_MCP_SLAVE_INTMASK1_MASK		GENMASK(15, 0)
GENMASK           118 drivers/soundwire/cadence_master.c #define CDNS_MCP_RX_FIFO_AVAIL			GENMASK(5, 0)
GENMASK           126 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_COMMAND			GENMASK(30, 28)
GENMASK           127 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_DEV_ADDR			GENMASK(27, 24)
GENMASK           128 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_REG_ADDR_H			GENMASK(23, 16)
GENMASK           129 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_REG_ADDR_L			GENMASK(15, 8)
GENMASK           130 drivers/soundwire/cadence_master.c #define CDNS_MCP_CMD_REG_DATA			GENMASK(7, 0)
GENMASK           135 drivers/soundwire/cadence_master.c #define CDNS_MCP_RESP_RDATA			GENMASK(15, 8)
GENMASK           156 drivers/soundwire/cadence_master.c #define CDNS_DPN_CONFIG_BGC			GENMASK(17, 16)
GENMASK           157 drivers/soundwire/cadence_master.c #define CDNS_DPN_CONFIG_WL			GENMASK(12, 8)
GENMASK           158 drivers/soundwire/cadence_master.c #define CDNS_DPN_CONFIG_PORT_DAT		GENMASK(3, 2)
GENMASK           159 drivers/soundwire/cadence_master.c #define CDNS_DPN_CONFIG_PORT_FLOW		GENMASK(1, 0)
GENMASK           161 drivers/soundwire/cadence_master.c #define CDNS_DPN_SAMPLE_CTRL_SI			GENMASK(15, 0)
GENMASK           163 drivers/soundwire/cadence_master.c #define CDNS_DPN_OFFSET_CTRL_1			GENMASK(7, 0)
GENMASK           164 drivers/soundwire/cadence_master.c #define CDNS_DPN_OFFSET_CTRL_2			GENMASK(15, 8)
GENMASK           166 drivers/soundwire/cadence_master.c #define CDNS_DPN_HCTRL_HSTOP			GENMASK(3, 0)
GENMASK           167 drivers/soundwire/cadence_master.c #define CDNS_DPN_HCTRL_HSTART			GENMASK(7, 4)
GENMASK           168 drivers/soundwire/cadence_master.c #define CDNS_DPN_HCTRL_LCTRL			GENMASK(10, 8)
GENMASK           179 drivers/soundwire/cadence_master.c #define CDNS_PDI_CONFIG_CHANNEL			GENMASK(15, 8)
GENMASK           180 drivers/soundwire/cadence_master.c #define CDNS_PDI_CONFIG_PORT			GENMASK(4, 0)
GENMASK            49 drivers/soundwire/intel.c #define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
GENMASK            51 drivers/soundwire/intel.c #define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
GENMASK            55 drivers/soundwire/intel.c #define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
GENMASK            56 drivers/soundwire/intel.c #define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
GENMASK            57 drivers/soundwire/intel.c #define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)
GENMASK            59 drivers/soundwire/intel.c #define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
GENMASK            60 drivers/soundwire/intel.c #define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
GENMASK            61 drivers/soundwire/intel.c #define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
GENMASK            64 drivers/soundwire/intel.c #define SDW_SHIM_PDMSCAP_ISS		GENMASK(3, 0)
GENMASK            65 drivers/soundwire/intel.c #define SDW_SHIM_PDMSCAP_OSS		GENMASK(7, 4)
GENMASK            66 drivers/soundwire/intel.c #define SDW_SHIM_PDMSCAP_BSS		GENMASK(12, 8)
GENMASK            67 drivers/soundwire/intel.c #define SDW_SHIM_PDMSCAP_CPSS		GENMASK(15, 13)
GENMASK            81 drivers/soundwire/intel.c #define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)
GENMASK            91 drivers/soundwire/intel.c #define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
GENMASK            92 drivers/soundwire/intel.c #define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)
GENMASK           206 drivers/soundwire/intel.c 	links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
GENMASK            88 drivers/soundwire/intel_init.c 	caps &= GENMASK(2, 0);
GENMASK           190 drivers/soundwire/intel_init.c 	if ((adr & GENMASK(31, 28)) >> 28 != SDW_LINK_TYPE)
GENMASK           174 drivers/soundwire/mipi_disco.c 	addr &= GENMASK(14, 1);
GENMASK            99 drivers/soundwire/slave.c 		link_id = (addr >> 48) & GENMASK(3, 0);
GENMASK            63 drivers/spi/atmel-quadspi.c #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
GENMASK            67 drivers/spi/atmel-quadspi.c #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
GENMASK            69 drivers/spi/atmel-quadspi.c #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
GENMASK            71 drivers/spi/atmel-quadspi.c #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
GENMASK            89 drivers/spi/atmel-quadspi.c #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
GENMASK            91 drivers/spi/atmel-quadspi.c #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
GENMASK            95 drivers/spi/atmel-quadspi.c #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
GENMASK            97 drivers/spi/atmel-quadspi.c #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
GENMASK           101 drivers/spi/atmel-quadspi.c #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
GENMASK           113 drivers/spi/atmel-quadspi.c #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
GENMASK           122 drivers/spi/atmel-quadspi.c #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
GENMASK           132 drivers/spi/atmel-quadspi.c #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
GENMASK           137 drivers/spi/atmel-quadspi.c #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
GENMASK            42 drivers/spi/spi-at91-usart.c #define US_MR_CHRL		GENMASK(7, 6)
GENMASK           125 drivers/spi/spi-bcm-qspi.c #define ADDR_4MB_MASK				GENMASK(22, 0)
GENMASK           178 drivers/spi/spi-dln2.c 	u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
GENMASK            37 drivers/spi/spi-dw-mmio.c #define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
GENMASK            38 drivers/spi/spi-fsl-dspi.c #define SPI_TCR_GET_TCNT(x)		(((x) & GENMASK(31, 16)) >> 16)
GENMASK            40 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR(x)			(0x0c + (((x) & GENMASK(1, 0)) * 4))
GENMASK            41 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_FMSZ(x)		(((x) << 27) & GENMASK(30, 27))
GENMASK            45 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_PCSSCK(x)		(((x) << 22) & GENMASK(23, 22))
GENMASK            46 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_PASC(x)		(((x) << 20) & GENMASK(21, 20))
GENMASK            47 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_PDT(x)			(((x) << 18) & GENMASK(19, 18))
GENMASK            48 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_PBR(x)			(((x) << 16) & GENMASK(17, 16))
GENMASK            49 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_CSSCK(x)		(((x) << 12) & GENMASK(15, 12))
GENMASK            50 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_ASC(x)			(((x) << 8) & GENMASK(11, 8))
GENMASK            51 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_DT(x)			(((x) << 4) & GENMASK(7, 4))
GENMASK            52 drivers/spi/spi-fsl-dspi.c #define SPI_CTAR_BR(x)			((x) & GENMASK(3, 0))
GENMASK            85 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_CTAS(x)		(((x) << 12 & GENMASK(14, 12)))
GENMASK            88 drivers/spi/spi-fsl-dspi.c #define SPI_PUSHR_CMD_PCS(x)		(BIT(x) & GENMASK(5, 0))
GENMASK           103 drivers/spi/spi-fsl-dspi.c #define SPI_CTARE(x)			(0x11c + (((x) & GENMASK(1, 0)) * 4))
GENMASK            54 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_RESERVED_MASK	GENMASK(19, 16)
GENMASK            59 drivers/spi/spi-fsl-qspi.c #define QUADSPI_MCR_END_CFG_MASK	GENMASK(3, 2)
GENMASK            67 drivers/spi/spi-fsl-qspi.c #define QUADSPI_FLSHCR_TCSS_MASK	GENMASK(3, 0)
GENMASK            68 drivers/spi/spi-fsl-qspi.c #define QUADSPI_FLSHCR_TCSH_MASK	GENMASK(11, 8)
GENMASK            69 drivers/spi/spi-fsl-qspi.c #define QUADSPI_FLSHCR_TDH_MASK		GENMASK(17, 16)
GENMASK            74 drivers/spi/spi-fsl-qspi.c #define QUADSPI_BUF3CR_ADATSZ_MASK	GENMASK(15, 8)
GENMASK            85 drivers/spi/spi-fsl-qspi.c #define QUADSPI_SMPR_DDRSMP_MASK	GENMASK(18, 16)
GENMASK            91 drivers/spi/spi-fsl-qspi.c #define QUADSPI_RBCT_WMRK_MASK		GENMASK(4, 0)
GENMASK            23 drivers/spi/spi-geni-qcom.c #define LOOPBACK_MSK		GENMASK(1, 0)
GENMASK            29 drivers/spi/spi-geni-qcom.c #define CS_DEMUX_OUTPUT_INV_MSK	GENMASK(3, 0)
GENMASK            32 drivers/spi/spi-geni-qcom.c #define CS_DEMUX_OUTPUT_SEL	GENMASK(3, 0)
GENMASK            38 drivers/spi/spi-geni-qcom.c #define WORD_LEN_MSK		GENMASK(9, 0)
GENMASK            43 drivers/spi/spi-geni-qcom.c #define TRANS_LEN_MSK		GENMASK(23, 0)
GENMASK            48 drivers/spi/spi-geni-qcom.c #define SPI_INTER_WORDS_DELAY_MSK	GENMASK(9, 0)
GENMASK            49 drivers/spi/spi-geni-qcom.c #define SPI_CS_CLK_DELAY_MSK		GENMASK(19, 10)
GENMASK            54 drivers/spi/spi-meson-spicc.c #define SPICC_DRCTL_MASK	GENMASK(9, 8)
GENMASK            58 drivers/spi/spi-meson-spicc.c #define SPICC_CS_MASK		GENMASK(13, 12)
GENMASK            59 drivers/spi/spi-meson-spicc.c #define SPICC_DATARATE_MASK	GENMASK(18, 16)
GENMASK            64 drivers/spi/spi-meson-spicc.c #define SPICC_BITLENGTH_MASK	GENMASK(24, 19)
GENMASK            65 drivers/spi/spi-meson-spicc.c #define SPICC_BURSTLENGTH_MASK	GENMASK(31, 25)
GENMASK            79 drivers/spi/spi-meson-spicc.c #define SPICC_TXFIFO_THRESHOLD_MASK	GENMASK(5, 1)
GENMASK            80 drivers/spi/spi-meson-spicc.c #define SPICC_RXFIFO_THRESHOLD_MASK	GENMASK(10, 6)
GENMASK            81 drivers/spi/spi-meson-spicc.c #define SPICC_READ_BURST_MASK		GENMASK(14, 11)
GENMASK            82 drivers/spi/spi-meson-spicc.c #define SPICC_WRITE_BURST_MASK		GENMASK(18, 15)
GENMASK            84 drivers/spi/spi-meson-spicc.c #define SPICC_DMA_THREADID_MASK		GENMASK(25, 20)
GENMASK            85 drivers/spi/spi-meson-spicc.c #define SPICC_DMA_BURSTNUM_MASK		GENMASK(31, 26)
GENMASK            98 drivers/spi/spi-meson-spicc.c #define SPICC_PERIOD	GENMASK(14, 0)	/* Wait cycles */
GENMASK           101 drivers/spi/spi-meson-spicc.c #define SPICC_TXCNT_MASK	GENMASK(4, 0)	/* TX FIFO Counter */
GENMASK           102 drivers/spi/spi-meson-spicc.c #define SPICC_RXCNT_MASK	GENMASK(9, 5)	/* RX FIFO Counter */
GENMASK           103 drivers/spi/spi-meson-spicc.c #define SPICC_SMSTATUS_MASK	GENMASK(12, 10)	/* State Machine Status */
GENMASK           108 drivers/spi/spi-meson-spicc.c #define SPICC_DLYCTL_RO_MASK	GENMASK(20, 15) /* Delay Control Read-Only */
GENMASK           109 drivers/spi/spi-meson-spicc.c #define SPICC_DLYCTL_W1_MASK	GENMASK(21, 16) /* Delay Control Write-Only */
GENMASK           110 drivers/spi/spi-meson-spicc.c #define SPICC_FIFORST_RO_MASK	GENMASK(22, 21) /* FIFO Softreset Read-Only */
GENMASK           111 drivers/spi/spi-meson-spicc.c #define SPICC_FIFORST_W1_MASK	GENMASK(23, 22) /* FIFO Softreset Write-Only */
GENMASK            41 drivers/spi/spi-mt7621.c #define MASTER_RS_CLK_SEL	GENMASK(27, 16)
GENMASK            43 drivers/spi/spi-mt7621.c #define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
GENMASK            44 drivers/spi/spi-mxic.c #define INT_STS_ALL		GENMASK(31, 0)
GENMASK            42 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_R_BURST	GENMASK(25, 24)
GENMASK            43 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_ADDSIZ		GENMASK(17, 16)
GENMASK            44 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_DBW		GENMASK(13, 12)
GENMASK            45 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_ACCTYPE	GENMASK(9, 8)
GENMASK            46 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DRD_CFG_RDCMD		GENMASK(7, 0)
GENMASK            53 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_W_BURST	GENMASK(25, 24)
GENMASK            54 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_ADDSIZ		GENMASK(17, 16)
GENMASK            55 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_ABPCK		GENMASK(11, 10)
GENMASK            56 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_DBPCK		GENMASK(9, 8)
GENMASK            57 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_DWR_CFG_WRCMD		GENMASK(7, 0)
GENMASK            65 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_RDATSIZ	GENMASK(28, 24)
GENMASK            66 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_DBSIZ		GENMASK(23, 21)
GENMASK            67 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_WDATSIZ	GENMASK(20, 16)
GENMASK            68 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_ADDSIZ		GENMASK(13, 11)
GENMASK            70 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_RDBPCK		GENMASK(9, 8)
GENMASK            71 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_DBPCK		GENMASK(7, 6)
GENMASK            72 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_WDBPCK		GENMASK(5, 4)
GENMASK            73 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_ADBPCK		GENMASK(3, 2)
GENMASK            74 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CFG_CMBPCK		GENMASK(1, 0)
GENMASK            88 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CTS_DEV_NUM	GENMASK(9, 8)
GENMASK            93 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CMD_DUM3		GENMASK(31, 24)
GENMASK            94 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CMD_DUM2		GENMASK(23, 16)
GENMASK            95 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CMD_DUM1		GENMASK(15, 8)
GENMASK            96 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_CMD_CMD		GENMASK(7, 0)
GENMASK            99 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_ADDR_UMA_ADDR	GENMASK(31, 0)
GENMASK           100 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_ADDR_AB3		GENMASK(31, 24)
GENMASK           101 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_ADDR_AB2		GENMASK(23, 16)
GENMASK           102 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_ADDR_AB1		GENMASK(15, 8)
GENMASK           103 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_ADDR_AB0		GENMASK(7, 0)
GENMASK           106 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW0_WB3		GENMASK(31, 24)
GENMASK           107 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW0_WB2		GENMASK(23, 16)
GENMASK           108 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW0_WB1		GENMASK(15, 8)
GENMASK           109 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW0_WB0		GENMASK(7, 0)
GENMASK           112 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW1_WB7		GENMASK(31, 24)
GENMASK           113 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW1_WB6		GENMASK(23, 16)
GENMASK           114 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW1_WB5		GENMASK(15, 8)
GENMASK           115 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW1_WB4		GENMASK(7, 0)
GENMASK           118 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW2_WB11		GENMASK(31, 24)
GENMASK           119 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW2_WB10		GENMASK(23, 16)
GENMASK           120 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW2_WB9		GENMASK(15, 8)
GENMASK           121 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW2_WB8		GENMASK(7, 0)
GENMASK           124 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW3_WB15		GENMASK(31, 24)
GENMASK           125 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW3_WB14		GENMASK(23, 16)
GENMASK           126 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW3_WB13		GENMASK(15, 8)
GENMASK           127 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DW3_WB12		GENMASK(7, 0)
GENMASK           130 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR0_RB3		GENMASK(31, 24)
GENMASK           131 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR0_RB2		GENMASK(23, 16)
GENMASK           132 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR0_RB1		GENMASK(15, 8)
GENMASK           133 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR0_RB0		GENMASK(7, 0)
GENMASK           136 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR1_RB15		GENMASK(31, 24)
GENMASK           137 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR1_RB14		GENMASK(23, 16)
GENMASK           138 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR1_RB13		GENMASK(15, 8)
GENMASK           139 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR1_RB12		GENMASK(7, 0)
GENMASK           142 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR2_RB15		GENMASK(31, 24)
GENMASK           143 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR2_RB14		GENMASK(23, 16)
GENMASK           144 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR2_RB13		GENMASK(15, 8)
GENMASK           145 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR2_RB12		GENMASK(7, 0)
GENMASK           148 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR3_RB15		GENMASK(31, 24)
GENMASK           149 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR3_RB14		GENMASK(23, 16)
GENMASK           150 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR3_RB13		GENMASK(15, 8)
GENMASK           151 drivers/spi/spi-npcm-fiu.c #define NPCM_FIU_UMA_DR3_RB12		GENMASK(7, 0)
GENMASK            51 drivers/spi/spi-npcm-pspi.c #define NPCM_PSPI_CTL1_SCDV6_0	GENMASK(15, 9)
GENMASK            87 drivers/spi/spi-sh-msiof.c #define MDR1_SYNCMD_MASK   GENMASK(29, 28) /* SYNC Mode */
GENMASK            94 drivers/spi/spi-sh-msiof.c #define MDR1_FLD_MASK	   GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
GENMASK            99 drivers/spi/spi-sh-msiof.c #define TMDR1_SYNCCH_MASK  GENMASK(27, 26) /* Sync Signal Channel Select */
GENMASK           108 drivers/spi/spi-sh-msiof.c #define SCR_BRPS_MASK	GENMASK(12, 8) /* Prescaler Setting (1-32) */
GENMASK           110 drivers/spi/spi-sh-msiof.c #define SCR_BRDV_MASK	GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
GENMASK           119 drivers/spi/spi-sh-msiof.c #define CTR_TSCKIZ_MASK	GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
GENMASK           122 drivers/spi/spi-sh-msiof.c #define CTR_RSCKIZ_MASK	GENMASK(29, 28) /* Receive Clock Polarity Select */
GENMASK           127 drivers/spi/spi-sh-msiof.c #define CTR_TXDIZ_MASK	GENMASK(23, 22) /* Pin Output When TX is Disabled */
GENMASK           139 drivers/spi/spi-sh-msiof.c #define FCTR_TFWM_MASK	GENMASK(31, 29) /* Transmit FIFO Watermark */
GENMASK           148 drivers/spi/spi-sh-msiof.c #define FCTR_TFUA_MASK	GENMASK(26, 20) /* Transmit FIFO Usable Area */
GENMASK           151 drivers/spi/spi-sh-msiof.c #define FCTR_RFWM_MASK	GENMASK(15, 13) /* Receive FIFO Watermark */
GENMASK           160 drivers/spi/spi-sh-msiof.c #define FCTR_RFUA_MASK	GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
GENMASK            46 drivers/spi/spi-sprd-adi.c #define RD_VALUE_MASK			GENMASK(15, 0)
GENMASK            47 drivers/spi/spi-sprd-adi.c #define RD_ADDR_MASK			GENMASK(30, 16)
GENMASK            70 drivers/spi/spi-sprd-adi.c #define REG_ADDR_LOW_MASK		GENMASK(11, 0)
GENMASK           106 drivers/spi/spi-sprd-adi.c #define WDG_LOAD_MASK			GENMASK(15, 0)
GENMASK            55 drivers/spi/spi-sprd.c #define SPRD_SPI_CHNL_LEN_MASK		GENMASK(4, 0)
GENMASK            56 drivers/spi/spi-sprd.c #define SPRD_SPI_CSN_MASK		GENMASK(11, 8)
GENMASK            81 drivers/spi/spi-sprd.c #define SPRD_SPI_RTX_MD_MASK		GENMASK(13, 12)
GENMASK            88 drivers/spi/spi-sprd.c #define SPRD_SPI_ONLY_RECV_MASK		GENMASK(8, 0)
GENMASK           104 drivers/spi/spi-sprd.c #define SPRD_SPI_MODE_MASK		GENMASK(5, 3)
GENMASK           110 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_MAX_LEN_MASK	GENMASK(19, 0)
GENMASK           111 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_LEN_H_MASK		GENMASK(3, 0)
GENMASK           115 drivers/spi/spi-sprd.c #define SPRD_SPI_TX_LEN_L_MASK		GENMASK(15, 0)
GENMASK           118 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_MAX_LEN_MASK	GENMASK(19, 0)
GENMASK           119 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_LEN_H_MASK		GENMASK(3, 0)
GENMASK           123 drivers/spi/spi-sprd.c #define SPRD_SPI_RX_LEN_L_MASK		GENMASK(15, 0)
GENMASK            38 drivers/spi/spi-stm32-qspi.c #define CR_PRESC_MASK		GENMASK(31, 24)
GENMASK            41 drivers/spi/spi-stm32-qspi.c #define DCR_FSIZE_MASK		GENMASK(20, 16)
GENMASK            50 drivers/spi/spi-stm32-qspi.c #define SR_FLEVEL_MASK		GENMASK(13, 8)
GENMASK            59 drivers/spi/spi-stm32-qspi.c #define CCR_INST_MASK		GENMASK(7, 0)
GENMASK            60 drivers/spi/spi-stm32-qspi.c #define CCR_IMODE_MASK		GENMASK(9, 8)
GENMASK            61 drivers/spi/spi-stm32-qspi.c #define CCR_ADMODE_MASK		GENMASK(11, 10)
GENMASK            62 drivers/spi/spi-stm32-qspi.c #define CCR_ADSIZE_MASK		GENMASK(13, 12)
GENMASK            63 drivers/spi/spi-stm32-qspi.c #define CCR_DCYC_MASK		GENMASK(22, 18)
GENMASK            64 drivers/spi/spi-stm32-qspi.c #define CCR_DMODE_MASK		GENMASK(25, 24)
GENMASK            65 drivers/spi/spi-stm32-qspi.c #define CCR_FMODE_MASK		GENMASK(27, 26)
GENMASK            35 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_BR		GENMASK(5, 3)
GENMASK            47 drivers/spi/spi-stm32.c #define STM32F4_SPI_CR1_BR_MAX		(GENMASK(5, 3) >> 3)
GENMASK            98 drivers/spi/spi-stm32.c #define STM32H7_SPI_CR2_TSIZE		GENMASK(15, 0)
GENMASK           102 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_DSIZE		GENMASK(4, 0)
GENMASK           104 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_FTHLV		GENMASK(8, 5)
GENMASK           108 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_MBR		GENMASK(30, 28)
GENMASK           110 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG1_MBR_MAX	(GENMASK(30, 28) >> 28)
GENMASK           114 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_MIDI		GENMASK(7, 4)
GENMASK           116 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_COMM		GENMASK(18, 17)
GENMASK           118 drivers/spi/spi-stm32.c #define STM32H7_SPI_CFG2_SP		GENMASK(21, 19)
GENMASK           134 drivers/spi/spi-stm32.c #define STM32H7_SPI_IER_ALL		GENMASK(10, 0)
GENMASK           144 drivers/spi/spi-stm32.c #define STM32H7_SPI_SR_RXPLVL		GENMASK(14, 13)
GENMASK           148 drivers/spi/spi-stm32.c #define STM32H7_SPI_IFCR_ALL		GENMASK(11, 3)
GENMASK            46 drivers/spi/spi-uniphier.c #define   SSI_CKS_CKRAT_MASK	GENMASK(7, 0)
GENMASK            52 drivers/spi/spi-uniphier.c #define   SSI_TXWDS_WDLEN_MASK	GENMASK(13, 8)
GENMASK            53 drivers/spi/spi-uniphier.c #define   SSI_TXWDS_TDTF_MASK	GENMASK(7, 6)
GENMASK            54 drivers/spi/spi-uniphier.c #define   SSI_TXWDS_DTLEN_MASK	GENMASK(5, 0)
GENMASK            57 drivers/spi/spi-uniphier.c #define   SSI_RXWDS_DTLEN_MASK	GENMASK(5, 0)
GENMASK            82 drivers/spi/spi-uniphier.c #define   SSI_FC_TXFTH_MASK	GENMASK(11, 8)
GENMASK            84 drivers/spi/spi-uniphier.c #define   SSI_FC_RXFTH_MASK	GENMASK(3, 0)
GENMASK            58 drivers/spi/spi-xtensa-xtfpga.c 	xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
GENMASK            51 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_BDRATE_MASK	GENMASK(5, 3) /* Baud Rate Mask */
GENMASK            55 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK	GENMASK(7, 6) /* FIFO width */
GENMASK            64 drivers/spi/spi-zynq-qspi.c #define ZYNQ_QSPI_BAUD_DIV_MAX		GENMASK(2, 0) /* Baud rate maximum */
GENMASK            62 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_MLOC_MASK	GENMASK(2, 1)	/* Memory location bits */
GENMASK            65 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_MEM_MASK	GENMASK(31, 4)
GENMASK            67 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASRR_IO_MASK	GENMASK(31, 2)
GENMASK            76 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASBA_MEM_MASK	GENMASK(31, 4)
GENMASK            78 drivers/staging/comedi/drivers/plx9080.h #define PLX_LASBA_IO_MASK	GENMASK(31, 2)
GENMASK            87 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_LT_MASK	GENMASK(7, 0)
GENMASK            91 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PT_MASK	GENMASK(15, 8)
GENMASK           103 drivers/staging/comedi/drivers/plx9080.h #define PLX_MARBR_PRIO_MASK	GENMASK(20, 19)
GENMASK           169 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSWIDTH_MASK	GENMASK(1, 0)
GENMASK           172 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_MSIWS_MASK	GENMASK(5, 2)
GENMASK           190 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD_PFCOUNT_MASK	GENMASK(14, 11)
GENMASK           197 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMWIDTH_MASK	GENMASK(17, 16)
GENMASK           200 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_EROMIWS_MASK	GENMASK(21, 18)
GENMASK           216 drivers/staging/comedi/drivers/plx9080.h #define PLX_LBRD0_TRDELAY_MASK	GENMASK(31, 28)
GENMASK           249 drivers/staging/comedi/drivers/plx9080.h 				  (GENMASK(8, 5) & (v))) >> 5)
GENMASK           250 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_PAFL_MASK	(BIT(10) | GENMASK(8, 5))
GENMASK           262 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_WDELAY_MASK	GENMASK(15, 14)
GENMASK           264 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMPBAM_REMAP_MASK	GENMASK(31, 16)
GENMASK           272 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_TYPE_MASK	GENMASK(1, 0)
GENMASK           275 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_REGNUM_MASK	GENMASK(7, 2)
GENMASK           279 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_FUNCNUM_MASK	GENMASK(10, 8)
GENMASK           283 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_DEVNUM_MASK	GENMASK(15, 11)
GENMASK           287 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMCFGA_BUSNUM_MASK	GENMASK(23, 16)
GENMASK           398 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCRDMA_MASK	GENMASK(3, 0)
GENMASK           403 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCWDMA_MASK	GENMASK(7, 4)
GENMASK           408 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCRDM_MASK	GENMASK(11, 8)
GENMASK           413 drivers/staging/comedi/drivers/plx9080.h #define PLX_CNTRL_CCWDM_MASK	GENMASK(15, 12)
GENMASK           465 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_WIDTH_MASK	GENMASK(1, 0)
GENMASK           468 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMAMODE_IWS_MASK	GENMASK(5, 2)
GENMASK           524 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMADPR_NEXT_MASK	GENMASK(31, 4)
GENMASK           555 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0PLAF_MASK	GENMASK(3, 0)
GENMASK           559 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0LPAE_MASK	GENMASK(7, 4)
GENMASK           563 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0LPAF_MASK	GENMASK(11, 8)
GENMASK           567 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C0PLAE_MASK	GENMASK(15, 12)
GENMASK           571 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1PLAF_MASK	GENMASK(19, 16)
GENMASK           575 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1LPAE_MASK	GENMASK(23, 20)
GENMASK           579 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1LPAF_MASK	GENMASK(27, 24)
GENMASK           583 drivers/staging/comedi/drivers/plx9080.h #define PLX_DMATHR_C1PLAE_MASK	GENMASK(31, 28)
GENMASK            74 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h 	GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
GENMASK            81 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h 	(((var)  >> (bit)) & GENMASK(0, 0))
GENMASK           317 drivers/staging/iio/accel/adis16240.c 		return adis_write_reg_16(st, addr, val & GENMASK(9, 0));
GENMASK            50 drivers/staging/iio/cdc/ad7150.c #define AD7150_THRESHTYPE_MSK			GENMASK(6, 5)
GENMASK            74 drivers/staging/iio/cdc/ad7746.c #define AD7746_CONF_VTFS_MASK		GENMASK(7, 6)
GENMASK            75 drivers/staging/iio/cdc/ad7746.c #define AD7746_CONF_CAPFS_MASK		GENMASK(5, 3)
GENMASK            54 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_TYPE_MASK GENMASK(2, 0)
GENMASK            59 drivers/staging/ks7010/eap_packet.h #define WPA_KEY_INFO_KEY_INDEX_MASK GENMASK(5, 4)
GENMASK            72 drivers/staging/ks7010/ks_wlan.h #define SME_WEP_VAL_MASK    GENMASK(8, 5)
GENMASK            25 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_AXI_RD_ID(v)		(((v) << 24) & GENMASK(31, 24))
GENMASK            32 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_LATENCY(v)		(((v) << 11) & GENMASK(16, 11))
GENMASK            38 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_MAX_BURST(v)		(((v) << 0) & GENMASK(4, 0))
GENMASK            40 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_MODE(v)		(((v) << 28) & GENMASK(31, 28))
GENMASK            50 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_DEC_AXI_WR_ID(v)		(((v) << 0) & GENMASK(7, 0))
GENMASK            52 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_MB_WIDTH(v)		(((v) << 23) & GENMASK(31, 23))
GENMASK            53 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_PIC_MB_HEIGHT_P(v)	(((v) << 11) & GENMASK(18, 11))
GENMASK            57 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_STRM_START_BIT(v)	(((v) << 26) & GENMASK(31, 26))
GENMASK            60 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_INTRA_DC_PREC(v)		(((v) << 2) & GENMASK(3, 2))
GENMASK            64 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_INIT_QP(v)		(((v) << 25) & GENMASK(30, 25))
GENMASK            65 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_STREAM_LEN(v)		(((v) << 0) & GENMASK(23, 0))
GENMASK            68 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FCODE_FWD_HOR(v)		(((v) << 15) & GENMASK(18, 15))
GENMASK            69 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FCODE_FWD_VER(v)		(((v) << 11) & GENMASK(14, 11))
GENMASK            70 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FCODE_BWD_HOR(v)		(((v) << 7) & GENMASK(10, 7))
GENMASK            71 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_FCODE_BWD_VER(v)		(((v) << 3) & GENMASK(6, 3))
GENMASK            75 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_STARTMB_X(v)		(((v) << 23) & GENMASK(31, 23))
GENMASK            76 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_STARTMB_Y(v)		(((v) << 15) & GENMASK(22, 15))
GENMASK            78 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c #define G1_REG_APF_THRESHOLD(v)		(((v) << 0) & GENMASK(13, 0))
GENMASK            28 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_LATENCY(v)		(((v) << 1) & GENMASK(6, 1))
GENMASK            30 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_INIT_QP(v)		(((v) << 25) & GENMASK(30, 25))
GENMASK            31 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_STREAM_LEN(v)		(((v) << 0) & GENMASK(23, 0))
GENMASK            33 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_APF_THRESHOLD(v)	(((v) << 17) & GENMASK(30, 17))
GENMASK            34 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_STARTMB_X(v)		(((v) << 8) & GENMASK(16, 8))
GENMASK            35 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_STARTMB_Y(v)		(((v) << 0) & GENMASK(7, 0))
GENMASK            37 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_MODE(v)		(((v) << 0) & GENMASK(3, 0))
GENMASK            47 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_MAX_BURST(v)	(((v) << 16) & GENMASK(20, 16))
GENMASK            48 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_AXI_WR_ID(v)	(((v) << 8) & GENMASK(15, 8))
GENMASK            49 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_DEC_AXI_RD_ID(v)	(((v) << 0) & GENMASK(7, 0))
GENMASK            62 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_MB_WIDTH(v)	(((v) << 23) & GENMASK(31, 23))
GENMASK            63 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_PIC_MB_HEIGHT_P(v)	(((v) << 11) & GENMASK(18, 11))
GENMASK            67 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_STRM_START_BIT(v)	(((v) << 26) & GENMASK(31, 26))
GENMASK            70 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_INTRA_DC_PREC(v)	(((v) << 2) & GENMASK(3, 2))
GENMASK            75 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FCODE_FWD_HOR(v)	(((v) << 15) & GENMASK(18, 15))
GENMASK            76 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FCODE_FWD_VER(v)	(((v) << 11) & GENMASK(14, 11))
GENMASK            77 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FCODE_BWD_HOR(v)	(((v) << 7) & GENMASK(10, 7))
GENMASK            78 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c #define VDPU_REG_FCODE_BWD_VER(v)	(((v) << 3) & GENMASK(6, 3))
GENMASK            20 drivers/staging/media/meson/vdec/codec_mpeg12.c 	#define MPEG2_SEQ_DAR_MASK	GENMASK(3, 0)
GENMASK           176 drivers/staging/media/meson/vdec/codec_mpeg12.c 	if ((reg & GENMASK(23, 17)) == GENMASK(23, 17))
GENMASK            14 drivers/staging/media/sunxi/cedrus/cedrus_regs.h 	(((unsigned long)(v) << (l)) & GENMASK(h, l))
GENMASK            78 drivers/staging/media/sunxi/cedrus/cedrus_regs.h 	(((unsigned long)(__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y))
GENMASK           210 drivers/staging/media/sunxi/cedrus/cedrus_regs.h 		u32 _lo = _tmp & GENMASK(27, 4);			\
GENMASK           211 drivers/staging/media/sunxi/cedrus/cedrus_regs.h 		u32 _hi = (_tmp >> 28) & GENMASK(3, 0);			\
GENMASK           421 drivers/staging/media/tegra-vde/vde.c 	value |= bitstream_data_size & GENMASK(19, 15);
GENMASK            25 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_LCDDS_PCW			GENMASK(30, 0)
GENMASK            30 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_XTAL_TYPE			GENMASK(10, 9)
GENMASK            38 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_BC				GENMASK(23, 22)
GENMASK            40 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_BP				GENMASK(21, 18)
GENMASK            42 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_IR				GENMASK(15, 12)
GENMASK            44 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_IC				GENMASK(11, 8)
GENMASK            46 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_PREDIV			GENMASK(7, 6)
GENMASK            48 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_PLL_DIVEN			GENMASK(3, 1)
GENMASK            52 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_FBKSEL			GENMASK(5, 4)
GENMASK            56 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_LCDDS_SSC_PRD			GENMASK(15, 0)
GENMASK            60 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_LCDDS_SSC_DELTA		GENMASK(11, 0)
GENMASK            62 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_LCDDS_SSC_DELTA1		GENMASK(27, 16)
GENMASK            69 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_H_PLL_BR				GENMASK(18, 16)
GENMASK            73 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c #define RG_PE1_MSTCKDIV				GENMASK(7, 6)
GENMASK            43 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_FTS_NUM_MASK		GENMASK(15, 8)
GENMASK            60 drivers/staging/mt7621-pci/pci-mt7621.c #define MT7621_BR0_MASK			GENMASK(19, 16)
GENMASK            61 drivers/staging/mt7621-pci/pci-mt7621.c #define MT7621_BR1_MASK			GENMASK(23, 20)
GENMASK            62 drivers/staging/mt7621-pci/pci-mt7621.c #define MT7621_BR2_MASK			GENMASK(27, 24)
GENMASK            63 drivers/staging/mt7621-pci/pci-mt7621.c #define MT7621_BR_ALL_MASK		GENMASK(27, 16)
GENMASK            82 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_BAR_MAP_MAX		GENMASK(30, 16)
GENMASK            90 drivers/staging/mt7621-pci/pci-mt7621.c #define PCIE_CLK_GEN1_DIS		GENMASK(30, 24)
GENMASK            93 drivers/staging/mt7621-pci/pci-mt7621.c #define PERST_MODE_MASK			GENMASK(11, 10)
GENMASK           141 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_CMD_AINFO		((u16)GENMASK(14, 8))
GENMASK           142 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_CMD_MACPORT		((u16)GENMASK(10, 8))
GENMASK           143 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_CMD_PROGMODE		((u16)GENMASK(9, 8))
GENMASK           144 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_CMD_CMDCODE		((u16)GENMASK(5, 0))
GENMASK           145 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_STATUS_RESULT		((u16)GENMASK(14, 8))
GENMASK           505 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_TX_MACPORT			((u16)GENMASK(10, 8))
GENMASK           506 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_TX_STRUCTYPE			((u16)GENMASK(4, 3))
GENMASK           564 drivers/staging/wlan-ng/hfa384x.h #define		HFA384x_RXSTATUS_MACPORT		((u16)GENMASK(10, 8))
GENMASK           135 drivers/staging/wlan-ng/p80211hdr.h #define WLAN_GET_FC_FTYPE(n)	((((u16)(n)) & GENMASK(3, 2)) >> 2)
GENMASK           136 drivers/staging/wlan-ng/p80211hdr.h #define WLAN_GET_FC_FSTYPE(n)	((((u16)(n)) & GENMASK(7, 4)) >> 4)
GENMASK           147 drivers/staging/wlan-ng/p80211netdev.h #define HOSTWEP_DEFAULTKEY_MASK GENMASK(1, 0)
GENMASK           652 drivers/staging/wlan-ng/prism2sta.c 	hw->mm_mods = hw->ident_sta_fw.variant & GENMASK(15, 14);
GENMASK           653 drivers/staging/wlan-ng/prism2sta.c 	hw->ident_sta_fw.variant &= ~((u16)GENMASK(15, 14));
GENMASK            37 drivers/tee/optee/optee_msg.h #define OPTEE_MSG_ATTR_TYPE_MASK		GENMASK(7, 0)
GENMASK            83 drivers/tee/optee/optee_msg.h #define OPTEE_MSG_ATTR_CACHE_MASK		GENMASK(2, 0)
GENMASK            36 drivers/thermal/broadcom/bcm2835_thermal.c 	GENMASK(BCM2835_TS_TSENSCTL_CTRL_BITS +     \
GENMASK            46 drivers/thermal/broadcom/bcm2835_thermal.c 	GENMASK(BCM2835_TS_TSENSCTL_THOLD_BITS +     \
GENMASK            60 drivers/thermal/broadcom/bcm2835_thermal.c 	GENMASK(BCM2835_TS_TSENSSTAT_DATA_BITS +     \
GENMASK            26 drivers/thermal/broadcom/brcmstb_thermal.c  #define AVS_TMON_STATUS_data_msk	GENMASK(10, 1)
GENMASK            33 drivers/thermal/broadcom/brcmstb_thermal.c  #define AVS_TMON_RESET_THRESH_msk	GENMASK(10, 1)
GENMASK            43 drivers/thermal/broadcom/brcmstb_thermal.c  #define AVS_TMON_INT_THRESH_high_msk	GENMASK(26, 17)
GENMASK            45 drivers/thermal/broadcom/brcmstb_thermal.c  #define AVS_TMON_INT_THRESH_low_msk	GENMASK(10, 1)
GENMASK            30 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define STATUS_GEN1_STAGE_MASK		GENMASK(1, 0)
GENMASK            31 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define STATUS_GEN2_STATE_MASK		GENMASK(6, 4)
GENMASK            35 drivers/thermal/qcom/qcom-spmi-temp-alarm.c #define SHUTDOWN_CTRL1_THRESHOLD_MASK	GENMASK(1, 0)
GENMASK           147 drivers/thermal/qcom/tsens-8960.c 	mask = GENMASK(priv->num_sensors - 1, 0);
GENMASK           202 drivers/thermal/qcom/tsens-8960.c 	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
GENMASK           117 drivers/thermal/qcom/tsens-common.c 		mask = GENMASK(priv->fields[LAST_TEMP_0].msb,
GENMASK            36 drivers/thermal/st/stm_thermal.c #define HSREF_CLK_DIV_MASK	GENMASK(30, 24)
GENMASK            37 drivers/thermal/st/stm_thermal.c #define TS1_SMP_TIME_MASK	GENMASK(19, 16)
GENMASK            38 drivers/thermal/st/stm_thermal.c #define TS1_INTRIG_SEL_MASK	GENMASK(11, 8)
GENMASK            41 drivers/thermal/st/stm_thermal.c #define TS1_T0_MASK		GENMASK(17, 16)
GENMASK            42 drivers/thermal/st/stm_thermal.c #define TS1_FMT0_MASK		GENMASK(15, 0)
GENMASK            45 drivers/thermal/st/stm_thermal.c #define TS1_RAMP_COEFF_MASK	GENMASK(15, 0)
GENMASK            48 drivers/thermal/st/stm_thermal.c #define TS1_HITTHD_MASK		GENMASK(31, 16)
GENMASK            49 drivers/thermal/st/stm_thermal.c #define TS1_LITTHD_MASK		GENMASK(15, 0)
GENMASK            52 drivers/thermal/st/stm_thermal.c #define TS1_MFREQ_MASK		GENMASK(15, 0)
GENMASK            35 drivers/thermal/uniphier_thermal.c #define EMONREPEAT_PERIOD		GENMASK(3, 0)
GENMASK            43 drivers/thermal/uniphier_thermal.c #define PVTCTLSEL_MASK			GENMASK(2, 0)
GENMASK            49 drivers/thermal/uniphier_thermal.c #define SETALERT_TEMP_OVF		(GENMASK(7, 0) << 16)
GENMASK            50 drivers/thermal/uniphier_thermal.c #define SETALERT_TEMP_OVF_VALUE(val)	(((val) & GENMASK(7, 0)) << 16)
GENMASK            57 drivers/thermal/uniphier_thermal.c #define PMALERTINTCTL_MASK		(GENMASK(10, 8) | GENMASK(6, 4) | \
GENMASK            58 drivers/thermal/uniphier_thermal.c 					 GENMASK(2, 0))
GENMASK            66 drivers/thermal/uniphier_thermal.c #define TMODSETUP0_VAL(val)		(((val) & GENMASK(13, 0)) << 16)
GENMASK            68 drivers/thermal/uniphier_thermal.c #define TMODSETUP1_VAL(val)		((val) & GENMASK(14, 0))
GENMASK            35 drivers/thermal/zx2967_thermal.c #define ZX2967_THERMAL_TEMP_MASK	GENMASK(11, 0)
GENMASK            23 drivers/thunderbolt/dma_port.c #define MAIL_IN_CMD_MASK		GENMASK(31, 28)
GENMASK            29 drivers/thunderbolt/dma_port.c #define MAIL_IN_DWORDS_MASK		GENMASK(27, 24)
GENMASK            31 drivers/thunderbolt/dma_port.c #define MAIL_IN_ADDRESS_MASK		GENMASK(23, 2)
GENMASK            38 drivers/thunderbolt/dma_port.c #define MAIL_OUT_STATUS_CMD_MASK	GENMASK(7, 4)
GENMASK            39 drivers/thunderbolt/dma_port.c #define MAIL_OUT_STATUS_MASK		GENMASK(3, 0)
GENMASK            29 drivers/thunderbolt/icm.c #define PCIE2CIO_CMD_CS_MASK		GENMASK(20, 19)
GENMASK            31 drivers/thunderbolt/icm.c #define PCIE2CIO_CMD_PORT_MASK		GENMASK(18, 13)
GENMASK            39 drivers/thunderbolt/icm.c #define PHY_PORT_CS1_LINK_STATE_MASK	GENMASK(29, 26)
GENMASK            75 drivers/thunderbolt/nhi_regs.h #define REG_RX_OPTIONS_E2E_HOP_MASK	GENMASK(22, 12)
GENMASK           100 drivers/thunderbolt/nhi_regs.h #define REG_INT_VEC_ALLOC_MASK	GENMASK(3, 0)
GENMASK           112 drivers/thunderbolt/nhi_regs.h #define REG_INMAIL_CMD_MASK		GENMASK(7, 0)
GENMASK           118 drivers/thunderbolt/nhi_regs.h #define REG_OUTMAIL_CMD_OPMODE_MASK	GENMASK(11, 8)
GENMASK           145 drivers/thunderbolt/nhi_regs.h #define VS_CAP_19_CMD_MASK		GENMASK(7, 1)
GENMASK           149 drivers/thunderbolt/nhi_regs.h #define VS_CAP_22_DMA_DELAY_MASK	GENMASK(31, 24)
GENMASK           124 drivers/thunderbolt/tb_msgs.h #define ICM_FLAGS_SLEVEL_MASK		GENMASK(4, 3)
GENMASK           164 drivers/thunderbolt/tb_msgs.h #define ICM_SWITCH_UPSTREAM_PORT_MASK	GENMASK(7, 1)
GENMASK           167 drivers/thunderbolt/tb_msgs.h #define ICM_PORT_TYPE_MASK		GENMASK(23, 0)
GENMASK           169 drivers/thunderbolt/tb_msgs.h #define ICM_PORT_INDEX_MASK		GENMASK(31, 24)
GENMASK           182 drivers/thunderbolt/tb_msgs.h #define ICM_LINK_INFO_DEPTH_MASK	GENMASK(7, 4)
GENMASK           289 drivers/thunderbolt/tb_msgs.h #define ICM_AR_INFO_SLEVEL_MASK		GENMASK(3, 0)
GENMASK           291 drivers/thunderbolt/tb_msgs.h #define ICM_AR_INFO_BOOT_ACL_MASK	GENMASK(11, 7)
GENMASK           338 drivers/thunderbolt/tb_msgs.h #define ICM_TR_INFO_SLEVEL_MASK		GENMASK(2, 0)
GENMASK           340 drivers/thunderbolt/tb_msgs.h #define ICM_TR_INFO_BOOT_ACL_MASK	GENMASK(12, 7)
GENMASK           482 drivers/thunderbolt/tb_msgs.h #define TB_XDOMAIN_LENGTH_MASK	GENMASK(5, 0)
GENMASK           483 drivers/thunderbolt/tb_msgs.h #define TB_XDOMAIN_SN_MASK	GENMASK(28, 27)
GENMASK           215 drivers/thunderbolt/tb_regs.h #define TB_PORT_NFC_CREDITS_MASK	GENMASK(19, 0)
GENMASK           217 drivers/thunderbolt/tb_regs.h #define TB_PORT_MAX_CREDITS_MASK	GENMASK(26, 20)
GENMASK           220 drivers/thunderbolt/tb_regs.h #define TB_PORT_LCA_MASK		GENMASK(28, 22)
GENMASK           226 drivers/thunderbolt/tb_regs.h #define TB_DP_VIDEO_HOPID_MASK		GENMASK(26, 16)
GENMASK           230 drivers/thunderbolt/tb_regs.h #define TB_DP_AUX_TX_HOPID_MASK		GENMASK(10, 0)
GENMASK           232 drivers/thunderbolt/tb_regs.h #define TB_DP_AUX_RX_HOPID_MASK		GENMASK(21, 11)
GENMASK           275 drivers/thunderbolt/tb_regs.h #define TB_LC_DESC_NLC_MASK		GENMASK(3, 0)
GENMASK           277 drivers/thunderbolt/tb_regs.h #define TB_LC_DESC_SIZE_MASK		GENMASK(15, 8)
GENMASK           279 drivers/thunderbolt/tb_regs.h #define TB_LC_DESC_PORT_SIZE_MASK	GENMASK(27, 16)
GENMASK            27 drivers/tty/serial/8250/8250_aspeed_vuart.c #define ASPEED_VUART_GCRB_HOST_SIRQ_MASK	GENMASK(7, 4)
GENMASK            41 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_USMODE		GENMASK(3, 0)	/* Mode of the USART */
GENMASK            49 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_USCLKS		GENMASK(5, 4)	/* Clock Selection */
GENMASK            53 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
GENMASK            59 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_PAR		GENMASK(11, 9)	/* Parity Type */
GENMASK            66 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_NBSTOP		GENMASK(13, 12)	/* Number of Stop Bits */
GENMASK            70 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
GENMASK            81 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_MAX_ITER_MASK	GENMASK(26, 24)	/* Max Iterations */
GENMASK           117 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_CD		GENMASK(15, 0)	/* Clock Divider */
GENMASK           123 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_TO		GENMASK(15, 0)	/* Time-out Value */
GENMASK           126 drivers/tty/serial/atmel_serial.h #define	ATMEL_US_TG		GENMASK(7, 0)	/* Timeguard Value */
GENMASK            60 drivers/tty/serial/lantiq.c #define ASC_IRNCR_MASK		GENMASK(2, 0)
GENMASK            54 drivers/tty/serial/mps2-uart.c #define UARTn_BAUDDIV_MASK			GENMASK(20, 0)
GENMASK            31 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_DWLS_MASK		GENMASK(1, 0)
GENMASK            37 drivers/tty/serial/owl-uart.c #define OWL_UART_CTL_PRS_MASK		GENMASK(6, 4)
GENMASK            62 drivers/tty/serial/owl-uart.c #define OWL_UART_STAT_TRFL_MASK		GENMASK(16, 11)
GENMASK            41 drivers/tty/serial/qcom_geni_serial.c #define TX_WORD_LEN_MSK		GENMASK(9, 0)
GENMASK            44 drivers/tty/serial/qcom_geni_serial.c #define TX_STOP_BIT_LEN_MSK	GENMASK(23, 0)
GENMASK            50 drivers/tty/serial/qcom_geni_serial.c #define TX_TRANS_LEN_MSK	GENMASK(23, 0)
GENMASK            57 drivers/tty/serial/qcom_geni_serial.c #define RX_WORD_LEN_MASK	GENMASK(9, 0)
GENMASK            60 drivers/tty/serial/qcom_geni_serial.c #define RX_STALE_CNT		GENMASK(23, 0)
GENMASK            64 drivers/tty/serial/qcom_geni_serial.c #define PAR_MODE_MSK		GENMASK(2, 1)
GENMASK            91 drivers/tty/serial/sh-sci.c #define SCI_SR_RANGE(x, y)	GENMASK((y) - 1, (x) - 1)
GENMASK            51 drivers/tty/serial/sprd_serial.c #define SPRD_RX_FIFO_CNT_MASK	GENMASK(7, 0)
GENMASK            52 drivers/tty/serial/sprd_serial.c #define SPRD_TX_FIFO_CNT_MASK	GENMASK(15, 8)
GENMASK            94 drivers/tty/serial/sprd_serial.c #define THLD_RX_FULL_MASK	GENMASK(6, 0)
GENMASK            98 drivers/tty/serial/sprd_serial.c #define SPRD_CLKD0_MASK		GENMASK(15, 0)
GENMASK           100 drivers/tty/serial/sprd_serial.c #define SPRD_CLKD1_MASK		GENMASK(20, 16)
GENMASK           120 drivers/tty/serial/stm32-usart.c 		usartdiv = usartdiv & GENMASK(15, 0);
GENMASK           124 drivers/tty/serial/stm32-usart.c 			usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
GENMASK           134 drivers/tty/serial/stm32-usart.h #define USART_DR_MASK		GENMASK(8, 0)
GENMASK           137 drivers/tty/serial/stm32-usart.h #define USART_BRR_DIV_F_MASK	GENMASK(3, 0)
GENMASK           138 drivers/tty/serial/stm32-usart.h #define USART_BRR_DIV_M_MASK	GENMASK(15, 4)
GENMASK           160 drivers/tty/serial/stm32-usart.h #define USART_CR1_DEDT_MASK	GENMASK(20, 16)	/* F7 */
GENMASK           161 drivers/tty/serial/stm32-usart.h #define USART_CR1_DEAT_MASK	GENMASK(25, 21)	/* F7 */
GENMASK           165 drivers/tty/serial/stm32-usart.h #define USART_CR1_IE_MASK	(GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
GENMASK           171 drivers/tty/serial/stm32-usart.h #define USART_CR2_ADD_MASK	GENMASK(3, 0)	/* F4 */
GENMASK           178 drivers/tty/serial/stm32-usart.h #define USART_CR2_STOP_MASK	GENMASK(13, 12)
GENMASK           186 drivers/tty/serial/stm32-usart.h #define USART_CR2_ABRMOD_MASK	GENMASK(22, 21)	/* F7 */
GENMASK           188 drivers/tty/serial/stm32-usart.h #define USART_CR2_ADD_F7_MASK	GENMASK(31, 24)	/* F7 */
GENMASK           207 drivers/tty/serial/stm32-usart.h #define USART_CR3_SCARCNT_MASK	GENMASK(19, 17)	/* F7 */
GENMASK           208 drivers/tty/serial/stm32-usart.h #define USART_CR3_WUS_MASK	GENMASK(21, 20)	/* H7 */
GENMASK           213 drivers/tty/serial/stm32-usart.h #define USART_CR3_RXFTCFG_MASK	GENMASK(27, 25)	/* H7 */
GENMASK           216 drivers/tty/serial/stm32-usart.h #define USART_CR3_TXFTCFG_MASK	GENMASK(31, 29)	/* H7 */
GENMASK           226 drivers/tty/serial/stm32-usart.h #define USART_GTPR_PSC_MASK	GENMASK(7, 0)
GENMASK           227 drivers/tty/serial/stm32-usart.h #define USART_GTPR_GT_MASK	GENMASK(15, 8)
GENMASK           230 drivers/tty/serial/stm32-usart.h #define USART_RTOR_RTO_MASK	GENMASK(23, 0)	/* F7 */
GENMASK           231 drivers/tty/serial/stm32-usart.h #define USART_RTOR_BLEN_MASK	GENMASK(31, 24)	/* F7 */
GENMASK            73 drivers/usb/cdns3/drd.h #define CDNS_RID(p)			((p) & GENMASK(15, 0))
GENMASK            76 drivers/usb/cdns3/drd.h #define CDNS_DID(p)			((p) & GENMASK(31, 0))
GENMASK           131 drivers/usb/cdns3/drd.h #define OTGSTS_STRAP(p)			(((p) & GENMASK(14, 12)) >> 12)
GENMASK           142 drivers/usb/cdns3/drd.h #define OTGSTATE_DEV_STATE_MASK		GENMASK(2, 0)
GENMASK           143 drivers/usb/cdns3/drd.h #define OTGSTATE_HOST_STATE_MASK	GENMASK(5, 3)
GENMASK           227 drivers/usb/cdns3/gadget.h #define USB_STS_USBSPEED_MASK	GENMASK(6, 4)
GENMASK           310 drivers/usb/cdns3/gadget.h #define USB_STS_LPMST_MASK	GENMASK(19, 18)
GENMASK           347 drivers/usb/cdns3/gadget.h #define USB_STS_LST_MASK	GENMASK(29, 26)
GENMASK           385 drivers/usb/cdns3/gadget.h #define USB_CMD_FADDR_MASK	GENMASK(7, 1)
GENMASK           392 drivers/usb/cdns3/gadget.h #define USB_STS_TMODE_SEL_MASK	GENMASK(11, 10)
GENMASK           402 drivers/usb/cdns3/gadget.h #define USB_CMD_DNFW_INT_MASK	GENMASK(23, 16)
GENMASK           408 drivers/usb/cdns3/gadget.h #define USB_CMD_DNLTM_BELT_MASK	GENMASK(27, 16)
GENMASK           417 drivers/usb/cdns3/gadget.h #define USB_ITPN_MASK		GENMASK(13, 0)
GENMASK           422 drivers/usb/cdns3/gadget.h #define USB_LPM_HIRD_MASK	GENMASK(3, 0)
GENMASK           529 drivers/usb/cdns3/gadget.h #define EP_SEL_EPNO_MASK	GENMASK(3, 0)
GENMASK           551 drivers/usb/cdns3/gadget.h #define EP_CFG_EPTYPE_MASK	GENMASK(2, 1)
GENMASK           562 drivers/usb/cdns3/gadget.h #define EP_CFG_MAXBURST_MASK	GENMASK(11, 8)
GENMASK           565 drivers/usb/cdns3/gadget.h #define EP_CFG_MULT_MASK	GENMASK(15, 14)
GENMASK           568 drivers/usb/cdns3/gadget.h #define EP_CFG_MAXPKTSIZE_MASK	GENMASK(26, 16)
GENMASK           571 drivers/usb/cdns3/gadget.h #define EP_CFG_BUFFERING_MASK	GENMASK(31, 27)
GENMASK           599 drivers/usb/cdns3/gadget.h #define EP_CMD_TDL_MASK		GENMASK(15, 9)
GENMASK           604 drivers/usb/cdns3/gadget.h #define EP_CMD_ERDY_SID_MASK	GENMASK(31, 16)
GENMASK           643 drivers/usb/cdns3/gadget.h #define EP_STS_SPSMST_MASK		GENMASK(18, 17)
GENMASK           651 drivers/usb/cdns3/gadget.h #define EP_STS_OUTQ_NO_MASK	GENMASK(27, 24)
GENMASK           661 drivers/usb/cdns3/gadget.h #define EP_STS_SID_MASK		GENMASK(15, 0)
GENMASK           750 drivers/usb/cdns3/gadget.h #define USB_CAP1_SFR_TYPE_MASK	GENMASK(3, 0)
GENMASK           764 drivers/usb/cdns3/gadget.h #define USB_CAP1_SFR_WIDTH_MASK	GENMASK(7, 4)
GENMASK           778 drivers/usb/cdns3/gadget.h #define USB_CAP1_DMA_TYPE_MASK	GENMASK(11, 8)
GENMASK           792 drivers/usb/cdns3/gadget.h #define USB_CAP1_DMA_WIDTH_MASK	GENMASK(15, 12)
GENMASK           802 drivers/usb/cdns3/gadget.h #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
GENMASK           816 drivers/usb/cdns3/gadget.h #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
GENMASK           868 drivers/usb/cdns3/gadget.h #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
GENMASK           883 drivers/usb/cdns3/gadget.h #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
GENMASK           896 drivers/usb/cdns3/gadget.h #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
GENMASK           898 drivers/usb/cdns3/gadget.h #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
GENMASK           910 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p)	((p) & GENMASK(7, 0))
GENMASK           915 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK	GENMASK(15, 8)
GENMASK           916 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p)	(((p) << 8) & GENMASK(15, 8))
GENMASK           927 drivers/usb/cdns3/gadget.h #define DBG_LINK1_LFPS_GEN_PING(p)		(((p) << 17) & GENMASK(21, 17))
GENMASK           955 drivers/usb/cdns3/gadget.h #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
GENMASK           957 drivers/usb/cdns3/gadget.h #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
GENMASK          1007 drivers/usb/cdns3/gadget.h #define TRB_TYPE_BITMASK	GENMASK(15, 10)
GENMASK          1044 drivers/usb/cdns3/gadget.h #define TRB_STREAM_ID_BITMASK		GENMASK(31, 16)
GENMASK          1049 drivers/usb/cdns3/gadget.h #define TRB_TDL_HS_SIZE(p)	(((p) << 16) & GENMASK(31, 16))
GENMASK          1050 drivers/usb/cdns3/gadget.h #define TRB_TDL_HS_SIZE_GET(p)	(((p) & GENMASK(31, 16)) >> 16)
GENMASK          1053 drivers/usb/cdns3/gadget.h #define TRB_LEN(p)		((p) & GENMASK(16, 0))
GENMASK          1056 drivers/usb/cdns3/gadget.h #define TRB_TDL_SS_SIZE(p)	(((p) << 17) & GENMASK(23, 17))
GENMASK          1057 drivers/usb/cdns3/gadget.h #define TRB_TDL_SS_SIZE_GET(p)	(((p) & GENMASK(23, 17)) >> 17)
GENMASK          1060 drivers/usb/cdns3/gadget.h #define TRB_BURST_LEN(p)	(((p) << 24) & GENMASK(31, 24))
GENMASK          1061 drivers/usb/cdns3/gadget.h #define TRB_BURST_LEN_GET(p)	(((p) & GENMASK(31, 24)) >> 24)
GENMASK          1064 drivers/usb/cdns3/gadget.h #define TRB_BUFFER(p)		((p) & GENMASK(31, 0))
GENMASK            48 drivers/usb/chipidea/ulpi.c 	return hw_read(ci, OP_ULPI_VIEWPORT, GENMASK(15, 8)) >> 8;
GENMASK           234 drivers/usb/dwc2/hw.h #define GSNPSID_ID_MASK			GENMASK(31, 16)
GENMASK            56 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
GENMASK            57 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
GENMASK            63 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(4, 2)
GENMASK            64 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(9, 7)
GENMASK            65 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(13, 12)
GENMASK            69 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
GENMASK            70 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
GENMASK            73 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
GENMASK            74 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
GENMASK            78 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
GENMASK            79 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
GENMASK            85 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
GENMASK            91 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
GENMASK            96 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
GENMASK            97 drivers/usb/dwc3/dwc3-meson-g12a.c 	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
GENMASK            86 drivers/usb/gadget/udc/renesas_usb3.c #define DMA_CON_PIPE_NO_MASK	GENMASK(12, DMA_CON_PIPE_NO_SHIFT)
GENMASK           102 drivers/usb/gadget/udc/renesas_usb3.c #define USB_COM_CON_DEV_ADDR_MASK	GENMASK(14, USB_COM_CON_DEV_ADDR_SHIFT)
GENMASK           113 drivers/usb/gadget/udc/renesas_usb3.c #define USB20_CON_B2_TSTMOD_MASK	GENMASK(10, USB20_CON_B2_TSTMOD_SHIFT)
GENMASK           120 drivers/usb/gadget/udc/renesas_usb3.c #define USB30_CON_POW_SEL_MASK		GENMASK(26, USB30_CON_POW_SEL_SHIFT)
GENMASK           204 drivers/usb/gadget/udc/renesas_usb3.c #define PN_MOD_TYPE_MASK	GENMASK(5, PN_MOD_TYPE_SHIFT)
GENMASK           207 drivers/usb/gadget/udc/renesas_usb3.c #define PN_MOD_EPNUM_MASK	GENMASK(3, 0)
GENMASK           212 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMAREA_MASK	GENMASK(31, PN_RAMMAP_RAMAREA_SHIFT)
GENMASK           219 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_MPKT_MASK	GENMASK(26, PN_RAMMAP_MPKT_SHIFT)
GENMASK           223 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_RAMIF_MASK	GENMASK(15, PN_RAMMAP_RAMIF_SHIFT)
GENMASK           226 drivers/usb/gadget/udc/renesas_usb3.c #define PN_RAMMAP_BASEAD_MASK	GENMASK(13, 0)
GENMASK           287 drivers/usb/gadget/udc/renesas_usb3.c #define USB3_PRD1_SIZE_MASK	GENMASK(15, 0)
GENMASK            32 drivers/usb/host/ehci-orion.c #define   USB_MODE_MASK		GENMASK(1, 0)
GENMASK            29 drivers/usb/host/xhci-histb.c #define USB3_DEEMPHASIS_MASK	GENMASK(2, 1)
GENMASK            82 drivers/usb/mtu3/mtu3_gadget.c 	mep->maxp = max_packet & GENMASK(10, 0);
GENMASK           103 drivers/usb/mtu3/mtu3_gadget.c 			burst = (max_packet & GENMASK(12, 11)) >> 11;
GENMASK           104 drivers/usb/mtu3/mtu3_hw_regs.h #define LV1IECR_MSK		GENMASK(31, 0)
GENMASK           121 drivers/usb/mtu3/mtu3_hw_regs.h #define EP0_MAXPKTSZ_MSK	GENMASK(9, 0)
GENMASK           132 drivers/usb/mtu3/mtu3_hw_regs.h #define TX_TXMAXPKTSZ_MSK	GENMASK(10, 0)
GENMASK           171 drivers/usb/mtu3/mtu3_hw_regs.h #define RX_RXMAXPKTSZ_MSK	GENMASK(10, 0)
GENMASK           215 drivers/usb/mtu3/mtu3_hw_regs.h #define QMU_START_ADDR_HI_MSK	GENMASK(3, 0)
GENMASK           270 drivers/usb/mtu3/mtu3_hw_regs.h #define DEV_ADDR_MSK		GENMASK(30, 24)
GENMASK           348 drivers/usb/mtu3/mtu3_hw_regs.h #define DEV_U2_INACT_TIMEOUT_MSK	GENMASK(23, 16)
GENMASK           350 drivers/usb/mtu3/mtu3_hw_regs.h #define U2_INACT_TIMEOUT_MSK		GENMASK(15, 8)
GENMASK           351 drivers/usb/mtu3/mtu3_hw_regs.h #define U1_INACT_TIMEOUT_MSK		GENMASK(7, 0)
GENMASK           366 drivers/usb/mtu3/mtu3_hw_regs.h #define LINK_ERROR_COUNT	GENMASK(15, 0)
GENMASK           422 drivers/usb/mtu3/mtu3_hw_regs.h #define WTCHRP_MSK		GENMASK(19, 16)
GENMASK           428 drivers/usb/mtu3/mtu3_hw_regs.h #define LPM_BESL		GENMASK(3, 0)
GENMASK           277 drivers/usb/renesas_usbhs/common.c 	u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0);
GENMASK           413 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_DTR_MASK		GENMASK(1, 0)
GENMASK           431 drivers/usb/serial/cp210x.c #define CP210X_SERIAL_RTS_MASK		GENMASK(7, 6)
GENMASK           479 drivers/usb/serial/cp210x.c #define CP210X_SCI_GPIO_MODE_MASK	GENMASK(11, 9)
GENMASK           482 drivers/usb/serial/cp210x.c #define CP210X_ECI_GPIO_MODE_MASK	GENMASK(3, 2)
GENMASK           485 drivers/usb/serial/cp210x.c #define CP210X_GPIO_MODE_MASK		GENMASK(11, 8)
GENMASK            62 drivers/usb/serial/f81232.c #define F81232_CLK_MASK			GENMASK(1, 0)
GENMASK           108 drivers/usb/serial/f81534.c #define F81534_PORT_CONF_MODE_MASK	GENMASK(1, 0)
GENMASK           136 drivers/usb/serial/f81534.c #define F81534_CLK_MASK			GENMASK(2, 1)
GENMASK            58 drivers/usb/typec/tps6598x.c #define TPS_POWER_STATUS_PWROPMODE(p)	(((p) & GENMASK(3, 2)) >> 2)
GENMASK            31 drivers/usb/typec/ucsi/trace.c 	u8 cmd = raw_cmd & GENMASK(7, 0);
GENMASK            49 drivers/usb/typec/ucsi/trace.c 	if (cci & GENMASK(7, 0)) {
GENMASK          3324 drivers/video/fbdev/sis/init.c #define GENBITSMASK(mask)   	GENMASK(1?mask,0?mask)
GENMASK            47 drivers/watchdog/lantiq_wdt.c #define  LTQ_WDT_CR_PW_MASK	GENMASK(23, 16)	/* Password field */
GENMASK            51 drivers/watchdog/lantiq_wdt.c #define  LTQ_WDT_SR_VALUE_MASK	GENMASK(15, 0)	/* Timer value */
GENMASK            46 drivers/watchdog/sp5100_tco.h #define SP5100_PM_WATCHDOG_SECOND_RES	GENMASK(2, 1)
GENMASK            58 drivers/watchdog/sp5100_tco.h #define SB800_PM_WATCHDOG_SECOND_RES	GENMASK(1, 0)
GENMASK            74 drivers/watchdog/sp5100_tco.h #define EFCH_PM_DECODEEN_SECOND_RES	GENMASK(1, 0)
GENMASK            75 drivers/watchdog/sp5100_tco.h #define EFCH_PM_WATCHDOG_DISABLE	((u8)GENMASK(3, 2))
GENMASK            55 drivers/watchdog/sprd_wdt.c #define SPRD_WDT_LOW_VALUE_MASK		GENMASK(15, 0)
GENMASK            43 drivers/watchdog/stm32_iwdg.c #define RLR_MAX		GENMASK(11, 0)	/* max value of reload register */
GENMASK            25 drivers/watchdog/zx2967_wdt.c #define ZX2967_WDT_REFRESH_MASK			GENMASK(5, 0)
GENMASK            36 drivers/watchdog/zx2967_wdt.c #define ZX2967_WDT_VAL_MASK			GENMASK(15, 0)
GENMASK            42 include/linux/amba/clcd-regs.h #define TIM2_PCD_LO_MASK	GENMASK(4, 0)
GENMASK            45 include/linux/amba/clcd-regs.h #define TIM2_ACB_MASK		GENMASK(10, 6)
GENMASK            51 include/linux/amba/clcd-regs.h #define TIM2_PCD_HI_MASK	GENMASK(31, 27)
GENMASK            70 include/linux/amba/pl080.h #define PL080_LLI_ADDR_MASK			GENMASK(31, 2)
GENMASK            75 include/linux/amba/pl080.h #define PL080_CONTROL_PROT_MASK			GENMASK(30, 28)
GENMASK            84 include/linux/amba/pl080.h #define PL080_CONTROL_DWIDTH_MASK		GENMASK(23, 21)
GENMASK            86 include/linux/amba/pl080.h #define PL080_CONTROL_SWIDTH_MASK		GENMASK(20, 18)
GENMASK            88 include/linux/amba/pl080.h #define PL080_CONTROL_DB_SIZE_MASK		GENMASK(17, 15)
GENMASK            90 include/linux/amba/pl080.h #define PL080_CONTROL_SB_SIZE_MASK		GENMASK(14, 12)
GENMASK            92 include/linux/amba/pl080.h #define PL080_CONTROL_TRANSFER_SIZE_MASK	GENMASK(11, 0)
GENMASK            93 include/linux/amba/pl080.h #define PL080S_CONTROL_TRANSFER_SIZE_MASK	GENMASK(24, 0)
GENMASK           116 include/linux/amba/pl080.h #define PL080_CONFIG_FLOW_CONTROL_MASK		GENMASK(13, 11)
GENMASK           118 include/linux/amba/pl080.h #define PL080_CONFIG_DST_SEL_MASK		GENMASK(9, 6)
GENMASK           120 include/linux/amba/pl080.h #define PL080_CONFIG_SRC_SEL_MASK		GENMASK(4, 1)
GENMASK           135 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_FIFOTH_MSK		GENMASK(26, 24)
GENMASK           137 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_CHPR1_MSK		GENMASK(23, 22)
GENMASK           141 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_SRC_SIZE_MSK		GENMASK(18, 16)
GENMASK           144 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_SRC_WIDTH_MSK		GENMASK(13, 11)
GENMASK           146 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_DST_WIDTH_MSK		GENMASK(10, 8)
GENMASK           150 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_SRCAD_CTL_MSK		GENMASK(6, 5)
GENMASK           152 include/linux/amba/pl080.h #define FTDMAC020_CH_CSR_DSTAD_CTL_MSK		GENMASK(4, 3)
GENMASK           171 include/linux/amba/pl080.h #define FTDMAC020_CH_CFG_LLP_CNT_MASK		GENMASK(19, 16)
GENMASK           180 include/linux/amba/pl080.h #define FTDMAC020_LLI_SRC_WIDTH_MSK		GENMASK(27, 25)
GENMASK           182 include/linux/amba/pl080.h #define FTDMAC020_LLI_DST_WIDTH_MSK		GENMASK(24, 22)
GENMASK           184 include/linux/amba/pl080.h #define FTDMAC020_LLI_SRCAD_CTL_MSK		GENMASK(21, 20)
GENMASK           186 include/linux/amba/pl080.h #define FTDMAC020_LLI_DSTAD_CTL_MSK		GENMASK(19, 18)
GENMASK           190 include/linux/amba/pl080.h #define FTDMAC020_LLI_TRANSFER_SIZE_MASK	GENMASK(11, 0)
GENMASK           193 include/linux/amba/pl080.h #define FTDMAC020_CFG_LLP_CNT_MASK		GENMASK(19, 16)
GENMASK           190 include/linux/clk/at91_pmc.h #define		AT91_PMC_PCR_GCKDIV_MASK	GENMASK(27, 20)
GENMASK           281 include/linux/cper.h #define CPER_ARM_ERR_TRANSACTION_MASK		GENMASK(1,0)
GENMASK           283 include/linux/cper.h #define CPER_ARM_ERR_OPERATION_MASK		GENMASK(3,0)
GENMASK           285 include/linux/cper.h #define CPER_ARM_ERR_LEVEL_MASK			GENMASK(2,0)
GENMASK           287 include/linux/cper.h #define CPER_ARM_ERR_PC_CORRUPT_MASK		GENMASK(0,0)
GENMASK           289 include/linux/cper.h #define CPER_ARM_ERR_CORRECTED_MASK		GENMASK(0,0)
GENMASK           291 include/linux/cper.h #define CPER_ARM_ERR_PRECISE_PC_MASK		GENMASK(0,0)
GENMASK           293 include/linux/cper.h #define CPER_ARM_ERR_RESTARTABLE_PC_MASK	GENMASK(0,0)
GENMASK           295 include/linux/cper.h #define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK	GENMASK(1,0)
GENMASK           297 include/linux/cper.h #define CPER_ARM_ERR_TIME_OUT_MASK		GENMASK(0,0)
GENMASK           299 include/linux/cper.h #define CPER_ARM_ERR_ADDRESS_SPACE_MASK		GENMASK(1,0)
GENMASK           301 include/linux/cper.h #define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK	GENMASK(8,0)
GENMASK           303 include/linux/cper.h #define CPER_ARM_ERR_ACCESS_MODE_MASK		GENMASK(0,0)
GENMASK           200 include/linux/i3c/ccc.h #define I3C_CCC_STATUS_PENDING_INT(status)	((status) & GENMASK(3, 0))
GENMASK           203 include/linux/i3c/ccc.h 	(((status) & GENMASK(7, 6)) >> 6)
GENMASK           268 include/linux/i3c/ccc.h #define I3C_CCC_MAX_SDR_FSCL_MASK	GENMASK(2, 0)
GENMASK            86 include/linux/i3c/device.h #define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
GENMASK            23 include/linux/i3c/master.h #define I3C_MAX_ADDR			GENMASK(6, 0)
GENMASK            47 include/linux/i3c/master.h #define I3C_LVR_I2C_INDEX_MASK		GENMASK(7, 5)
GENMASK            51 include/linux/i3c/master.h #define I2C_MAX_ADDR			GENMASK(6, 0)
GENMASK           893 include/linux/ieee80211.h #define IEEE80211_ADDBA_EXT_FRAG_LEVEL_MASK	GENMASK(2, 1)
GENMASK           138 include/linux/kvm_host.h #define KVM_REQUEST_MASK           GENMASK(7,0)
GENMASK            24 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_MODE_MASK		GENMASK(9, 8)
GENMASK            28 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_GUARDTIME_MASK	GENMASK(20, 16)
GENMASK            43 include/linux/mfd/atmel-hlcdc.h #define ATMEL_HLCDC_CLKDIV_MASK		GENMASK(23, 16)
GENMASK            36 include/linux/mfd/bd9571mwv.h #define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK	GENMASK(3, 0)
GENMASK            31 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_PDBTIME_MASK		GENMASK(31, 25)
GENMASK            37 include/linux/mfd/imx25-tsadc.h #define MX25_TGCR_POWERMODE_MASK	GENMASK(9, 8)
GENMASK            65 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_RWAIT_MASK		GENMASK(15, 12)
GENMASK            67 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_WMRK_MASK		GENMASK(11, 8)
GENMASK            73 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CR_QSM_MASK		GENMASK(1, 0)
GENMASK           106 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CFG_NOS_MASK		GENMASK(19, 16)
GENMASK           123 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CFG_REFP_MASK		GENMASK(8, 7)
GENMASK           138 include/linux/mfd/imx25-tsadc.h #define MX25_ADCQ_CFG_REFN_MASK		GENMASK(3, 2)
GENMASK            15 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ID_MINREV0	GENMASK(2, 0)
GENMASK            16 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ID_MAJREV0	GENMASK(5, 3)
GENMASK            17 include/linux/mfd/intel_soc_pmic_mrfld.h #define BCOVE_ID_VENDID0	GENMASK(7, 6)
GENMASK            51 include/linux/mfd/max77650.h #define MAX77650_CID_MASK		GENMASK(3, 0)
GENMASK            25 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_CMPOK_ARROK		GENMASK(4, 3)
GENMASK            30 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_CMPOKCF_ARROKCF	GENMASK(4, 3)
GENMASK            40 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_PRESC	GENMASK(11, 9)
GENMASK            41 include/linux/mfd/stm32-lptimer.h #define STM32_LPTIM_CKPOL	GENMASK(2, 1)
GENMASK            39 include/linux/mfd/stm32-timers.h #define TIM_CR2_MMS2	GENMASK(23, 20) /* Master mode selection 2 */
GENMASK            55 include/linux/mfd/stm32-timers.h #define TIM_CCMR_IC1PSC		GENMASK(3, 2)	/* Input capture 1 prescaler */
GENMASK            57 include/linux/mfd/stm32-timers.h #define TIM_CCMR_IC2PSC		GENMASK(11, 10)	/* Input capture 2 prescaler */
GENMASK            81 include/linux/mfd/stm32-timers.h #define TIM_DCR_DBA	GENMASK(4, 0)	/* DMA base addr */
GENMASK            82 include/linux/mfd/stm32-timers.h #define TIM_DCR_DBL	GENMASK(12, 8)	/* DMA burst len */
GENMASK            63 include/linux/mfd/stmfx.h #define STMFX_REG_CHIP_ID_MASK		GENMASK(7, 0)
GENMASK           101 include/linux/mfd/stpmic1.h #define LDO_VOLTAGE_MASK		GENMASK(6, 2)
GENMASK           102 include/linux/mfd/stpmic1.h #define BUCK_VOLTAGE_MASK		GENMASK(7, 2)
GENMASK           113 include/linux/mfd/stpmic1.h #define BUCKS_PD_CR_REG_MASK	GENMASK(7, 0)
GENMASK           114 include/linux/mfd/stpmic1.h #define BUCK_MASK_RANK_REGISTER_MASK	GENMASK(3, 0)
GENMASK           115 include/linux/mfd/stpmic1.h #define BUCK_MASK_RESET_REGISTER_MASK	GENMASK(3, 0)
GENMASK           116 include/linux/mfd/stpmic1.h #define LDO1234_PULL_DOWN_REGISTER_MASK	GENMASK(7, 0)
GENMASK           117 include/linux/mfd/stpmic1.h #define LDO56_VREF_PD_CR_REG_MASK	GENMASK(5, 0)
GENMASK           118 include/linux/mfd/stpmic1.h #define LDO_MASK_RANK_REGISTER_MASK	GENMASK(5, 0)
GENMASK           119 include/linux/mfd/stpmic1.h #define LDO_MASK_RESET_REGISTER_MASK	GENMASK(5, 0)
GENMASK           145 include/linux/mfd/stpmic1.h #define BUCKS_ICCTO_CR_REG_MASK	GENMASK(6, 0)
GENMASK           146 include/linux/mfd/stpmic1.h #define LDOS_ICCTO_CR_REG_MASK	GENMASK(5, 0)
GENMASK           177 include/linux/mfd/stpmic1.h #define VINLOW_CTRL_REG_MASK		GENMASK(7, 0)
GENMASK           196 include/linux/mfd/stpmic1.h #define PONKEY_TURNOFF_TIMER_MASK	GENMASK(3, 0)
GENMASK           197 include/linux/mfd/stpmic1.h #define PONKEY_TURNOFF_MASK		GENMASK(7, 0)
GENMASK            12 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x)		((GENMASK(7, 0) & (x)) << 24)
GENMASK            15 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x)		((GENMASK(1, 0) & (x)) << 20)
GENMASK            16 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_FS_DIV(x)			((GENMASK(3, 0) & (x)) << 16)
GENMASK            17 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL0_T_ACQ(x)			(GENMASK(15, 0) & (x))
GENMASK            21 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x)		((GENMASK(7, 0) & (x)) << 12)
GENMASK            27 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x)		(GENMASK(2, 0) & (x))
GENMASK            28 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK			GENMASK(2, 0)
GENMASK            35 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)		(GENMASK(3, 0) & BIT(x))
GENMASK            36 include/linux/mfd/sun4i-gpadc.h #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK			GENMASK(3, 0)
GENMASK            44 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)	((GENMASK(3, 0) & (x)) << 28)
GENMASK            45 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x)		((GENMASK(1, 0) & (x)) << 26)
GENMASK            47 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)		(GENMASK(23, 0) & (x))
GENMASK            52 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)		(GENMASK(1, 0) & (x))
GENMASK            57 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_TPR_TEMP_PERIOD(x)			(GENMASK(15, 0) & (x))
GENMASK            65 include/linux/mfd/sun4i-gpadc.h #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x)	((GENMASK(4, 0) & (x)) << 8)
GENMASK            64 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_ULBT			GENMASK(2, 0)
GENMASK            72 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_SLOT_CYCLE			GENMASK(7,  0)
GENMASK            73 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_DEFMSTR_TYPE		GENMASK(17, 16)
GENMASK            77 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_FIXED_DEFMSTR		GENMASK(20, 18)
GENMASK            78 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_ARBT			GENMASK(25, 24)
GENMASK            82 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_ITCM_SIZE			GENMASK(3, 0)
GENMASK            87 include/linux/mfd/syscon/atmel-matrix.h #define	AT91_MATRIX_DTCM_SIZE			GENMASK(7, 4)
GENMASK            95 include/linux/mfd/syscon/atmel-matrix.h #define AT91_MATRIX_MPR(x)			GENMASK(((x) * 0x4) + 1, ((x) * 0x4))
GENMASK            21 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_ABTSZ			GENMASK(9, 8)
GENMASK            25 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_ABTTYP			GENMASK(11, 10)
GENMASK            35 include/linux/mfd/syscon/atmel-mc.h #define AT91_MPR_MSTP(n)		GENMASK(2 + ((x) * 4), ((x) * 4))
GENMASK            47 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_NWS			GENMASK(6, 0)
GENMASK            50 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_TDF			GENMASK(11, 8)
GENMASK            54 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_DBW			GENMASK(14, 13)
GENMASK            58 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_ACSS		GENMASK(17, 16)
GENMASK            61 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_RWSETUP		GENMASK(26, 24)
GENMASK            63 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SMC_RWHOLD		GENMASK(30, 28)
GENMASK            69 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_MODE		GENMASK(3, 0)
GENMASK            78 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_COUNT		GENMASK(11, 0)
GENMASK            81 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_NC		GENMASK(1, 0)
GENMASK            86 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_NR		GENMASK(3, 2)
GENMASK            93 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_CAS		GENMASK(6, 5)
GENMASK            95 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TWR		GENMASK(10,  7)
GENMASK            96 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TRC		GENMASK(14, 11)
GENMASK            97 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TRP		GENMASK(18, 15)
GENMASK            98 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TRCD		GENMASK(22, 19)
GENMASK            99 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TRAS		GENMASK(26, 23)
GENMASK           100 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_SDRAMC_TXSR		GENMASK(30, 27)
GENMASK           116 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_BFCOM		GENMASK(1, 0)
GENMASK           120 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_BFCC		GENMASK(3, 2)
GENMASK           124 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_AVL			GENMASK(7,  4)
GENMASK           125 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_PAGES		GENMASK(10, 8)
GENMASK           134 include/linux/mfd/syscon/atmel-mc.h #define AT91_MC_BFC_OEL			GENMASK(13, 12)
GENMASK            41 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_EXNWMODE_MASK		GENMASK(5, 4)
GENMASK            48 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_DBW_MASK			GENMASK(13, 12)
GENMASK            52 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_TDF_MASK			GENMASK(19, 16)
GENMASK            58 include/linux/mfd/syscon/atmel-smc.h #define ATMEL_SMC_MODE_PS_MASK			GENMASK(29, 28)
GENMASK            87 include/linux/mfd/tps65086.h #define TPS65086_DEVICEID_PART_MASK	GENMASK(3, 0)
GENMASK            88 include/linux/mfd/tps65086.h #define TPS65086_DEVICEID_OTP_MASK	GENMASK(5, 4)
GENMASK            89 include/linux/mfd/tps65086.h #define TPS65086_DEVICEID_REV_MASK	GENMASK(7, 6)
GENMASK            92 include/linux/mfd/tps65086.h #define BUCK_VID_MASK			GENMASK(7, 1)
GENMASK            93 include/linux/mfd/tps65086.h #define VDOA1_VID_MASK			GENMASK(4, 1)
GENMASK            94 include/linux/mfd/tps65086.h #define VDOA23_VID_MASK			GENMASK(3, 0)
GENMASK            57 include/linux/mfd/tps68470.h #define TPS68470_REG_RESET_MASK		GENMASK(7, 0)
GENMASK            58 include/linux/mfd/tps68470.h #define TPS68470_VAVAL_AVOLT_MASK	GENMASK(6, 0)
GENMASK            60 include/linux/mfd/tps68470.h #define TPS68470_VDVAL_DVOLT_MASK	GENMASK(5, 0)
GENMASK            61 include/linux/mfd/tps68470.h #define TPS68470_VCMVAL_VCVOLT_MASK	GENMASK(6, 0)
GENMASK            62 include/linux/mfd/tps68470.h #define TPS68470_VIOVAL_IOVOLT_MASK	GENMASK(6, 0)
GENMASK            63 include/linux/mfd/tps68470.h #define TPS68470_VSIOVAL_IOVOLT_MASK	GENMASK(6, 0)
GENMASK            64 include/linux/mfd/tps68470.h #define TPS68470_VAUX1VAL_AUX1VOLT_MASK	GENMASK(6, 0)
GENMASK            65 include/linux/mfd/tps68470.h #define TPS68470_VAUX2VAL_AUX2VOLT_MASK	GENMASK(6, 0)
GENMASK            67 include/linux/mfd/tps68470.h #define TPS68470_VACTL_EN_MASK		GENMASK(0, 0)
GENMASK            68 include/linux/mfd/tps68470.h #define TPS68470_VDCTL_EN_MASK		GENMASK(0, 0)
GENMASK            69 include/linux/mfd/tps68470.h #define TPS68470_VCMCTL_EN_MASK		GENMASK(0, 0)
GENMASK            70 include/linux/mfd/tps68470.h #define TPS68470_S_I2C_CTL_EN_MASK	GENMASK(1, 0)
GENMASK            71 include/linux/mfd/tps68470.h #define TPS68470_VAUX1CTL_EN_MASK	GENMASK(0, 0)
GENMASK            72 include/linux/mfd/tps68470.h #define TPS68470_VAUX2CTL_EN_MASK	GENMASK(0, 0)
GENMASK            73 include/linux/mfd/tps68470.h #define TPS68470_PLL_EN_MASK		GENMASK(0, 0)
GENMASK            75 include/linux/mfd/tps68470.h #define TPS68470_CLKCFG1_MODE_A_MASK	GENMASK(1, 0)
GENMASK            76 include/linux/mfd/tps68470.h #define TPS68470_CLKCFG1_MODE_B_MASK	GENMASK(3, 2)
GENMASK            80 include/linux/mfd/tps68470.h #define TPS68470_GPIO_MODE_MASK		GENMASK(1, 0)
GENMASK           416 include/linux/mmc/mmc.h #define EXT_CSD_CMDQ_DEPTH_MASK		GENMASK(4, 0)
GENMASK           154 include/linux/mtd/spi-nor.h #define SNOR_PROTO_INST_MASK	GENMASK(23, 16)
GENMASK           160 include/linux/mtd/spi-nor.h #define SNOR_PROTO_ADDR_MASK	GENMASK(15, 8)
GENMASK           166 include/linux/mtd/spi-nor.h #define SNOR_PROTO_DATA_MASK	GENMASK(7, 0)
GENMASK           352 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_MASK		GENMASK(14, 0)
GENMASK           357 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_DUAL		GENMASK(6, 3)
GENMASK           363 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_QUAD		GENMASK(10, 7)
GENMASK           369 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_READ_OCTAL		GENMASK(14, 11)
GENMASK           384 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_MASK	GENMASK(22, 16)
GENMASK           387 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_QUAD	GENMASK(19, 17)
GENMASK           392 include/linux/mtd/spi-nor.h #define SNOR_HWCAPS_PP_OCTAL	GENMASK(22, 20)
GENMASK           164 include/linux/mtd/spinand.h #define STATUS_ECC_MASK		GENMASK(5, 4)
GENMASK            31 include/linux/olpc-ec.h #define EC_SCI_SRC_ALL          GENMASK(8, 0)
GENMASK           202 include/linux/phy.h #define MII_REGADDR_C45_MASK	GENMASK(15, 0)
GENMASK           641 include/linux/phy.h #define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
GENMASK           642 include/linux/phy.h #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
GENMASK           643 include/linux/phy.h #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
GENMASK            62 include/linux/platform_data/dma-dw.h #define CHAN_PROTCTL_MASK		GENMASK(2, 0)
GENMASK            90 include/linux/qcom-geni-se.h #define CLK_DIV_MSK			GENMASK(15, 4)
GENMASK            94 include/linux/qcom-geni-se.h #define FW_REV_PROTOCOL_MSK		GENMASK(15, 8)
GENMASK            98 include/linux/qcom-geni-se.h #define CLK_SEL_MSK			GENMASK(2, 0)
GENMASK           104 include/linux/qcom-geni-se.h #define M_OPCODE_MSK			GENMASK(31, 27)
GENMASK           106 include/linux/qcom-geni-se.h #define M_PARAMS_MSK			GENMASK(26, 0)
GENMASK           114 include/linux/qcom-geni-se.h #define S_OPCODE_MSK			GENMASK(31, 27)
GENMASK           116 include/linux/qcom-geni-se.h #define S_PARAMS_MSK			GENMASK(26, 0)
GENMASK           149 include/linux/qcom-geni-se.h #define M_COMMON_GENI_M_IRQ_EN	(GENMASK(6, 1) | \
GENMASK           175 include/linux/qcom-geni-se.h #define S_COMMON_GENI_S_IRQ_EN	(GENMASK(5, 1) | GENMASK(13, 9) | \
GENMASK           179 include/linux/qcom-geni-se.h #define WATERMARK_MSK			GENMASK(5, 0)
GENMASK           182 include/linux/qcom-geni-se.h #define TX_FIFO_WC			GENMASK(27, 0)
GENMASK           186 include/linux/qcom-geni-se.h #define RX_LAST_BYTE_VALID_MSK		GENMASK(30, 28)
GENMASK           188 include/linux/qcom-geni-se.h #define RX_FIFO_WC_MSK			GENMASK(24, 0)
GENMASK           206 include/linux/qcom-geni-se.h #define RX_GENI_GP_IRQ			GENMASK(10, 5)
GENMASK           208 include/linux/qcom-geni-se.h #define RX_GENI_GP_IRQ_EXT		GENMASK(13, 12)
GENMASK           211 include/linux/qcom-geni-se.h #define TX_FIFO_WIDTH_MSK		GENMASK(29, 24)
GENMASK           213 include/linux/qcom-geni-se.h #define TX_FIFO_DEPTH_MSK		GENMASK(21, 16)
GENMASK           217 include/linux/qcom-geni-se.h #define RX_FIFO_WIDTH_MSK		GENMASK(29, 24)
GENMASK           219 include/linux/qcom-geni-se.h #define RX_FIFO_DEPTH_MSK		GENMASK(21, 16)
GENMASK           222 include/linux/qcom-geni-se.h #define HW_VER_MAJOR_MASK		GENMASK(31, 28)
GENMASK           224 include/linux/qcom-geni-se.h #define HW_VER_MINOR_MASK		GENMASK(27, 16)
GENMASK           226 include/linux/qcom-geni-se.h #define HW_VER_STEP_MASK		GENMASK(15, 0)
GENMASK            65 include/linux/soundwire/sdw.h #define SDW_PORT_FLOW_MODE_ASYNC	GENMASK(1, 0)
GENMASK            17 include/linux/soundwire/sdw_registers.h #define SDW_REGADDR				GENMASK(14, 0)
GENMASK            18 include/linux/soundwire/sdw_registers.h #define SDW_SCP_ADDRPAGE2_MASK			GENMASK(22, 15)
GENMASK            19 include/linux/soundwire/sdw_registers.h #define SDW_SCP_ADDRPAGE1_MASK			GENMASK(30, 23)
GENMASK            50 include/linux/soundwire/sdw_registers.h #define SDW_DP0_PORTCTRL_DATAMODE		GENMASK(3, 2)
GENMASK            52 include/linux/soundwire/sdw_registers.h #define SDW_DP0_PORTCTRL_BPT_PAYLD		GENMASK(7, 6)
GENMASK            70 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INT1_PORT0_3			GENMASK(6, 3)
GENMASK            74 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INTSTAT2_PORT4_10		GENMASK(6, 0)
GENMASK            77 include/linux/soundwire/sdw_registers.h #define SDW_SCP_INTSTAT3_PORT11_14		GENMASK(3, 0)
GENMASK           137 include/linux/soundwire/sdw_registers.h #define SDW_DPN_PORTCTRL_FLOWMODE		GENMASK(1, 0)
GENMASK           138 include/linux/soundwire/sdw_registers.h #define SDW_DPN_PORTCTRL_DATAMODE		GENMASK(3, 2)
GENMASK           141 include/linux/soundwire/sdw_registers.h #define SDW_DPN_BLOCKCTRL1_WDLEN		GENMASK(5, 0)
GENMASK           143 include/linux/soundwire/sdw_registers.h #define SDW_DPN_PREPARECTRL_CH_PREP		GENMASK(7, 0)
GENMASK           172 include/linux/soundwire/sdw_registers.h #define SDW_DPN_SAMPLECTRL_LOW			GENMASK(7, 0)
GENMASK           173 include/linux/soundwire/sdw_registers.h #define SDW_DPN_SAMPLECTRL_HIGH			GENMASK(15, 8)
GENMASK           175 include/linux/soundwire/sdw_registers.h #define SDW_DPN_HCTRL_HSTART			GENMASK(7, 4)
GENMASK           176 include/linux/soundwire/sdw_registers.h #define SDW_DPN_HCTRL_HSTOP			GENMASK(3, 0)
GENMASK           453 include/linux/spi/spi.h #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
GENMASK            74 include/linux/usb/typec_dp.h #define DP_CAP_DFP_D_PIN_ASSIGN(_cap_)	(((_cap_) & GENMASK(15, 8)) >> 8)
GENMASK            75 include/linux/usb/typec_dp.h #define DP_CAP_UFP_D_PIN_ASSIGN(_cap_)	(((_cap_) & GENMASK(23, 16)) >> 16)
GENMASK            98 include/linux/usb/typec_dp.h #define DP_CONF_PIN_ASSIGNEMENT_MASK	GENMASK(15, 8)
GENMASK           102 include/linux/usb/typec_dp.h #define DP_CONF_GET_PIN_ASSIGN(_conf_)	(((_conf_) & GENMASK(15, 8)) >> 8)
GENMASK           100 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
GENMASK           103 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
GENMASK           107 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
GENMASK           112 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
GENMASK           117 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
GENMASK           122 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
GENMASK           127 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
GENMASK           132 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
GENMASK           137 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
GENMASK           142 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
GENMASK           145 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
GENMASK           148 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
GENMASK           153 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
GENMASK           158 include/media/drv-intf/cx25840.h #define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
GENMASK            66 include/net/ip_tunnels.h 	GENMASK((FIELD_SIZEOF(struct ip_tunnel_info,		\
GENMASK           157 include/rdma/uverbs_ioctl.h 	UVERBS_API_ATTR_KEY_MASK = GENMASK(UVERBS_API_ATTR_KEY_BITS - 1, 0),
GENMASK           169 include/rdma/uverbs_ioctl.h 	UVERBS_API_METHOD_KEY_MASK = GENMASK(
GENMASK           179 include/rdma/uverbs_ioctl.h 	UVERBS_API_OBJ_KEY_MASK = GENMASK(31, UVERBS_API_OBJ_KEY_SHIFT),
GENMASK            37 include/soc/at91/atmel-sfr.h #define AT91_OHCIICR_USB_SUSPEND		GENMASK(10, 8)
GENMASK            41 include/soc/at91/atmel-sfr.h #define AT91_UTMICKTRIM_FREQ			GENMASK(1, 0)
GENMASK            49 include/soc/at91/atmel-sfr.h #define AT91_SFR_WPMR_WPKEY_MASK		GENMASK(31, 8)
GENMASK            92 include/soc/fsl/qman.h #define QM_FD_FORMAT_MASK	GENMASK(31, 29)
GENMASK            94 include/soc/fsl/qman.h #define QM_FD_OFF_MASK		GENMASK(28, 20)
GENMASK            95 include/soc/fsl/qman.h #define QM_FD_LEN_MASK		GENMASK(19, 0)
GENMASK            96 include/soc/fsl/qman.h #define QM_FD_LEN_BIG_MASK	GENMASK(28, 0)
GENMASK           196 include/soc/fsl/qman.h #define QM_SG_LEN_MASK	GENMASK(29, 0)
GENMASK           197 include/soc/fsl/qman.h #define QM_SG_OFF_MASK	GENMASK(12, 0)
GENMASK           270 include/soc/fsl/qman.h #define QM_FQID_MASK	GENMASK(23, 0)
GENMASK           387 include/soc/fsl/qman.h #define QM_FQD_WQ_MASK		GENMASK(2, 0)
GENMASK           388 include/soc/fsl/qman.h #define QM_FQD_TD_EXP_MASK	GENMASK(4, 0)
GENMASK           390 include/soc/fsl/qman.h #define QM_FQD_TD_MANT_MASK	GENMASK(12, 5)
GENMASK            90 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELBGV820(x)                      (((x) << 23) & GENMASK(26, 23))
GENMASK            91 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELBGV820_M                       GENMASK(26, 23)
GENMASK            92 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELBGV820_X(x)                    (((x) & GENMASK(26, 23)) >> 23)
GENMASK            93 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x)                    (((x) << 18) & GENMASK(22, 18))
GENMASK            94 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M                     GENMASK(22, 18)
GENMASK            95 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x)                  (((x) & GENMASK(22, 18)) >> 18)
GENMASK            96 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELCPI(x)                         (((x) << 16) & GENMASK(17, 16))
GENMASK            97 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELCPI_M                          GENMASK(17, 16)
GENMASK            98 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_SELCPI_X(x)                       (((x) & GENMASK(17, 16)) >> 16)
GENMASK           103 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x)                    (((x) << 6) & GENMASK(11, 6))
GENMASK           104 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M                     GENMASK(11, 6)
GENMASK           105 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x)                  (((x) & GENMASK(11, 6)) >> 6)
GENMASK           106 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x)                   ((x) & GENMASK(5, 0))
GENMASK           107 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M                    GENMASK(5, 0)
GENMASK           114 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x)                   (((x) << 6) & GENMASK(13, 6))
GENMASK           115 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M                    GENMASK(13, 6)
GENMASK           116 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x)                 (((x) & GENMASK(13, 6)) >> 6)
GENMASK           131 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_AMPC_SEL(x)                       (((x) << 16) & GENMASK(23, 16))
GENMASK           132 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_AMPC_SEL_M                        GENMASK(23, 16)
GENMASK           133 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_AMPC_SEL_X(x)                     (((x) & GENMASK(23, 16)) >> 16)
GENMASK           140 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_GAIN_TEST(x)                      (((x) << 5) & GENMASK(9, 5))
GENMASK           141 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_GAIN_TEST_M                       GENMASK(9, 5)
GENMASK           142 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG2_GAIN_TEST_X(x)                    (((x) & GENMASK(9, 5)) >> 5)
GENMASK           149 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x)               (((x) << 22) & GENMASK(23, 22))
GENMASK           150 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M                GENMASK(23, 22)
GENMASK           151 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x)             (((x) & GENMASK(23, 22)) >> 22)
GENMASK           152 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TESTOUT_SEL(x)                    (((x) << 19) & GENMASK(21, 19))
GENMASK           153 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TESTOUT_SEL_M                     GENMASK(21, 19)
GENMASK           154 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x)                  (((x) & GENMASK(21, 19)) >> 19)
GENMASK           166 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FBDIVSEL(x)                       ((x) & GENMASK(7, 0))
GENMASK           167 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG3_FBDIVSEL_M                        GENMASK(7, 0)
GENMASK           169 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x)                   (((x) << 16) & GENMASK(23, 16))
GENMASK           170 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M                    GENMASK(23, 16)
GENMASK           171 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x)                 (((x) & GENMASK(23, 16)) >> 16)
GENMASK           172 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG4_IB_CTRL(x)                        ((x) & GENMASK(15, 0))
GENMASK           173 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG4_IB_CTRL_M                         GENMASK(15, 0)
GENMASK           175 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x)                   (((x) << 16) & GENMASK(23, 16))
GENMASK           176 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M                    GENMASK(23, 16)
GENMASK           177 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x)                 (((x) & GENMASK(23, 16)) >> 16)
GENMASK           178 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG5_OB_CTRL(x)                        ((x) & GENMASK(15, 0))
GENMASK           179 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG5_OB_CTRL_M                         GENMASK(15, 0)
GENMASK           182 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_REFCLK_SEL(x)                     (((x) << 20) & GENMASK(22, 20))
GENMASK           183 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_REFCLK_SEL_M                      GENMASK(22, 20)
GENMASK           184 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x)                   (((x) & GENMASK(22, 20)) >> 20)
GENMASK           186 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_POR_DEL_SEL(x)                    (((x) << 16) & GENMASK(17, 16))
GENMASK           187 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_POR_DEL_SEL_M                     GENMASK(17, 16)
GENMASK           188 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x)                  (((x) & GENMASK(17, 16)) >> 16)
GENMASK           189 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_DIV125REF_SEL(x)                  (((x) << 8) & GENMASK(15, 8))
GENMASK           190 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_DIV125REF_SEL_M                   GENMASK(15, 8)
GENMASK           191 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x)                (((x) & GENMASK(15, 8)) >> 8)
GENMASK           194 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x)                    ((x) & GENMASK(5, 0))
GENMASK           195 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M                     GENMASK(5, 0)
GENMASK           201 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_READBACK_DATA(x)               (((x) << 1) & GENMASK(8, 1))
GENMASK           202 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_READBACK_DATA_M                GENMASK(8, 1)
GENMASK           203 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x)             (((x) & GENMASK(8, 1)) >> 1)
GENMASK           206 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_SIG_DEL(x)                     (((x) << 21) & GENMASK(28, 21))
GENMASK           207 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_SIG_DEL_M                      GENMASK(28, 21)
GENMASK           208 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_SIG_DEL_X(x)                   (((x) & GENMASK(28, 21)) >> 21)
GENMASK           209 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_GAIN_STAT(x)                   (((x) << 16) & GENMASK(20, 16))
GENMASK           210 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_GAIN_STAT_M                    GENMASK(20, 16)
GENMASK           211 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x)                 (((x) & GENMASK(20, 16)) >> 16)
GENMASK           212 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FBCNT_DIF(x)                   (((x) << 4) & GENMASK(13, 4))
GENMASK           213 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FBCNT_DIF_M                    GENMASK(13, 4)
GENMASK           214 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x)                 (((x) & GENMASK(13, 4)) >> 4)
GENMASK           215 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FSM_STAT(x)                    (((x) << 1) & GENMASK(3, 1))
GENMASK           216 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FSM_STAT_M                     GENMASK(3, 1)
GENMASK           217 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_STATUS1_FSM_STAT_X(x)                  (((x) & GENMASK(3, 1)) >> 1)
GENMASK           222 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x)          (((x) << 20) & GENMASK(23, 20))
GENMASK           223 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M           GENMASK(23, 20)
GENMASK           224 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x)        (((x) & GENMASK(23, 20)) >> 20)
GENMASK           225 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x)          (((x) << 16) & GENMASK(19, 16))
GENMASK           226 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M           GENMASK(19, 16)
GENMASK           227 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x)        (((x) & GENMASK(19, 16)) >> 16)
GENMASK           228 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x)       ((x) & GENMASK(15, 0))
GENMASK           229 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M        GENMASK(15, 0)
GENMASK           231 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x)            (((x) << 4) & GENMASK(7, 4))
GENMASK           232 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M             GENMASK(7, 4)
GENMASK           233 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x)          (((x) & GENMASK(7, 4)) >> 4)
GENMASK           238 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x)             (((x) << 16) & GENMASK(31, 16))
GENMASK           239 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M              GENMASK(31, 16)
GENMASK           240 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x)           (((x) & GENMASK(31, 16)) >> 16)
GENMASK           241 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x)        ((x) & GENMASK(15, 0))
GENMASK           242 include/soc/mscc/ocelot_hsio.h #define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M         GENMASK(15, 0)
GENMASK           246 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_SPEED_SEL(x)                      (((x) << 10) & GENMASK(11, 10))
GENMASK           247 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_SPEED_SEL_M                       GENMASK(11, 10)
GENMASK           248 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_SPEED_SEL_X(x)                    (((x) & GENMASK(11, 10)) >> 10)
GENMASK           249 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_MODE_SEL(x)                       (((x) << 8) & GENMASK(9, 8))
GENMASK           250 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_MODE_SEL_M                        GENMASK(9, 8)
GENMASK           251 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_MODE_SEL_X(x)                     (((x) & GENMASK(9, 8)) >> 8)
GENMASK           253 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_RCOMP_VAL(x)                      ((x) & GENMASK(3, 0))
GENMASK           254 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_CFG0_RCOMP_VAL_M                       GENMASK(3, 0)
GENMASK           258 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_STATUS_RCOMP(x)                        ((x) & GENMASK(3, 0))
GENMASK           259 include/soc/mscc/ocelot_hsio.h #define HSIO_RCOMP_STATUS_RCOMP_M                         GENMASK(3, 0)
GENMASK           263 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x)             (((x) << 4) & GENMASK(7, 4))
GENMASK           264 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M              GENMASK(7, 4)
GENMASK           265 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x)           (((x) & GENMASK(7, 4)) >> 4)
GENMASK           266 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x)             (((x) << 1) & GENMASK(3, 1))
GENMASK           267 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M              GENMASK(3, 1)
GENMASK           268 include/soc/mscc/ocelot_hsio.h #define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x)           (((x) & GENMASK(3, 1)) >> 1)
GENMASK           273 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x)                  (((x) << 13) & GENMASK(16, 13))
GENMASK           274 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M                   GENMASK(16, 13)
GENMASK           275 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x)                (((x) & GENMASK(16, 13)) >> 13)
GENMASK           276 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x)                  (((x) << 11) & GENMASK(12, 11))
GENMASK           277 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M                   GENMASK(12, 11)
GENMASK           278 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x)                (((x) & GENMASK(12, 11)) >> 11)
GENMASK           279 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x)                 (((x) << 8) & GENMASK(10, 8))
GENMASK           280 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M                  GENMASK(10, 8)
GENMASK           281 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x)               (((x) & GENMASK(10, 8)) >> 8)
GENMASK           282 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_ANA(x)                    (((x) << 5) & GENMASK(7, 5))
GENMASK           283 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_ANA_M                     GENMASK(7, 5)
GENMASK           284 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x)                  (((x) & GENMASK(7, 5)) >> 5)
GENMASK           286 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_HYST(x)                   (((x) << 1) & GENMASK(3, 1))
GENMASK           287 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_HYST_M                    GENMASK(3, 1)
GENMASK           288 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x)                 (((x) & GENMASK(3, 1)) >> 1)
GENMASK           292 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_ACJTAG_HYST(x)                    (((x) << 24) & GENMASK(26, 24))
GENMASK           293 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_ACJTAG_HYST_M                     GENMASK(26, 24)
GENMASK           294 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x)                  (((x) & GENMASK(26, 24)) >> 24)
GENMASK           295 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_DET_LEV(x)                     (((x) << 19) & GENMASK(21, 19))
GENMASK           296 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_DET_LEV_M                      GENMASK(21, 19)
GENMASK           297 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x)                   (((x) & GENMASK(21, 19)) >> 19)
GENMASK           304 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x)                     (((x) << 6) & GENMASK(8, 6))
GENMASK           305 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M                      GENMASK(8, 6)
GENMASK           306 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x)                   (((x) & GENMASK(8, 6)) >> 6)
GENMASK           307 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x)             (((x) << 4) & GENMASK(5, 4))
GENMASK           308 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M              GENMASK(5, 4)
GENMASK           309 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x)           (((x) & GENMASK(5, 4)) >> 4)
GENMASK           310 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x)               ((x) & GENMASK(3, 0))
GENMASK           311 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M                GENMASK(3, 0)
GENMASK           313 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_SLP(x)                         (((x) << 17) & GENMASK(18, 17))
GENMASK           314 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_SLP_M                          GENMASK(18, 17)
GENMASK           315 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_SLP_X(x)                       (((x) & GENMASK(18, 17)) >> 17)
GENMASK           316 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x)                    (((x) << 13) & GENMASK(16, 13))
GENMASK           317 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M                     GENMASK(16, 13)
GENMASK           318 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x)                  (((x) & GENMASK(16, 13)) >> 13)
GENMASK           319 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x)               (((x) << 10) & GENMASK(12, 10))
GENMASK           320 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M                GENMASK(12, 10)
GENMASK           321 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x)             (((x) & GENMASK(12, 10)) >> 10)
GENMASK           324 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x)                    (((x) << 4) & GENMASK(7, 4))
GENMASK           325 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M                     GENMASK(7, 4)
GENMASK           326 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x)                  (((x) & GENMASK(7, 4)) >> 4)
GENMASK           327 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x)               ((x) & GENMASK(3, 0))
GENMASK           328 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M                GENMASK(3, 0)
GENMASK           334 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_ALISEL(x)                    (((x) << 4) & GENMASK(5, 4))
GENMASK           335 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_ALISEL_M                     GENMASK(5, 4)
GENMASK           336 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_SER_CFG_SER_ALISEL_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
GENMASK           347 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_LANE_CTRL(x)                  (((x) << 13) & GENMASK(15, 13))
GENMASK           348 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_LANE_CTRL_M                   GENMASK(15, 13)
GENMASK           349 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x)                (((x) & GENMASK(15, 13)) >> 13)
GENMASK           360 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x)             (((x) << 8) & GENMASK(15, 8))
GENMASK           361 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M              GENMASK(15, 8)
GENMASK           362 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x)           (((x) & GENMASK(15, 8)) >> 8)
GENMASK           371 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x)                ((x) & GENMASK(7, 0))
GENMASK           372 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M                 GENMASK(7, 0)
GENMASK           376 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_PRBS_SEL(x)                     (((x) << 20) & GENMASK(21, 20))
GENMASK           377 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_PRBS_SEL_M                      GENMASK(21, 20)
GENMASK           378 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x)                   (((x) & GENMASK(21, 20)) >> 20)
GENMASK           379 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_TEST_MODE(x)                    (((x) << 16) & GENMASK(18, 16))
GENMASK           380 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_TEST_MODE_M                     GENMASK(18, 16)
GENMASK           381 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x)                  (((x) & GENMASK(18, 16)) >> 16)
GENMASK           387 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x)               (((x) << 8) & GENMASK(17, 8))
GENMASK           388 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M                GENMASK(17, 8)
GENMASK           389 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x)             (((x) & GENMASK(17, 8)) >> 8)
GENMASK           390 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x)                 (((x) << 4) & GENMASK(7, 4))
GENMASK           391 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M                  GENMASK(7, 4)
GENMASK           392 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x)               (((x) & GENMASK(7, 4)) >> 4)
GENMASK           398 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x)               (((x) << 8) & GENMASK(17, 8))
GENMASK           399 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M                GENMASK(17, 8)
GENMASK           400 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x)             (((x) & GENMASK(17, 8)) >> 8)
GENMASK           401 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x)                 (((x) << 4) & GENMASK(7, 4))
GENMASK           402 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M                  GENMASK(7, 4)
GENMASK           403 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x)               (((x) & GENMASK(7, 4)) >> 4)
GENMASK           410 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x)     (((x) << 16) & GENMASK(17, 16))
GENMASK           411 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M      GENMASK(17, 16)
GENMASK           412 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x)   (((x) & GENMASK(17, 16)) >> 16)
GENMASK           413 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x)         (((x) << 8) & GENMASK(15, 8))
GENMASK           414 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M          GENMASK(15, 8)
GENMASK           415 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x)       (((x) & GENMASK(15, 8)) >> 8)
GENMASK           416 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x)          ((x) & GENMASK(7, 0))
GENMASK           417 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M           GENMASK(7, 0)
GENMASK           419 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x)          (((x) << 11) & GENMASK(12, 11))
GENMASK           420 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M           GENMASK(12, 11)
GENMASK           421 include/soc/mscc/ocelot_hsio.h #define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x)        (((x) & GENMASK(12, 11)) >> 11)
GENMASK           443 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x)            ((x) & GENMASK(8, 0))
GENMASK           444 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M             GENMASK(8, 0)
GENMASK           446 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_GP(x)                            (((x) << 16) & GENMASK(18, 16))
GENMASK           447 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_GP_M                             GENMASK(18, 16)
GENMASK           448 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_GP_X(x)                          (((x) & GENMASK(18, 16)) >> 16)
GENMASK           451 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_AST(x)                    (((x) << 3) & GENMASK(5, 3))
GENMASK           452 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_AST_M                     GENMASK(5, 3)
GENMASK           453 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x)                  (((x) & GENMASK(5, 3)) >> 3)
GENMASK           454 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_DST(x)                    ((x) & GENMASK(2, 0))
GENMASK           455 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DIG_CFG_SIGDET_DST_M                     GENMASK(2, 0)
GENMASK           459 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_PRBS_SEL(x)                     (((x) << 20) & GENMASK(21, 20))
GENMASK           460 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_PRBS_SEL_M                      GENMASK(21, 20)
GENMASK           461 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x)                   (((x) & GENMASK(21, 20)) >> 20)
GENMASK           462 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_TEST_MODE(x)                    (((x) << 16) & GENMASK(18, 16))
GENMASK           463 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_TEST_MODE_M                     GENMASK(18, 16)
GENMASK           464 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x)                  (((x) & GENMASK(18, 16)) >> 16)
GENMASK           470 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x)               (((x) << 8) & GENMASK(17, 8))
GENMASK           471 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M                GENMASK(17, 8)
GENMASK           472 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x)             (((x) & GENMASK(17, 8)) >> 8)
GENMASK           473 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x)                 (((x) << 4) & GENMASK(7, 4))
GENMASK           474 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M                  GENMASK(7, 4)
GENMASK           475 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x)               (((x) & GENMASK(7, 4)) >> 4)
GENMASK           481 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x)               (((x) << 8) & GENMASK(17, 8))
GENMASK           482 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M                GENMASK(17, 8)
GENMASK           483 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x)             (((x) & GENMASK(17, 8)) >> 8)
GENMASK           484 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x)                 (((x) << 4) & GENMASK(7, 4))
GENMASK           485 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M                  GENMASK(7, 4)
GENMASK           486 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x)               (((x) & GENMASK(7, 4)) >> 4)
GENMASK           493 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x)     (((x) << 16) & GENMASK(19, 16))
GENMASK           494 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M      GENMASK(19, 16)
GENMASK           495 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x)   (((x) & GENMASK(19, 16)) >> 16)
GENMASK           496 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x)         (((x) << 8) & GENMASK(15, 8))
GENMASK           497 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M          GENMASK(15, 8)
GENMASK           498 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x)       (((x) & GENMASK(15, 8)) >> 8)
GENMASK           499 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x)          ((x) & GENMASK(7, 0))
GENMASK           500 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M           GENMASK(7, 0)
GENMASK           502 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x)                 (((x) << 13) & GENMASK(14, 13))
GENMASK           503 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M                  GENMASK(14, 13)
GENMASK           504 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x)               (((x) & GENMASK(14, 13)) >> 13)
GENMASK           505 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x)          (((x) << 11) & GENMASK(12, 11))
GENMASK           506 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M           GENMASK(12, 11)
GENMASK           507 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x)        (((x) & GENMASK(12, 11)) >> 11)
GENMASK           519 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x)               (((x) << 23) & GENMASK(28, 23))
GENMASK           520 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M                GENMASK(28, 23)
GENMASK           521 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x)             (((x) & GENMASK(28, 23)) >> 23)
GENMASK           522 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x)               (((x) << 18) & GENMASK(22, 18))
GENMASK           523 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M                GENMASK(22, 18)
GENMASK           524 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x)             (((x) & GENMASK(22, 18)) >> 18)
GENMASK           525 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x)                (((x) << 13) & GENMASK(17, 13))
GENMASK           526 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M                 GENMASK(17, 13)
GENMASK           527 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x)              (((x) & GENMASK(17, 13)) >> 13)
GENMASK           528 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x)             (((x) << 6) & GENMASK(8, 6))
GENMASK           529 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M              GENMASK(8, 6)
GENMASK           530 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x)           (((x) & GENMASK(8, 6)) >> 6)
GENMASK           531 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x)                 ((x) & GENMASK(5, 0))
GENMASK           532 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M                  GENMASK(5, 0)
GENMASK           545 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x)                  (((x) << 13) & GENMASK(16, 13))
GENMASK           546 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M                   GENMASK(16, 13)
GENMASK           547 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x)                (((x) & GENMASK(16, 13)) >> 13)
GENMASK           548 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x)                 (((x) << 10) & GENMASK(12, 10))
GENMASK           549 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M                  GENMASK(12, 10)
GENMASK           550 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x)               (((x) & GENMASK(12, 10)) >> 10)
GENMASK           551 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x)                  (((x) << 8) & GENMASK(9, 8))
GENMASK           552 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M                   GENMASK(9, 8)
GENMASK           553 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x)                (((x) & GENMASK(9, 8)) >> 8)
GENMASK           554 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_HYST(x)                   (((x) << 5) & GENMASK(7, 5))
GENMASK           555 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_HYST_M                    GENMASK(7, 5)
GENMASK           556 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x)                 (((x) & GENMASK(7, 5)) >> 5)
GENMASK           558 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_ANA(x)                    (((x) << 1) & GENMASK(3, 1))
GENMASK           559 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_ANA_M                     GENMASK(3, 1)
GENMASK           560 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x)                  (((x) & GENMASK(3, 1)) >> 1)
GENMASK           563 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SOFSI(x)                       (((x) << 29) & GENMASK(30, 29))
GENMASK           564 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SOFSI_M                        GENMASK(30, 29)
GENMASK           565 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SOFSI_X(x)                     (((x) & GENMASK(30, 29)) >> 29)
GENMASK           567 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x)                    (((x) << 24) & GENMASK(27, 24))
GENMASK           568 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M                     GENMASK(27, 24)
GENMASK           569 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x)                  (((x) & GENMASK(27, 24)) >> 24)
GENMASK           570 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x)                    (((x) << 20) & GENMASK(23, 20))
GENMASK           571 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M                     GENMASK(23, 20)
GENMASK           572 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x)                  (((x) & GENMASK(23, 20)) >> 20)
GENMASK           573 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x)               (((x) << 18) & GENMASK(19, 18))
GENMASK           574 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M                GENMASK(19, 18)
GENMASK           575 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x)             (((x) & GENMASK(19, 18)) >> 18)
GENMASK           576 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x)             (((x) << 15) & GENMASK(17, 15))
GENMASK           577 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M              GENMASK(17, 15)
GENMASK           578 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x)           (((x) & GENMASK(17, 15)) >> 15)
GENMASK           579 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x)              (((x) << 13) & GENMASK(14, 13))
GENMASK           580 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M               GENMASK(14, 13)
GENMASK           581 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x)            (((x) & GENMASK(14, 13)) >> 13)
GENMASK           582 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x)             (((x) << 11) & GENMASK(12, 11))
GENMASK           583 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M              GENMASK(12, 11)
GENMASK           584 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x)           (((x) & GENMASK(12, 11)) >> 11)
GENMASK           585 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x)              (((x) << 9) & GENMASK(10, 9))
GENMASK           586 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M               GENMASK(10, 9)
GENMASK           587 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x)            (((x) & GENMASK(10, 9)) >> 9)
GENMASK           588 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x)          (((x) << 7) & GENMASK(8, 7))
GENMASK           589 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M           GENMASK(8, 7)
GENMASK           590 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x)        (((x) & GENMASK(8, 7)) >> 7)
GENMASK           599 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TJTAG(x)                      (((x) << 17) & GENMASK(21, 17))
GENMASK           600 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TJTAG_M                       GENMASK(21, 17)
GENMASK           601 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x)                    (((x) & GENMASK(21, 17)) >> 17)
GENMASK           602 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TSDET(x)                      (((x) << 12) & GENMASK(16, 12))
GENMASK           603 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TSDET_M                       GENMASK(16, 12)
GENMASK           604 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_TSDET_X(x)                    (((x) & GENMASK(16, 12)) >> 12)
GENMASK           605 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_SCALY(x)                      (((x) << 8) & GENMASK(11, 8))
GENMASK           606 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_SCALY_M                       GENMASK(11, 8)
GENMASK           607 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG1_IB_SCALY_X(x)                    (((x) & GENMASK(11, 8)) >> 8)
GENMASK           617 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TINFV(x)                      (((x) << 27) & GENMASK(29, 27))
GENMASK           618 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TINFV_M                       GENMASK(29, 27)
GENMASK           619 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TINFV_X(x)                    (((x) & GENMASK(29, 27)) >> 27)
GENMASK           620 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFI(x)                      (((x) << 22) & GENMASK(26, 22))
GENMASK           621 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFI_M                       GENMASK(26, 22)
GENMASK           622 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFI_X(x)                    (((x) & GENMASK(26, 22)) >> 22)
GENMASK           623 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TAUX(x)                       (((x) << 19) & GENMASK(21, 19))
GENMASK           624 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TAUX_M                        GENMASK(21, 19)
GENMASK           625 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TAUX_X(x)                     (((x) & GENMASK(21, 19)) >> 19)
GENMASK           626 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFS(x)                      (((x) << 16) & GENMASK(18, 16))
GENMASK           627 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFS_M                       GENMASK(18, 16)
GENMASK           628 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OINFS_X(x)                    (((x) & GENMASK(18, 16)) >> 16)
GENMASK           629 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OCALS(x)                      (((x) << 10) & GENMASK(15, 10))
GENMASK           630 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OCALS_M                       GENMASK(15, 10)
GENMASK           631 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_OCALS_X(x)                    (((x) & GENMASK(15, 10)) >> 10)
GENMASK           632 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TCALV(x)                      (((x) << 5) & GENMASK(9, 5))
GENMASK           633 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TCALV_M                       GENMASK(9, 5)
GENMASK           634 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_TCALV_X(x)                    (((x) & GENMASK(9, 5)) >> 5)
GENMASK           635 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_UMAX(x)                       (((x) << 3) & GENMASK(4, 3))
GENMASK           636 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_UMAX_M                        GENMASK(4, 3)
GENMASK           637 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_UMAX_X(x)                     (((x) & GENMASK(4, 3)) >> 3)
GENMASK           638 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_UREG(x)                       ((x) & GENMASK(2, 0))
GENMASK           639 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG2_IB_UREG_M                        GENMASK(2, 0)
GENMASK           641 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_HP(x)                     (((x) << 18) & GENMASK(23, 18))
GENMASK           642 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_HP_M                      GENMASK(23, 18)
GENMASK           643 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x)                   (((x) & GENMASK(23, 18)) >> 18)
GENMASK           644 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_MID(x)                    (((x) << 12) & GENMASK(17, 12))
GENMASK           645 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_MID_M                     GENMASK(17, 12)
GENMASK           646 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x)                  (((x) & GENMASK(17, 12)) >> 12)
GENMASK           647 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_LP(x)                     (((x) << 6) & GENMASK(11, 6))
GENMASK           648 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_LP_M                      GENMASK(11, 6)
GENMASK           649 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x)                   (((x) & GENMASK(11, 6)) >> 6)
GENMASK           650 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x)                 ((x) & GENMASK(5, 0))
GENMASK           651 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M                  GENMASK(5, 0)
GENMASK           653 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_HP(x)                     (((x) << 18) & GENMASK(23, 18))
GENMASK           654 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_HP_M                      GENMASK(23, 18)
GENMASK           655 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x)                   (((x) & GENMASK(23, 18)) >> 18)
GENMASK           656 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_MID(x)                    (((x) << 12) & GENMASK(17, 12))
GENMASK           657 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_MID_M                     GENMASK(17, 12)
GENMASK           658 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x)                  (((x) & GENMASK(17, 12)) >> 12)
GENMASK           659 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_LP(x)                     (((x) << 6) & GENMASK(11, 6))
GENMASK           660 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_LP_M                      GENMASK(11, 6)
GENMASK           661 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x)                   (((x) & GENMASK(11, 6)) >> 6)
GENMASK           662 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x)                 ((x) & GENMASK(5, 0))
GENMASK           663 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M                  GENMASK(5, 0)
GENMASK           665 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_HP(x)                     (((x) << 18) & GENMASK(23, 18))
GENMASK           666 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_HP_M                      GENMASK(23, 18)
GENMASK           667 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x)                   (((x) & GENMASK(23, 18)) >> 18)
GENMASK           668 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_MID(x)                    (((x) << 12) & GENMASK(17, 12))
GENMASK           669 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_MID_M                     GENMASK(17, 12)
GENMASK           670 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x)                  (((x) & GENMASK(17, 12)) >> 12)
GENMASK           671 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_LP(x)                     (((x) << 6) & GENMASK(11, 6))
GENMASK           672 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_LP_M                      GENMASK(11, 6)
GENMASK           673 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x)                   (((x) & GENMASK(11, 6)) >> 6)
GENMASK           674 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x)                 ((x) & GENMASK(5, 0))
GENMASK           675 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M                  GENMASK(5, 0)
GENMASK           680 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST0(x)                       (((x) << 23) & GENMASK(28, 23))
GENMASK           681 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST0_M                        GENMASK(28, 23)
GENMASK           682 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST0_X(x)                     (((x) & GENMASK(28, 23)) >> 23)
GENMASK           683 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_PREC(x)                        (((x) << 18) & GENMASK(22, 18))
GENMASK           684 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_PREC_M                         GENMASK(22, 18)
GENMASK           685 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_PREC_X(x)                      (((x) & GENMASK(22, 18)) >> 18)
GENMASK           688 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST1(x)                       (((x) << 11) & GENMASK(15, 11))
GENMASK           689 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST1_M                        GENMASK(15, 11)
GENMASK           690 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_POST1_X(x)                     (((x) & GENMASK(15, 11)) >> 11)
GENMASK           694 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_SR(x)                          (((x) << 4) & GENMASK(7, 4))
GENMASK           695 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_SR_M                           GENMASK(7, 4)
GENMASK           696 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_SR_X(x)                        (((x) & GENMASK(7, 4)) >> 4)
GENMASK           697 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x)               ((x) & GENMASK(3, 0))
GENMASK           698 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M                GENMASK(3, 0)
GENMASK           700 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x)                    (((x) << 6) & GENMASK(8, 6))
GENMASK           701 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M                     GENMASK(8, 6)
GENMASK           702 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x)                  (((x) & GENMASK(8, 6)) >> 6)
GENMASK           703 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG1_OB_LEV(x)                        ((x) & GENMASK(5, 0))
GENMASK           704 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_OB_CFG1_OB_LEV_M                         GENMASK(5, 0)
GENMASK           709 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_ALISEL(x)                    (((x) << 4) & GENMASK(5, 4))
GENMASK           710 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_ALISEL_M                     GENMASK(5, 4)
GENMASK           711 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_SER_CFG_SER_ALISEL_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
GENMASK           723 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_LANE_CTRL(x)                  (((x) << 9) & GENMASK(11, 9))
GENMASK           724 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_LANE_CTRL_M                   GENMASK(11, 9)
GENMASK           725 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x)                (((x) & GENMASK(11, 9)) >> 9)
GENMASK           733 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_IF_MODE(x)                    ((x) & GENMASK(1, 0))
GENMASK           734 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_COMMON_CFG_IF_MODE_M                     GENMASK(1, 0)
GENMASK           736 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x)                  (((x) << 16) & GENMASK(17, 16))
GENMASK           737 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M                   GENMASK(17, 16)
GENMASK           738 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x)                (((x) & GENMASK(17, 16)) >> 16)
GENMASK           741 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x)             (((x) << 6) & GENMASK(13, 6))
GENMASK           742 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M              GENMASK(13, 6)
GENMASK           743 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x)           (((x) & GENMASK(13, 6)) >> 6)
GENMASK           758 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_GP_CFG_GP_MSB(x)                         (((x) << 16) & GENMASK(31, 16))
GENMASK           759 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_GP_CFG_GP_MSB_M                          GENMASK(31, 16)
GENMASK           760 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_GP_CFG_GP_MSB_X(x)                       (((x) & GENMASK(31, 16)) >> 16)
GENMASK           761 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_GP_CFG_GP_LSB(x)                         ((x) & GENMASK(15, 0))
GENMASK           762 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_GP_CFG_GP_LSB_M                          GENMASK(15, 0)
GENMASK           774 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x)            (((x) << 18) & GENMASK(23, 18))
GENMASK           775 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M             GENMASK(23, 18)
GENMASK           776 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x)          (((x) & GENMASK(23, 18)) >> 18)
GENMASK           777 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x)           (((x) << 12) & GENMASK(17, 12))
GENMASK           778 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M            GENMASK(17, 12)
GENMASK           779 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x)         (((x) & GENMASK(17, 12)) >> 12)
GENMASK           780 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x)            (((x) << 6) & GENMASK(11, 6))
GENMASK           781 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M             GENMASK(11, 6)
GENMASK           782 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x)          (((x) & GENMASK(11, 6)) >> 6)
GENMASK           783 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x)             ((x) & GENMASK(5, 0))
GENMASK           784 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M              GENMASK(5, 0)
GENMASK           793 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x)                ((x) & GENMASK(7, 0))
GENMASK           794 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M                 GENMASK(7, 0)
GENMASK           796 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SERDES_REV(x)                      (((x) << 26) & GENMASK(31, 26))
GENMASK           797 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SERDES_REV_M                       GENMASK(31, 26)
GENMASK           798 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SERDES_REV_X(x)                    (((x) & GENMASK(31, 26)) >> 26)
GENMASK           799 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_RCPLL_REV(x)                       (((x) << 21) & GENMASK(25, 21))
GENMASK           800 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_RCPLL_REV_M                        GENMASK(25, 21)
GENMASK           801 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_RCPLL_REV_X(x)                     (((x) & GENMASK(25, 21)) >> 21)
GENMASK           802 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SER_REV(x)                         (((x) << 16) & GENMASK(20, 16))
GENMASK           803 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SER_REV_M                          GENMASK(20, 16)
GENMASK           804 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_SER_REV_X(x)                       (((x) & GENMASK(20, 16)) >> 16)
GENMASK           805 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_DES_REV(x)                         (((x) << 10) & GENMASK(15, 10))
GENMASK           806 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_DES_REV_M                          GENMASK(15, 10)
GENMASK           807 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_DES_REV_X(x)                       (((x) & GENMASK(15, 10)) >> 10)
GENMASK           808 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_OB_REV(x)                          (((x) << 5) & GENMASK(9, 5))
GENMASK           809 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_OB_REV_M                           GENMASK(9, 5)
GENMASK           810 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_OB_REV_X(x)                        (((x) & GENMASK(9, 5)) >> 5)
GENMASK           811 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_IB_REV(x)                          ((x) & GENMASK(4, 0))
GENMASK           812 include/soc/mscc/ocelot_hsio.h #define HSIO_S6G_REVID_IB_REV_M                           GENMASK(4, 0)
GENMASK           816 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x)            ((x) & GENMASK(24, 0))
GENMASK           817 include/soc/mscc/ocelot_hsio.h #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M             GENMASK(24, 0)
GENMASK           832 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x)           (((x) << 1) & GENMASK(6, 1))
GENMASK           833 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M            GENMASK(6, 1)
GENMASK           834 include/soc/mscc/ocelot_hsio.h #define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x)         (((x) & GENMASK(6, 1)) >> 1)
GENMASK           837 include/soc/mscc/ocelot_hsio.h #define HSIO_CLK_CFG_CLKDIV_PHY(x)                        (((x) << 1) & GENMASK(8, 1))
GENMASK           838 include/soc/mscc/ocelot_hsio.h #define HSIO_CLK_CFG_CLKDIV_PHY_M                         GENMASK(8, 1)
GENMASK           839 include/soc/mscc/ocelot_hsio.h #define HSIO_CLK_CFG_CLKDIV_PHY_X(x)                      (((x) & GENMASK(8, 1)) >> 1)
GENMASK           849 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CFG_RUN_WID(x)                   (((x) << 8) & GENMASK(15, 8))
GENMASK           850 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CFG_RUN_WID_M                    GENMASK(15, 8)
GENMASK           851 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x)                 (((x) & GENMASK(15, 8)) >> 8)
GENMASK           852 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x)                ((x) & GENMASK(7, 0))
GENMASK           853 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M                 GENMASK(7, 0)
GENMASK           856 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_STAT_TEMP(x)                     ((x) & GENMASK(7, 0))
GENMASK           857 include/soc/mscc/ocelot_hsio.h #define HSIO_TEMP_SENSOR_STAT_TEMP_M                      GENMASK(7, 0)
GENMASK           366 kernel/trace/trace_probe.h #define TPARG_FL_MASK	GENMASK(2, 0)
GENMASK           268 net/bridge/br.c 	bm->optmask = GENMASK((BR_BOOLOPT_MAX - 1), 0);
GENMASK            46 net/dsa/tag_8021q.c #define DSA_8021Q_DIR_MASK		GENMASK(11, 10)
GENMASK            53 net/dsa/tag_8021q.c #define DSA_8021Q_SWITCH_ID_MASK	GENMASK(8, 6)
GENMASK            58 net/dsa/tag_8021q.c #define DSA_8021Q_PORT_MASK		GENMASK(3, 0)
GENMASK            45 net/dsa/tag_gswip.c #define GSWIP_TX_CLASS_MASK		GENMASK(3, 0)
GENMASK            50 net/dsa/tag_gswip.c #define GSWIP_TX_PORT_MAP_MASK		GENMASK(6, 1)
GENMASK            57 net/dsa/tag_gswip.c #define GSWIP_RX_SPPID_MASK		GENMASK(6, 4)
GENMASK            16 net/dsa/tag_mtk.c #define MTK_HDR_RECV_SOURCE_PORT_MASK	GENMASK(2, 0)
GENMASK            17 net/dsa/tag_mtk.c #define MTK_HDR_XMIT_DP_BIT_MASK	GENMASK(5, 0)
GENMASK            13 net/dsa/tag_qca.c #define QCA_HDR_RECV_VERSION_MASK	GENMASK(15, 14)
GENMASK            15 net/dsa/tag_qca.c #define QCA_HDR_RECV_PRIORITY_MASK	GENMASK(13, 11)
GENMASK            17 net/dsa/tag_qca.c #define QCA_HDR_RECV_TYPE_MASK		GENMASK(10, 6)
GENMASK            20 net/dsa/tag_qca.c #define QCA_HDR_RECV_SOURCE_PORT_MASK	GENMASK(2, 0)
GENMASK            22 net/dsa/tag_qca.c #define QCA_HDR_XMIT_VERSION_MASK	GENMASK(15, 14)
GENMASK            24 net/dsa/tag_qca.c #define QCA_HDR_XMIT_PRIORITY_MASK	GENMASK(13, 11)
GENMASK            26 net/dsa/tag_qca.c #define QCA_HDR_XMIT_CONTROL_MASK	GENMASK(10, 8)
GENMASK            29 net/dsa/tag_qca.c #define QCA_HDR_XMIT_DP_BIT_MASK	GENMASK(6, 0)
GENMASK           810 net/mac80211/sta_info.h #define STA_STATS_FIELD_HT_MCS		GENMASK( 7,  0)
GENMASK           811 net/mac80211/sta_info.h #define STA_STATS_FIELD_LEGACY_IDX	GENMASK( 3,  0)
GENMASK           812 net/mac80211/sta_info.h #define STA_STATS_FIELD_LEGACY_BAND	GENMASK( 7,  4)
GENMASK           813 net/mac80211/sta_info.h #define STA_STATS_FIELD_VHT_MCS		GENMASK( 3,  0)
GENMASK           814 net/mac80211/sta_info.h #define STA_STATS_FIELD_VHT_NSS		GENMASK( 7,  4)
GENMASK           815 net/mac80211/sta_info.h #define STA_STATS_FIELD_HE_MCS		GENMASK( 3,  0)
GENMASK           816 net/mac80211/sta_info.h #define STA_STATS_FIELD_HE_NSS		GENMASK( 7,  4)
GENMASK           817 net/mac80211/sta_info.h #define STA_STATS_FIELD_BW		GENMASK(11,  8)
GENMASK           818 net/mac80211/sta_info.h #define STA_STATS_FIELD_SGI		GENMASK(12, 12)
GENMASK           819 net/mac80211/sta_info.h #define STA_STATS_FIELD_TYPE		GENMASK(15, 13)
GENMASK           820 net/mac80211/sta_info.h #define STA_STATS_FIELD_HE_RU		GENMASK(18, 16)
GENMASK           821 net/mac80211/sta_info.h #define STA_STATS_FIELD_HE_GI		GENMASK(20, 19)
GENMASK           822 net/mac80211/sta_info.h #define STA_STATS_FIELD_HE_DCM		GENMASK(21, 21)
GENMASK            57 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_MODE_MASK		GENMASK(0, 0)
GENMASK            61 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_DATALENGTH_MASK		GENMASK(4, 2)
GENMASK            71 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_FORMAT_MASK	GENMASK(7, 6)
GENMASK            81 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_RXDMA_MASK	GENMASK(9, 9)
GENMASK            92 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_TXDMA_MASK	GENMASK(13, 13)
GENMASK            97 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_TXSAME_MASK	GENMASK(14, 14)
GENMASK           102 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_IMCKDIV_MASK	GENMASK(21, 16)
GENMASK           107 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_IMCKFS_MASK	GENMASK(29, 24)
GENMASK           112 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_MR_IMCKMODE_MASK	GENMASK(30, 30)
GENMASK           135 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_RXORCH_MASK	GENMASK(15, 8)
GENMASK           139 sound/soc/atmel/atmel-i2s.c #define ATMEL_I2SC_SR_TXURCH_MASK	GENMASK(27, 20)
GENMASK            25 sound/soc/atmel/atmel-pdmic.h #define PDMIC_MR_PRESCAL_MASK	GENMASK(14, 8)
GENMASK            60 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_OSR_MASK		GENMASK(6, 4)
GENMASK            63 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_SCALE_MASK		GENMASK(11, 8)
GENMASK            66 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR0_SHIFT_MASK		GENMASK(15, 12)
GENMASK            71 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR1_DGAIN_MASK		GENMASK(14, 0)
GENMASK            74 sound/soc/atmel/atmel-pdmic.h #define PDMIC_DSPR1_OFFSET_MASK		GENMASK(31, 16)
GENMASK            87 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_MODE_MASK		GENMASK(0, 0)
GENMASK            91 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_DATALENGTH_MASK			GENMASK(3, 1)
GENMASK           101 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_WIRECFG_MASK		GENMASK(5, 4)
GENMASK           107 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_FORMAT_MASK		GENMASK(7, 6)
GENMASK           133 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_NBCHAN_MASK		GENMASK(15, 13)
GENMASK           138 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_IMCKDIV_MASK		GENMASK(21, 16)
GENMASK           143 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_TDMFS_MASK		GENMASK(23, 22)
GENMASK           149 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_ISCKDIV_MASK		GENMASK(29, 24)
GENMASK           154 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRA_IMCKMODE_MASK		GENMASK(30, 30)
GENMASK           178 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRB_DMACHUNK_MASK		GENMASK(9, 8)
GENMASK           182 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_MRB_CLKSEL_MASK		GENMASK(16, 16)
GENMASK           195 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXRDY_MASK(ch)		GENMASK((ch) - 1, 0)
GENMASK           197 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_TXUNF_MASK(ch)		GENMASK((ch) + 7, 8)
GENMASK           199 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXRDY_MASK(ch)		GENMASK((ch) + 15, 16)
GENMASK           201 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_INT_RXOVF_MASK(ch)		GENMASK((ch) + 23, 24)
GENMASK           216 sound/soc/atmel/mchp-i2s-mcc.c #define MCHP_I2SMCC_VERSION_MASK		GENMASK(11, 0)
GENMASK           360 sound/soc/atmel/mchp-i2s-mcc.c 		if (rx_mask != GENMASK(slots - 1, 0) ||
GENMASK           422 sound/soc/atmel/mchp-i2s-mcc.c 	     (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&
GENMASK           423 sound/soc/atmel/mchp-i2s-mcc.c 	     (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));
GENMASK           260 sound/soc/bcm/bcm2835-i2s.c 		rx_mask &= GENMASK(slots - 1, 0);
GENMASK           261 sound/soc/bcm/bcm2835-i2s.c 		tx_mask &= GENMASK(slots - 1, 0);
GENMASK            46 sound/soc/codecs/ak4458.h #define AK4458_SD_MASK		GENMASK(5, 5)
GENMASK            47 sound/soc/codecs/ak4458.h #define AK4458_SLOW_MASK	GENMASK(0, 0)
GENMASK            48 sound/soc/codecs/ak4458.h #define AK4458_SSLOW_MASK	GENMASK(0, 0)
GENMASK            55 sound/soc/codecs/ak4458.h #define AK4458_DIF_MASK		GENMASK(3, 1)
GENMASK            64 sound/soc/codecs/ak4458.h #define AK4458_RSTN_MASK	GENMASK(0, 0)
GENMASK            69 sound/soc/codecs/ak4458.h #define AK4458_MODE_MASK	GENMASK(7, 6)
GENMASK            84 sound/soc/codecs/ak4458.h #define AK4458_ATS_MASK		GENMASK(7, 6)
GENMASK            20 sound/soc/codecs/ak5558.h #define AK5558_DIF			GENMASK(1, 1)
GENMASK            24 sound/soc/codecs/ak5558.h #define AK5558_BITS			GENMASK(2, 2)
GENMASK            28 sound/soc/codecs/ak5558.h #define AK5558_CKS			GENMASK(6, 3)
GENMASK            46 sound/soc/codecs/ak5558.h #define AK5558_MODE_BITS	GENMASK(6, 5)
GENMASK            32 sound/soc/codecs/jz4725b.c #define	ICDC_RGADW_RGADDR_MASK		GENMASK(14, ICDC_RGADW_RGADDR_OFFSET)
GENMASK            35 sound/soc/codecs/jz4725b.c #define	ICDC_RGADW_RGDIN_MASK		GENMASK(7, ICDC_RGADW_RGDIN_OFFSET)
GENMASK            41 sound/soc/codecs/jz4725b.c #define ICDC_RGDATA_RGDOUT_MASK		GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET)
GENMASK            59 sound/soc/codecs/msm8916-wcd-analog.c #define CONN_TX1_SERIAL_TX1_MUX		GENMASK(1, 0)
GENMASK            65 sound/soc/codecs/msm8916-wcd-analog.c #define CONN_TX2_SERIAL_TX2_MUX		GENMASK(1, 0)
GENMASK           101 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
GENMASK           111 sound/soc/codecs/msm8916-wcd-analog.c #define MICB_1_VAL_MICB_OUT_VAL_MASK	GENMASK(7, 3)
GENMASK           161 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK		GENMASK(4, 3)
GENMASK           166 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_PLUG_TYPE_MASK				GENMASK(4, 3)
GENMASK           175 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK		GENMASK(6, 4)
GENMASK           185 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_BTN_VREF_FINE_MASK	GENMASK(4, 2)
GENMASK           186 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_BTN_VREF_COARSE_MASK	GENMASK(7, 5)
GENMASK           191 sound/soc/codecs/msm8916-wcd-analog.c #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK	GENMASK(4, 0)
GENMASK            24 sound/soc/codecs/msm8916-wcd-digital.c #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK		GENMASK(3, 1)
GENMASK            37 sound/soc/codecs/msm8916-wcd-digital.c #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK		GENMASK(2, 0)
GENMASK            48 sound/soc/codecs/msm8916-wcd-digital.c #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK		GENMASK(2, 0)
GENMASK           162 sound/soc/codecs/msm8916-wcd-digital.c #define TX_MUX_CTL_CUT_OFF_FREQ_MASK		GENMASK(5, 4)
GENMASK           176 sound/soc/codecs/msm8916-wcd-digital.c #define TXN_DMIC_CTL_CLK_SEL_MASK		GENMASK(2, 0)
GENMASK           146 sound/soc/codecs/pcm186x.h #define PCM186X_ADC_INPUT_SEL_MASK	GENMASK(5, 0)
GENMASK           149 sound/soc/codecs/pcm186x.h #define PCM186X_PCM_CFG_RX_WLEN_MASK	GENMASK(7, 6)
GENMASK           156 sound/soc/codecs/pcm186x.h #define PCM186X_PCM_CFG_TX_WLEN_MASK	GENMASK(3, 2)
GENMASK           162 sound/soc/codecs/pcm186x.h #define PCM186X_PCM_CFG_FMT_MASK	GENMASK(1, 0)
GENMASK            48 sound/soc/codecs/rk3328_codec.h #define DAC_VDL_MASK			GENMASK(6, 5)
GENMASK            53 sound/soc/codecs/rk3328_codec.h #define DAC_MODE_MASK			GENMASK(4, 3)
GENMASK            63 sound/soc/codecs/rk3328_codec.h #define DAC_WL_MASK			GENMASK(3, 2)
GENMASK            93 sound/soc/codecs/rk3328_codec.h #define DAC_CHARGE_CURRENT_ALL_MASK	GENMASK(6, 0)
GENMASK           189 sound/soc/codecs/rk3328_codec.h #define HPOUTL_GAIN_MASK		GENMASK(4, 0)
GENMASK           192 sound/soc/codecs/rk3328_codec.h #define HPOUTR_GAIN_MASK		GENMASK(4, 0)
GENMASK           195 sound/soc/codecs/rk3328_codec.h #define HPOUTR_POP_MASK			GENMASK(5, 4)
GENMASK           198 sound/soc/codecs/rk3328_codec.h #define HPOUTL_POP_MASK			GENMASK(1, 0)
GENMASK            35 sound/soc/codecs/tas5720.h #define TAS5720_DIG_CLIP_MASK		GENMASK(7, 2)
GENMASK            49 sound/soc/codecs/tas5720.h #define TAS5720_SAIF_FORMAT_MASK	GENMASK(2, 0)
GENMASK            54 sound/soc/codecs/tas5720.h #define TAS5720_TDM_SLOT_SEL_MASK	GENMASK(2, 0)
GENMASK            65 sound/soc/codecs/tas5720.h #define TAS5720_PWM_RATE_MASK		GENMASK(6, 4)
GENMASK            70 sound/soc/codecs/tas5720.h #define TAS5720_ANALOG_GAIN_MASK	GENMASK(3, 2)
GENMASK            78 sound/soc/codecs/tas5720.h #define TAS5720_OC_THRESH_MASK		GENMASK(5, 4)
GENMASK            83 sound/soc/codecs/tas5720.h #define TAS5720_FAULT_MASK		GENMASK(3, 0)
GENMASK            86 sound/soc/codecs/tas5720.h #define TAS5720_CLIP1_MASK		GENMASK(7, 2)
GENMASK            98 sound/soc/codecs/tas5720.h #define TAS5722_HPF_MASK		GENMASK(7, 5)
GENMASK           103 sound/soc/codecs/tas5720.h #define TAS5722_AUTO_SLEEP_MASK		GENMASK(4, 3)
GENMASK            60 sound/soc/codecs/tas6424.h #define TAS6424_SAP_RATE_MASK		GENMASK(7, 6)
GENMASK            67 sound/soc/codecs/tas6424.h #define TAS6424_SAP_FMT_MASK		GENMASK(2, 0)
GENMASK            77 sound/soc/codecs/tas6424.h #define TAS6424_CH1_STATE_MASK		GENMASK(7, 6)
GENMASK            82 sound/soc/codecs/tas6424.h #define TAS6424_CH2_STATE_MASK		GENMASK(5, 4)
GENMASK            87 sound/soc/codecs/tas6424.h #define TAS6424_CH3_STATE_MASK		GENMASK(3, 2)
GENMASK            92 sound/soc/codecs/tas6424.h #define TAS6424_CH4_STATE_MASK		GENMASK(1, 0)
GENMASK           118 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_PLL_CLKIN_MASK		GENMASK(3, 2)
GENMASK           124 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_CODEC_CLKIN_MASK	GENMASK(1, 0)
GENMASK           137 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_PLL_MASK		GENMASK(6, 0)
GENMASK           141 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_IFACE1_DATATYPE_MASK	GENMASK(7, 6)
GENMASK           147 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_IFACE1_DATALEN_MASK	GENMASK(5, 4)
GENMASK           153 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_IFACE1_MASTER_MASK	GENMASK(3, 2)
GENMASK           158 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DATA_OFFSET_MASK	GENMASK(7, 0)
GENMASK           162 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_BDIVCLK_MASK		GENMASK(1, 0)
GENMASK           206 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_GPIO1_FUNC_MASK		GENMASK(5, 2)
GENMASK           222 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_SOFTSTEP_MASK		GENMASK(1, 0)
GENMASK           225 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_DACMUTE_MASK		GENMASK(3, 2)
GENMASK           229 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_HSD_TYPE_MASK		GENMASK(6, 5)
GENMASK           236 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_MICBIAS_MASK		GENMASK(1, 0)
GENMASK           103 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_PLL_CLKIN_MASK		GENMASK(3, 2)
GENMASK           109 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_CODEC_CLKIN_MASK	GENMASK(1, 0)
GENMASK           118 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_PLL_P_MASK		GENMASK(6, 4)
GENMASK           120 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_PLL_R_MASK		GENMASK(3, 0)
GENMASK           124 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_NDAC_MASK		GENMASK(6, 0)
GENMASK           128 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_MDAC_MASK		GENMASK(6, 0)
GENMASK           132 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_NADC_MASK		GENMASK(6, 0)
GENMASK           136 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_MADC_MASK		GENMASK(6, 0)
GENMASK           140 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_BCLK_MASK		GENMASK(6, 0)
GENMASK           143 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_IFACE1_DATATYPE_MASK	GENMASK(7, 6)
GENMASK           149 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_IFACE1_DATALEN_MASK	GENMASK(5, 4)
GENMASK           155 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_IFACE1_MASTER_MASK	GENMASK(3, 2)
GENMASK           160 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_DATA_OFFSET_MASK	GENMASK(7, 0)
GENMASK           164 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_BDIVCLK_MASK		GENMASK(1, 0)
GENMASK           172 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_DAC_CHAN_MASK		GENMASK(5, 2)
GENMASK           198 sound/soc/codecs/tlv320aic32x4.h #define AIC32x4_MICBIAS_MASK            GENMASK(6, 3)
GENMASK           210 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_DIV_MASK        GENMASK(6, 0)
GENMASK            30 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK		GENMASK(3, 0)
GENMASK            32 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK		GENMASK(7, 0)
GENMASK            52 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK		GENMASK(3, 2)
GENMASK            61 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK		GENMASK(6, 5)
GENMASK            67 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK		GENMASK(7, 4)
GENMASK            68 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK		GENMASK(3, 0)
GENMASK            70 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_HPH_CONST_SEL_L_MASK			GENMASK(7, 3)
GENMASK            76 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK		GENMASK(2, 0)
GENMASK            78 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK	GENMASK(5, 4)
GENMASK            87 sound/soc/codecs/wcd-clsh-v2.c #define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK	GENMASK(7, 4)
GENMASK            18 sound/soc/codecs/wcd9335.h #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK	GENMASK(1, 0)
GENMASK            22 sound/soc/codecs/wcd9335.h #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK	GENMASK(1, 0)
GENMASK            27 sound/soc/codecs/wcd9335.h #define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1)
GENMASK           219 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_BUCK_VOUT_MASK		GENMASK(7, 0)
GENMASK           258 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK	GENMASK(6, 4)
GENMASK           259 sound/soc/codecs/wcd9335.h #define WCD9335_ANA_MBHC_BD_ISRC_100UA		GENMASK(5, 4)
GENMASK           267 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_BTN_RESULT_MASK		GENMASK(2, 0)
GENMASK           294 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_BTN_DBNC_MASK		GENMASK(1, 0)
GENMASK           300 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HS_VREF_CTL_MASK		GENMASK(1, 0)
GENMASK           303 sound/soc/codecs/wcd9335.h #define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK	GENMASK(7, 6)
GENMASK           312 sound/soc/codecs/wcd9335.h #define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK	GENMASK(3, 0)
GENMASK           316 sound/soc/codecs/wcd9335.h #define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK	GENMASK(3, 0)
GENMASK           318 sound/soc/codecs/wcd9335.h #define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK	GENMASK(7, 4)
GENMASK           321 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK	GENMASK(2, 0)
GENMASK           330 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_GM3_IB_SCALE_MASK		GENMASK(3, 1)
GENMASK           342 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_CONST_SEL_L_MASK		GENMASK(7, 6)
GENMASK           346 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_PA_GAIN_MASK		GENMASK(4, 0)
GENMASK           355 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK	GENMASK(2, 0)
GENMASK           357 sound/soc/codecs/wcd9335.h #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK	GENMASK(6, 4)
GENMASK           379 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK	GENMASK(3, 0)
GENMASK           449 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_MIX_PCM_RATE_MASK		GENMASK(3, 0)
GENMASK           475 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK	GENMASK(1, 0)
GENMASK           478 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK	GENMASK(5, 2)
GENMASK           489 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK	GENMASK(1, 0)
GENMASK           552 sound/soc/codecs/wcd9335.h #define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK	GENMASK(3, 0)
GENMASK            60 sound/soc/dwc/local.h #define	COMP1_TX_WORDSIZE_3(r)	(((r) & GENMASK(27, 25)) >> 25)
GENMASK            61 sound/soc/dwc/local.h #define	COMP1_TX_WORDSIZE_2(r)	(((r) & GENMASK(24, 22)) >> 22)
GENMASK            62 sound/soc/dwc/local.h #define	COMP1_TX_WORDSIZE_1(r)	(((r) & GENMASK(21, 19)) >> 19)
GENMASK            63 sound/soc/dwc/local.h #define	COMP1_TX_WORDSIZE_0(r)	(((r) & GENMASK(18, 16)) >> 16)
GENMASK            64 sound/soc/dwc/local.h #define	COMP1_TX_CHANNELS(r)	(((r) & GENMASK(10, 9)) >> 9)
GENMASK            65 sound/soc/dwc/local.h #define	COMP1_RX_CHANNELS(r)	(((r) & GENMASK(8, 7)) >> 7)
GENMASK            69 sound/soc/dwc/local.h #define	COMP1_FIFO_DEPTH_GLOBAL(r)	(((r) & GENMASK(3, 2)) >> 2)
GENMASK            70 sound/soc/dwc/local.h #define	COMP1_APB_DATA_WIDTH(r)	(((r) & GENMASK(1, 0)) >> 0)
GENMASK            72 sound/soc/dwc/local.h #define	COMP2_RX_WORDSIZE_3(r)	(((r) & GENMASK(12, 10)) >> 10)
GENMASK            73 sound/soc/dwc/local.h #define	COMP2_RX_WORDSIZE_2(r)	(((r) & GENMASK(9, 7)) >> 7)
GENMASK            74 sound/soc/dwc/local.h #define	COMP2_RX_WORDSIZE_1(r)	(((r) & GENMASK(5, 3)) >> 3)
GENMASK            75 sound/soc/dwc/local.h #define	COMP2_RX_WORDSIZE_0(r)	(((r) & GENMASK(2, 0)) >> 0)
GENMASK           113 sound/soc/fsl/fsl_sai.h #define FSL_SAI_CR3_TRCE_MASK	GENMASK(23, 16)
GENMASK            49 sound/soc/intel/boards/bytcht_es8316.c #define BYT_CHT_ES8316_MAP(quirk)		((quirk) & GENMASK(3, 0))
GENMASK            63 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_MAP(quirk)		((quirk) &  GENMASK(3, 0))
GENMASK            64 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_JDSRC(quirk)		(((quirk) & GENMASK(7, 4)) >> 4)
GENMASK            65 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_OVCD_TH(quirk)	(((quirk) & GENMASK(12, 8)) >> 8)
GENMASK            66 sound/soc/intel/boards/bytcr_rt5640.c #define BYT_RT5640_OVCD_SF(quirk)	(((quirk) & GENMASK(14, 13)) >> 13)
GENMASK            61 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_MAP(quirk)		((quirk) & GENMASK(3, 0))
GENMASK            62 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_JDSRC(quirk)		(((quirk) & GENMASK(7, 4)) >> 4)
GENMASK            63 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_OVCD_TH(quirk)	(((quirk) & GENMASK(12, 8)) >> 8)
GENMASK            64 sound/soc/intel/boards/bytcr_rt5651.c #define BYT_RT5651_OVCD_SF(quirk)	(((quirk) & GENMASK(14, 13)) >> 13)
GENMASK            47 sound/soc/intel/boards/cht_bsw_rt5645.c #define CHT_RT5645_MAP(quirk)	((quirk) & GENMASK(7, 0))
GENMASK            27 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_SSP_CODEC(quirk)		((quirk) & GENMASK(2, 0))
GENMASK            28 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_SSP_CODEC_MASK			(GENMASK(2, 0))
GENMASK            33 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_SSP_AMP_MASK                 (GENMASK(8, 6))
GENMASK            38 sound/soc/intel/boards/sof_rt5682.c #define SOF_RT5682_NUM_HDMIDEV_MASK		(GENMASK(12, 10))
GENMASK            16 sound/soc/intel/skylake/skl-i2s.h #define SKL_MCLK_DIV_CLK_SRC_MASK	GENMASK(17, 16)
GENMASK            18 sound/soc/intel/skylake/skl-i2s.h #define SKL_MNDSS_DIV_CLK_SRC_MASK	GENMASK(21, 20)
GENMASK            20 sound/soc/intel/skylake/skl-i2s.h #define SKL_MCLK_DIV_RATIO_MASK		GENMASK(11, 0)
GENMASK            90 sound/soc/intel/skylake/skl-sst-dsp.h #define SKL_DSP_CORES_MASK(nc)	GENMASK((nc - 1), 0)
GENMASK            31 sound/soc/intel/skylake/skl-topology.c #define SKL_PIN_COUNT_MASK		GENMASK(7, 4)
GENMASK            43 sound/soc/meson/axg-fifo.h #define FIFO_INT_MASK			GENMASK(7, 0)
GENMASK            48 sound/soc/meson/axg-fifo.h #define  CTRL0_SEL_MASK			GENMASK(2, 0)
GENMASK            52 sound/soc/meson/axg-fifo.h #define  CTRL1_STATUS2_SEL_MASK		GENMASK(11, 8)
GENMASK            55 sound/soc/meson/axg-fifo.h #define  CTRL1_FRDDR_DEPTH_MASK		GENMASK(31, 24)
GENMASK            20 sound/soc/meson/axg-pdm.c #define  PDM_CTRL_CHAN_RSTN_MASK	GENMASK(15, 8)
GENMASK            22 sound/soc/meson/axg-pdm.c #define  PDM_CTRL_CHAN_EN_MASK		GENMASK(7, 0)
GENMASK            26 sound/soc/meson/axg-pdm.c #define  PDM_HCIC_CTRL1_GAIN_SFT_MASK	GENMASK(29, 24)
GENMASK            28 sound/soc/meson/axg-pdm.c #define  PDM_HCIC_CTRL1_GAIN_MULT_MASK	GENMASK(23, 16)
GENMASK            30 sound/soc/meson/axg-pdm.c #define  PDM_HCIC_CTRL1_DSR_MASK	GENMASK(8, 4)
GENMASK            32 sound/soc/meson/axg-pdm.c #define  PDM_HCIC_CTRL1_STAGE_NUM_MASK	GENMASK(3, 0)
GENMASK            36 sound/soc/meson/axg-pdm.c #define  PDM_LPF_ROUND_MODE_MASK	GENMASK(17, 16)
GENMASK            38 sound/soc/meson/axg-pdm.c #define  PDM_LPF_DSR_MASK		GENMASK(15, 12)
GENMASK            40 sound/soc/meson/axg-pdm.c #define  PDM_LPF_STAGE_NUM_MASK		GENMASK(8, 0)
GENMASK            47 sound/soc/meson/axg-pdm.c #define  PDM_HPF_SFT_STEPS_MASK		GENMASK(20, 16)
GENMASK            49 sound/soc/meson/axg-pdm.c #define  PDM_HPF_OUT_FACTOR_MASK	GENMASK(15, 0)
GENMASK           209 sound/soc/meson/axg-pdm.c 	unsigned int mask = GENMASK(channels - 1, 0);
GENMASK            21 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_CTRL0_STATUS_SEL	GENMASK(10, 8)
GENMASK            22 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_CTRL0_SRC_SEL		GENMASK(5, 4)
GENMASK            25 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_CTRL1_BASE_TIMER	GENMASK(19, 0)
GENMASK            26 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_CTRL1_IRQ_MASK		GENMASK(27, 20)
GENMASK            37 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_STAT0_MODE		GENMASK(30, 28)
GENMASK            38 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_STAT0_MAXW		GENMASK(17, 8)
GENMASK            39 sound/soc/meson/axg-spdifin.c #define  SPDIFIN_STAT0_IRQ		GENMASK(7, 0)
GENMASK           157 sound/soc/meson/axg-spdifin.c 	regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
GENMASK            36 sound/soc/meson/axg-spdifout.c #define  SPDIFOUT_CTRL0_MASK_MASK	GENMASK(11, 4)
GENMASK            39 sound/soc/meson/axg-spdifout.c #define  SPDIFOUT_CTRL1_MSB_POS_MASK	GENMASK(12, 8)
GENMASK            41 sound/soc/meson/axg-spdifout.c #define  SPDIFOUT_CTRL1_TYPE_MASK	GENMASK(6, 4)
GENMASK            21 sound/soc/meson/axg-tdmin.c #define  TDMIN_CTRL_IN_BIT_SKEW_MASK	GENMASK(18, 16)
GENMASK            24 sound/soc/meson/axg-tdmin.c #define  TDMIN_CTRL_BITNUM_MASK	GENMASK(4, 0)
GENMASK            15 sound/soc/meson/axg-tdmout.c #define  TDMOUT_CTRL0_BITNUM_MASK	GENMASK(4, 0)
GENMASK            17 sound/soc/meson/axg-tdmout.c #define  TDMOUT_CTRL0_SLOTNUM_MASK	GENMASK(9, 5)
GENMASK            19 sound/soc/meson/axg-tdmout.c #define  TDMOUT_CTRL0_INIT_BITNUM_MASK	GENMASK(19, 15)
GENMASK            25 sound/soc/meson/axg-tdmout.c #define  TDMOUT_CTRL1_TYPE_MASK		GENMASK(6, 4)
GENMASK            28 sound/soc/meson/axg-tdmout.c #define  TDMOUT_CTRL1_MSB_POS_MASK	GENMASK(12, 8)
GENMASK            21 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_TYPE_MASK		GENMASK(15, 13)
GENMASK            23 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_MSB_POS_MASK	GENMASK(12, 8)
GENMASK            25 sound/soc/meson/axg-toddr.c #define CTRL0_TODDR_LSB_POS_MASK	GENMASK(7, 3)
GENMASK            20 sound/soc/meson/g12a-tohdmitx.c #define  CTRL0_I2S_DAT_SEL		GENMASK(13, 12)
GENMASK            21 sound/soc/meson/g12a-tohdmitx.c #define  CTRL0_I2S_LRCLK_SEL		GENMASK(9, 8)
GENMASK            24 sound/soc/meson/g12a-tohdmitx.c #define  CTRL0_I2S_BCLK_SEL		GENMASK(5, 4)
GENMASK            42 sound/soc/qcom/lpass-lpaif-reg.h #define LPAIF_I2SCTL_MICEN_MASK		GENMASK(8, 8)
GENMASK            47 sound/soc/qcom/lpass-lpaif-reg.h #define LPAIF_I2SCTL_MICMODE_MASK	GENMASK(7, 4)
GENMASK            59 sound/soc/qcom/lpass-lpaif-reg.h #define LPAIF_I2SCTL_MIMONO_MASK	GENMASK(3, 3)
GENMASK            56 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD0_1_MASK		GENMASK(1, 0)
GENMASK            57 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD2_3_MASK		GENMASK(3, 2)
GENMASK            58 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD0_1_2_MASK	GENMASK(2, 0)
GENMASK            59 sound/soc/qcom/qdsp6/q6afe.c #define AFE_PORT_I2S_SD0_1_2_3_MASK	GENMASK(3, 0)
GENMASK           171 sound/soc/rockchip/rockchip_pdm.c 					    GENMASK(16 - 1, 0),
GENMASK           172 sound/soc/rockchip/rockchip_pdm.c 					    GENMASK(16 - 1, 0),
GENMASK            49 sound/soc/rockchip/rockchip_pdm.h #define PDM_FD_NUMERATOR_MSK	GENMASK(31, 16)
GENMASK            51 sound/soc/rockchip/rockchip_pdm.h #define PDM_FD_DENOMINATOR_MSK	GENMASK(15, 0)
GENMASK            53 sound/soc/sof/intel/hda.h #define SOF_HDA_CAP_ID_MASK		GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
GENMASK           134 sound/soc/sof/intel/hda.h 	GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
GENMASK           177 sound/soc/sof/intel/hda.h #define HDA_DSP_ROM_STS_MASK			GENMASK(23, 0)
GENMASK           298 sound/soc/sof/intel/hda.h #define SOF_DSP_CORES_MASK(nc)	GENMASK(((nc) - 1), 0)
GENMASK           139 sound/soc/sof/intel/shim.h #define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
GENMASK           142 sound/soc/sof/intel/shim.h #define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
GENMASK            59 sound/soc/sprd/sprd-mcdt.c #define MCDT_CH_FIFO_AE_MASK	GENMASK(24, 16)
GENMASK            60 sound/soc/sprd/sprd-mcdt.c #define MCDT_CH_FIFO_AF_MASK	GENMASK(8, 0)
GENMASK            63 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_CH0_SEL_MASK	GENMASK(3, 0)
GENMASK            65 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_CH1_SEL_MASK	GENMASK(7, 4)
GENMASK            67 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_CH2_SEL_MASK	GENMASK(11, 8)
GENMASK            69 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_CH3_SEL_MASK	GENMASK(15, 12)
GENMASK            71 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_CH4_SEL_MASK	GENMASK(19, 16)
GENMASK            76 sound/soc/sprd/sprd-mcdt.c #define MCDT_DMA_ACK_SEL_MASK	GENMASK(3, 0)
GENMASK            80 sound/soc/sprd/sprd-mcdt.c #define MCDT_CH_FIFO_ADDR_MASK	GENMASK(9, 0)
GENMASK            54 sound/soc/stm/stm32_i2s.c #define I2S_CFG1_FTHVL_MASK	GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
GENMASK            87 sound/soc/stm/stm32_i2s.c #define I2S_SR_RXPLVL		GENMASK(14, 13)
GENMASK            90 sound/soc/stm/stm32_i2s.c #define I2S_SR_MASK		GENMASK(15, 0)
GENMASK           103 sound/soc/stm/stm32_i2s.c #define I2S_IFCR_MASK		GENMASK(11, 3)
GENMASK           109 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_I2SCFG_MASK	GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
GENMASK           113 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_I2SSTD_MASK	GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
GENMASK           119 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_DATLEN_MASK	GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
GENMASK           131 sound/soc/stm/stm32_i2s.c #define I2S_CGFR_I2SDIV_MASK	GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
GENMASK           144 sound/soc/stm/stm32_i2s.c #define I2S_HWCFGR_I2S_SUPPORT_MASK	GENMASK(15, 12)
GENMASK           147 sound/soc/stm/stm32_i2s.c #define I2S_VERR_MIN_MASK	GENMASK(3, 0)
GENMASK           148 sound/soc/stm/stm32_i2s.c #define I2S_VERR_MAJ_MASK	GENMASK(7, 4)
GENMASK           151 sound/soc/stm/stm32_i2s.c #define I2S_IPIDR_ID_MASK	GENMASK(31, 0)
GENMASK           154 sound/soc/stm/stm32_i2s.c #define I2S_SIDR_ID_MASK	GENMASK(31, 0)
GENMASK            39 sound/soc/stm/stm32_sai.h #define SAI_GCR_SYNCIN_MASK	GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
GENMASK            44 sound/soc/stm/stm32_sai.h #define SAI_GCR_SYNCOUT_MASK	GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
GENMASK            53 sound/soc/stm/stm32_sai.h #define SAI_XCR1_PRTCFG_MASK	GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
GENMASK            57 sound/soc/stm/stm32_sai.h #define SAI_XCR1_DS_MASK	GENMASK(7, SAI_XCR1_DS_SHIFT)
GENMASK            66 sound/soc/stm/stm32_sai.h #define SAI_XCR1_SYNCEN_MASK	GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
GENMASK            82 sound/soc/stm/stm32_sai.h #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
GENMASK            95 sound/soc/stm/stm32_sai.h #define SAI_XCR2_FTH_MASK	GENMASK(2, SAI_XCR2_FTH_SHIFT)
GENMASK           108 sound/soc/stm/stm32_sai.h #define SAI_XCR2_MUTECNT_MASK	GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
GENMASK           115 sound/soc/stm/stm32_sai.h #define SAI_XCR2_COMP_MASK	GENMASK(15, SAI_XCR2_COMP_SHIFT)
GENMASK           120 sound/soc/stm/stm32_sai.h #define SAI_XFRCR_FRL_MASK	GENMASK(7, SAI_XFRCR_FRL_SHIFT)
GENMASK           124 sound/soc/stm/stm32_sai.h #define SAI_XFRCR_FSALL_MASK	GENMASK(14, SAI_XFRCR_FSALL_SHIFT)
GENMASK           136 sound/soc/stm/stm32_sai.h #define SAI_XSLOTR_FBOFF_MASK	GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)
GENMASK           140 sound/soc/stm/stm32_sai.h #define SAI_XSLOTR_SLOTSZ_MASK	GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)
GENMASK           144 sound/soc/stm/stm32_sai.h #define SAI_XSLOTR_NBSLOT_MASK	GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)
GENMASK           149 sound/soc/stm/stm32_sai.h #define SAI_XSLOTR_SLOTEN_MASK	GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)
GENMASK           162 sound/soc/stm/stm32_sai.h #define SAI_XIMR_MASK		GENMASK(6, SAI_XIMR_SHIFT)
GENMASK           174 sound/soc/stm/stm32_sai.h #define SAI_XSR_MASK		GENMASK(6, SAI_XSR_SHIFT)
GENMASK           186 sound/soc/stm/stm32_sai.h #define SAI_XCLRFR_MASK		GENMASK(6, SAI_XCLRFR_SHIFT)
GENMASK           192 sound/soc/stm/stm32_sai.h #define SAI_PDMCR_MICNBR_MASK	GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
GENMASK           202 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_1L_MASK	GENMASK(2, SAI_PDMDLY_1L_SHIFT)
GENMASK           206 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_1R_MASK	GENMASK(6, SAI_PDMDLY_1R_SHIFT)
GENMASK           210 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_2L_MASK	GENMASK(10, SAI_PDMDLY_2L_SHIFT)
GENMASK           214 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_2R_MASK	GENMASK(14, SAI_PDMDLY_2R_SHIFT)
GENMASK           218 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_3L_MASK	GENMASK(18, SAI_PDMDLY_3L_SHIFT)
GENMASK           222 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_3R_MASK	GENMASK(22, SAI_PDMDLY_3R_SHIFT)
GENMASK           226 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_4L_MASK	GENMASK(26, SAI_PDMDLY_4L_SHIFT)
GENMASK           230 sound/soc/stm/stm32_sai.h #define SAI_PDMDLY_4R_MASK	GENMASK(30, SAI_PDMDLY_4R_SHIFT)
GENMASK           236 sound/soc/stm/stm32_sai.h #define SAI_HWCFGR_FIFO_SIZE	GENMASK(7, 0)
GENMASK           237 sound/soc/stm/stm32_sai.h #define SAI_HWCFGR_SPDIF_PDM	GENMASK(11, 8)
GENMASK           238 sound/soc/stm/stm32_sai.h #define SAI_HWCFGR_REGOUT	GENMASK(19, 12)
GENMASK           241 sound/soc/stm/stm32_sai.h #define SAI_VERR_MIN_MASK	GENMASK(3, 0)
GENMASK           242 sound/soc/stm/stm32_sai.h #define SAI_VERR_MAJ_MASK	GENMASK(7, 4)
GENMASK           245 sound/soc/stm/stm32_sai.h #define SAI_IDR_ID_MASK		GENMASK(31, 0)
GENMASK           248 sound/soc/stm/stm32_sai.h #define SAI_SIDR_ID_MASK	GENMASK(31, 0)
GENMASK            35 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_SPDIFEN_MASK	GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
GENMASK            42 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_DRFMT_MASK	GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
GENMASK            54 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_NBTR_MASK	GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
GENMASK            60 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CR_INSEL_MASK	GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
GENMASK            76 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_XIMR_MASK	GENMASK(6, 0)
GENMASK            90 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SR_WIDTH5_MASK	GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
GENMASK            99 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_XIFCR_MASK	GENMASK(5, 2)
GENMASK           103 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_DR_MASK	GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
GENMASK           113 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR0_PT_MASK	GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
GENMASK           123 sound/soc/stm/stm32_spdifrx.c #define  SPDIFRX_DR1_PT_MASK	GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
GENMASK           127 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_DR_MASK	GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
GENMASK           132 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_DRNL1_MASK	GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
GENMASK           136 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DR1_DRNL2_MASK	GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
GENMASK           141 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CSR_USR_MASK	GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
GENMASK           146 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_CSR_CS_MASK	GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
GENMASK           154 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DIR_THI_MASK	GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
GENMASK           158 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_DIR_TLO_MASK	GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
GENMASK           166 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_VERR_MIN_MASK	GENMASK(3, 0)
GENMASK           167 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_VERR_MAJ_MASK	GENMASK(7, 4)
GENMASK           170 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_IDR_ID_MASK	GENMASK(31, 0)
GENMASK           173 sound/soc/stm/stm32_spdifrx.c #define SPDIFRX_SIDR_SID_MASK	GENMASK(31, 0)
GENMASK            25 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CTRL_SDO_EN_MASK		GENMASK(11, 8)
GENMASK            41 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FMT0_SR_MASK			GENMASK(5, 4)
GENMASK            43 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FMT0_WSS_MASK			GENMASK(3, 2)
GENMASK            45 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FMT0_FMT_MASK			GENMASK(1, 0)
GENMASK            59 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK	GENMASK(1, 0)
GENMASK            72 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CLK_DIV_BCLK_MASK		GENMASK(6, 4)
GENMASK            74 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CLK_DIV_MCLK_MASK		GENMASK(3, 0)
GENMASK            81 sound/soc/sunxi/sun4i-i2s.c #define SUN4I_I2S_CHAN_SEL_MASK			GENMASK(2, 0)
GENMASK            94 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_CTRL_MODE_MASK		GENMASK(5, 4)
GENMASK           102 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK		GENMASK(17, 8)
GENMASK           112 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK	GENMASK(6, 4)
GENMASK           114 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK	GENMASK(2, 0)
GENMASK           119 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_TX_CHAN_OFFSET_MASK		GENMASK(13, 12)
GENMASK           121 sound/soc/sunxi/sun4i-i2s.c #define SUN8I_I2S_TX_CHAN_EN_MASK		GENMASK(11, 4)
GENMASK            39 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_TXCFG_TXRATIO_MASK		GENMASK(8, 4)
GENMASK            40 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_TXCFG_FMTRVD		GENMASK(3, 2)
GENMASK            62 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_FCTL_TXTL_MASK		GENMASK(12, 8)
GENMASK            64 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_FCTL_RXTL_MASK		GENMASK(7, 3)
GENMASK            67 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_FCTL_RXOM_MASK		GENMASK(1, 0)
GENMASK            74 sound/soc/sunxi/sun4i-spdif.c 	#define SUN50I_H6_SPDIF_FCTL_TXTL_MASK		GENMASK(19, 12)
GENMASK            76 sound/soc/sunxi/sun4i-spdif.c 	#define SUN50I_H6_SPDIF_FCTL_RXTL_MASK		GENMASK(10, 4)
GENMASK            79 sound/soc/sunxi/sun4i-spdif.c 	#define SUN50I_H6_SPDIF_FCTL_RXOM_MASK		GENMASK(1, 0)
GENMASK           118 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK	GENMASK(27, 24)
GENMASK           120 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK		GENMASK(23, 20)
GENMASK           132 sound/soc/sunxi/sun4i-spdif.c 	#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK	GENMASK(7, 4)
GENMASK            22 sound/soc/sunxi/sun8i-adda-pr-regmap.c #define ADDA_PR_ADDR_MASK		GENMASK(4, 0)
GENMASK            24 sound/soc/sunxi/sun8i-adda-pr-regmap.c #define ADDA_PR_DATA_IN_MASK		GENMASK(7, 0)
GENMASK            26 sound/soc/sunxi/sun8i-adda-pr-regmap.c #define ADDA_PR_DATA_OUT_MASK		GENMASK(7, 0)
GENMASK            81 sound/soc/sunxi/sun8i-codec.c #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK		GENMASK(15, 12)
GENMASK            82 sound/soc/sunxi/sun8i-codec.c #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK		GENMASK(11, 8)
GENMASK            83 sound/soc/sunxi/sun8i-codec.c #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK	GENMASK(3, 2)
GENMASK            84 sound/soc/sunxi/sun8i-codec.c #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK	GENMASK(5, 4)
GENMASK            85 sound/soc/sunxi/sun8i-codec.c #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK	GENMASK(8, 6)
GENMASK            86 sound/soc/sunxi/sun8i-codec.c #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK	GENMASK(12, 9)
GENMASK            32 sound/soc/uniphier/aio-reg.h #define   A2APLLCTR0_APLLXPOW_MASK        GENMASK(3, 0)
GENMASK            40 sound/soc/uniphier/aio-reg.h #define   A2EXMCLKSEL0_EXMCLK_MASK        GENMASK(2, 0)
GENMASK            46 sound/soc/uniphier/aio-reg.h #define   A2AIOINPUTSEL_RXSEL_PCMI1_MASK      GENMASK(2, 0)
GENMASK            48 sound/soc/uniphier/aio-reg.h #define   A2AIOINPUTSEL_RXSEL_PCMI2_MASK      GENMASK(6, 4)
GENMASK            50 sound/soc/uniphier/aio-reg.h #define   A2AIOINPUTSEL_RXSEL_PCMI3_MASK      GENMASK(10, 8)
GENMASK            52 sound/soc/uniphier/aio-reg.h #define   A2AIOINPUTSEL_RXSEL_IECI1_MASK      GENMASK(14, 12)
GENMASK            67 sound/soc/uniphier/aio-reg.h #define   IPORTMXCTR1_LRSEL_MASK           GENMASK(11, 10)
GENMASK            76 sound/soc/uniphier/aio-reg.h #define   IPORTMXCTR1_CHSEL_MASK           GENMASK(6, 4)
GENMASK            83 sound/soc/uniphier/aio-reg.h #define   IPORTMXCTR1_FSSEL_MASK           GENMASK(3, 0)
GENMASK            98 sound/soc/uniphier/aio-reg.h #define   IPORTMXCTR2_ACLKSEL_MASK         GENMASK(19, 16)
GENMASK           112 sound/soc/uniphier/aio-reg.h #define   IPORTMXCTR2_DACCKSEL_MASK        GENMASK(9, 8)
GENMASK           124 sound/soc/uniphier/aio-reg.h #define   IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK        GENMASK(3, 0)
GENMASK           132 sound/soc/uniphier/aio-reg.h #define   IPORTMXMASK_IUXCKMSK_MASK        GENMASK(18, 16)
GENMASK           135 sound/soc/uniphier/aio-reg.h #define   IPORTMXMASK_XCKMSK_MASK          GENMASK(2, 0)
GENMASK           152 sound/soc/uniphier/aio-reg.h #define   PBINMXCTR_ENDIAN_MASK            GENMASK(5, 4)
GENMASK           157 sound/soc/uniphier/aio-reg.h #define   PBINMXCTR_MEMFMT_MASK            GENMASK(3, 0)
GENMASK           197 sound/soc/uniphier/aio-reg.h #define   OPORTMXCTR1_FSSEL_MASK           GENMASK(3, 0)
GENMASK           212 sound/soc/uniphier/aio-reg.h #define   OPORTMXCTR2_ACLKSEL_MASK         GENMASK(19, 16)
GENMASK           226 sound/soc/uniphier/aio-reg.h #define   OPORTMXCTR2_DACCKSEL_MASK        GENMASK(9, 8)
GENMASK           235 sound/soc/uniphier/aio-reg.h #define   OPORTMXCTR3_SRCSEL_MASK          GENMASK(18, 16)
GENMASK           262 sound/soc/uniphier/aio-reg.h #define   OPORTMXSRC1CTR_FSOCK_MASK        GENMASK(11, 10)
GENMASK           266 sound/soc/uniphier/aio-reg.h #define   OPORTMXSRC1CTR_FSICK_MASK        GENMASK(9, 8)
GENMASK           270 sound/soc/uniphier/aio-reg.h #define   OPORTMXSRC1CTR_FSIIPSEL_MASK     GENMASK(5, 4)
GENMASK           273 sound/soc/uniphier/aio-reg.h #define   OPORTMXSRC1CTR_FSISEL_MASK       GENMASK(3, 0)
GENMASK           317 sound/soc/uniphier/aio-reg.h #define   OPORTMXRATE_I_ACLKSRC_MASK       GENMASK(15, 12)
GENMASK           322 sound/soc/uniphier/aio-reg.h #define   OPORTMXRATE_I_ACLKSEL_MASK       GENMASK(11, 8)
GENMASK           333 sound/soc/uniphier/aio-reg.h #define   OPORTMXRATE_I_MCKSEL_MASK        GENMASK(7, 4)
GENMASK           337 sound/soc/uniphier/aio-reg.h #define   OPORTMXRATE_I_FSSEL_MASK         GENMASK(3, 0)
GENMASK           353 sound/soc/uniphier/aio-reg.h #define   OPORTMXMASK_IUDXMSK_MASK         GENMASK(28, 24)
GENMASK           356 sound/soc/uniphier/aio-reg.h #define   OPORTMXMASK_IUXCKMSK_MASK        GENMASK(18, 16)
GENMASK           359 sound/soc/uniphier/aio-reg.h #define   OPORTMXMASK_DXMSK_MASK           GENMASK(12, 8)
GENMASK           362 sound/soc/uniphier/aio-reg.h #define   OPORTMXMASK_XCKMSK_MASK          GENMASK(2, 0)
GENMASK           367 sound/soc/uniphier/aio-reg.h #define   OPORTMXTYVOLPARA1_SLOPEU_MASK    GENMASK(31, 16)
GENMASK           369 sound/soc/uniphier/aio-reg.h #define   OPORTMXTYVOLPARA2_FADE_MASK      GENMASK(17, 16)
GENMASK           373 sound/soc/uniphier/aio-reg.h #define   OPORTMXTYVOLPARA2_TARGET_MASK    GENMASK(15, 0)
GENMASK           375 sound/soc/uniphier/aio-reg.h #define   OPORTMXTYVOLGAINSTATUS_CUR_MASK  GENMASK(15, 0)
GENMASK           378 sound/soc/uniphier/aio-reg.h #define   OPORTMXTYSLOTCTR_SLOTSEL_MASK    GENMASK(11, 8)
GENMASK           396 sound/soc/uniphier/aio-reg.h #define   PBOUTMXCTR0_ENDIAN_MASK         GENMASK(5, 4)
GENMASK           401 sound/soc/uniphier/aio-reg.h #define   PBOUTMXCTR0_MEMFMT_MASK         GENMASK(3, 0)
GENMASK           419 sound/soc/uniphier/aio-reg.h #define   CDA2D_TEST_DDR_MODE_MASK         GENMASK(3, 2)
GENMASK           431 sound/soc/uniphier/aio-reg.h #define   CDA2D_CHMXAMODE_ENDIAN_MASK      GENMASK(17, 16)
GENMASK           437 sound/soc/uniphier/aio-reg.h #define   CDA2D_CHMXAMODE_AUPDT_MASK       GENMASK(5, 4)
GENMASK           440 sound/soc/uniphier/aio-reg.h #define   CDA2D_CHMXAMODE_TYPE_MASK        GENMASK(3, 2)
GENMASK           468 sound/soc/uniphier/aio-reg.h #define   CDA2D_RBMXPTRU_PTRU_MASK         GENMASK(1, 0)
GENMASK            40 sound/soc/uniphier/evea.c #define   ADAC1ODC_HP_DIS_RES_MASK            GENMASK(2, 1)
GENMASK            43 sound/soc/uniphier/evea.c #define   ADAC1ODC_ADAC_RAMPCLT_MASK          GENMASK(8, 7)
GENMASK            47 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_MM2S_CH_MASK	GENMASK(11, 8)
GENMASK            49 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_MM2S_XFER_MASK	GENMASK(14, 13)
GENMASK            53 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_S2MM_CH_MASK	GENMASK(27, 24)
GENMASK            55 sound/soc/xilinx/xlnx_formatter_pcm.c #define CFG_S2MM_XFER_MASK	GENMASK(30, 29)
GENMASK            23 sound/soc/xilinx/xlnx_i2s.c #define I2S_I2STIM_VALID_MASK		GENMASK(7, 0)
GENMASK            38 sound/soc/xilinx/xlnx_spdif.c #define XSPDIF_CLOCK_CONFIG_BITS_MASK	GENMASK(5, 2)
GENMASK            30 sound/soc/zte/zx-tdm.c #define DEAGULT_FIFO_THRES	GENMASK(4, 2)
GENMASK            41 sound/soc/zte/zx-tdm.c #define TXTH_MASK		GENMASK(5, 2)
GENMASK            42 sound/soc/zte/zx-tdm.c #define RXTH_MASK		GENMASK(5, 2)
GENMASK            52 sound/soc/zte/zx-tdm.c #define TIMING_SYNC_WIDTH_MASK	GENMASK(6, 5)
GENMASK            61 sound/soc/zte/zx-tdm.c #define TIMING_CLK_SEL_MASK	GENMASK(2, 0)
GENMASK            70 sound/soc/zte/zx-tdm.c #define INT_STATUS_MASK		GENMASK(6, 0)
GENMASK           144 tools/perf/arch/arm/util/cs-etm.c 	val &= GENMASK(28, 24);
GENMASK           222 tools/perf/arch/arm/util/cs-etm.c 	if (evsel->core.attr.config2 & GENMASK(31, 0))
GENMASK           166 tools/perf/util/cs-etm.h #define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
GENMASK            66 tools/power/x86/intel-speed-select/isst-core.c 	ctdp_level->pkg_tdp = resp & GENMASK(14, 0);
GENMASK            67 tools/power/x86/intel-speed-select/isst-core.c 	ctdp_level->tdp_ratio = (resp & GENMASK(23, 16)) >> 16;
GENMASK            87 tools/power/x86/intel-speed-select/isst-core.c 	ctdp_level->pkg_max_power = resp & GENMASK(14, 0);
GENMASK            88 tools/power/x86/intel-speed-select/isst-core.c 	ctdp_level->pkg_min_power = (resp & GENMASK(30, 16)) >> 16;
GENMASK           109 tools/power/x86/intel-speed-select/isst-core.c 	ctdp_level->t_proc_hot = resp & GENMASK(7, 0);
GENMASK           168 tools/power/x86/intel-speed-select/isst-core.c 	trl[0] = resp & GENMASK(7, 0);
GENMASK           169 tools/power/x86/intel-speed-select/isst-core.c 	trl[1] = (resp & GENMASK(15, 8)) >> 8;
GENMASK           170 tools/power/x86/intel-speed-select/isst-core.c 	trl[2] = (resp & GENMASK(23, 16)) >> 16;
GENMASK           171 tools/power/x86/intel-speed-select/isst-core.c 	trl[3] = (resp & GENMASK(31, 24)) >> 24;
GENMASK           183 tools/power/x86/intel-speed-select/isst-core.c 	trl[4] = resp & GENMASK(7, 0);
GENMASK           184 tools/power/x86/intel-speed-select/isst-core.c 	trl[5] = (resp & GENMASK(15, 8)) >> 8;
GENMASK           185 tools/power/x86/intel-speed-select/isst-core.c 	trl[6] = (resp & GENMASK(23, 16)) >> 16;
GENMASK           186 tools/power/x86/intel-speed-select/isst-core.c 	trl[7] = (resp & GENMASK(31, 24)) >> 24;
GENMASK           285 tools/power/x86/intel-speed-select/isst-core.c 	pbf_info->p1_high = (resp & GENMASK(15, 8)) >> 8;
GENMASK           577 virt/kvm/arm/hyp/vgic-v3-sr.c 	return pri & (GENMASK(7, 0) << bpr);
GENMASK           272 virt/kvm/arm/pmu.c 		return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);
GENMASK           460 virt/kvm/arm/pmu.c 		period &= GENMASK(31, 0);
GENMASK           611 virt/kvm/arm/pmu.c 		attr.sample_period = (-counter) & GENMASK(63, 0);
GENMASK           621 virt/kvm/arm/pmu.c 			attr.sample_period = (-counter) & GENMASK(63, 0);
GENMASK           623 virt/kvm/arm/pmu.c 			attr.sample_period = (-counter) & GENMASK(31, 0);
GENMASK          1508 virt/kvm/arm/vgic/vgic-its.c #define ITS_CMD_OFFSET(reg)		((reg) & GENMASK(19, 5))
GENMASK           174 virt/kvm/arm/vgic/vgic-mmio-v2.c 	u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
GENMASK           167 virt/kvm/arm/vgic/vgic-mmio-v3.c 	irq->mpidr = val & GENMASK(23, 0);
GENMASK           215 virt/kvm/arm/vgic/vgic-mmio-v3.c 	value = (u64)(mpidr & GENMASK(23, 0)) << 32;
GENMASK           544 virt/kvm/arm/vgic/vgic-mmio.c 		irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);