GEN9_MOCS_SIZE    147 drivers/gpu/drm/i915/gvt/mmio_context.c 	u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
GEN9_MOCS_SIZE    148 drivers/gpu/drm/i915/gvt/mmio_context.c 	u32 l3cc_table[GEN9_MOCS_SIZE / 2];
GEN9_MOCS_SIZE    175 drivers/gpu/drm/i915/gvt/mmio_context.c 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
GEN9_MOCS_SIZE    183 drivers/gpu/drm/i915/gvt/mmio_context.c 	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
GEN9_MOCS_SIZE    244 drivers/gpu/drm/i915/gvt/mmio_context.c 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
GEN9_MOCS_SIZE    248 drivers/gpu/drm/i915/gvt/mmio_context.c 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
GEN9_MOCS_SIZE    250 drivers/gpu/drm/i915/gvt/mmio_context.c 	for (index = 0; index < GEN9_MOCS_SIZE; index++) {
GEN9_MOCS_SIZE    271 drivers/gpu/drm/i915/gvt/mmio_context.c 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
GEN9_MOCS_SIZE    275 drivers/gpu/drm/i915/gvt/mmio_context.c 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
GEN9_MOCS_SIZE    277 drivers/gpu/drm/i915/gvt/mmio_context.c 	for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
GEN9_MOCS_SIZE    418 drivers/gpu/drm/i915/gvt/mmio_context.c 	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
GEN9_MOCS_SIZE    436 drivers/gpu/drm/i915/gvt/mmio_context.c 		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {