GEN8_R_PWR_CLK_STATE 599 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); GEN8_R_PWR_CLK_STATE 880 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); GEN8_R_PWR_CLK_STATE 3283 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); GEN8_R_PWR_CLK_STATE 1706 drivers/gpu/drm/i915/i915_perf.c CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE 1868 drivers/gpu/drm/i915/i915_perf.c GEN8_R_PWR_CLK_STATE,