GEN8_ROW_CHICKEN  198 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
GEN8_ROW_CHICKEN  245 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
GEN8_ROW_CHICKEN  271 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
GEN8_ROW_CHICKEN  296 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
GEN8_ROW_CHICKEN  423 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
GEN8_ROW_CHICKEN  483 drivers/gpu/drm/i915/gt/intel_workarounds.c 		WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
GEN8_ROW_CHICKEN  509 drivers/gpu/drm/i915/gt/intel_workarounds.c 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
GEN8_ROW_CHICKEN 2812 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
GEN8_ROW_CHICKEN  111 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */