GEN8_RING_PDP_UDW 1002 drivers/gpu/drm/i915/gem/i915_gem_context.c 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
GEN8_RING_PDP_UDW 1020 drivers/gpu/drm/i915/gem/i915_gem_context.c 			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
GEN8_RING_PDP_UDW  862 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
GEN8_RING_PDP_UDW  864 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
GEN8_RING_PDP_UDW  866 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1));
GEN8_RING_PDP_UDW  868 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
GEN8_RING_PDP_UDW 1938 drivers/gpu/drm/i915/gt/intel_lrc.c 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
GEN8_RING_PDP_UDW 3259 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
GEN8_RING_PDP_UDW 3261 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
GEN8_RING_PDP_UDW 3263 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
GEN8_RING_PDP_UDW 3265 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
GEN8_RING_PDP_UDW 1160 drivers/gpu/drm/i915/i915_gpu_error.c 					I915_READ(GEN8_RING_PDP_UDW(base, i));