GEN8_RING_PDP_LDW 1004 drivers/gpu/drm/i915/gem/i915_gem_context.c 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
GEN8_RING_PDP_LDW 1022 drivers/gpu/drm/i915/gem/i915_gem_context.c 			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
GEN8_RING_PDP_LDW  863 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
GEN8_RING_PDP_LDW  865 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2));
GEN8_RING_PDP_LDW  867 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1));
GEN8_RING_PDP_LDW  869 drivers/gpu/drm/i915/gt/intel_lrc.c 	regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
GEN8_RING_PDP_LDW 1940 drivers/gpu/drm/i915/gt/intel_lrc.c 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
GEN8_RING_PDP_LDW 3260 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
GEN8_RING_PDP_LDW 3262 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
GEN8_RING_PDP_LDW 3264 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
GEN8_RING_PDP_LDW 3266 drivers/gpu/drm/i915/gt/intel_lrc.c 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
GEN8_RING_PDP_LDW 1163 drivers/gpu/drm/i915/i915_gpu_error.c 					I915_READ(GEN8_RING_PDP_LDW(base, i));