GEN8_MASTER_IRQ  2738 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
GEN8_MASTER_IRQ   455 drivers/gpu/drm/i915/gvt/interrupt.c DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
GEN8_MASTER_IRQ   469 drivers/gpu/drm/i915/gvt/interrupt.c 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
GEN8_MASTER_IRQ   486 drivers/gpu/drm/i915/gvt/interrupt.c 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
GEN8_MASTER_IRQ   441 drivers/gpu/drm/i915/i915_debugfs.c 			   I915_READ(GEN8_MASTER_IRQ));
GEN8_MASTER_IRQ   517 drivers/gpu/drm/i915/i915_debugfs.c 			   I915_READ(GEN8_MASTER_IRQ));
GEN8_MASTER_IRQ  2043 drivers/gpu/drm/i915/i915_irq.c 		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
GEN8_MASTER_IRQ  2064 drivers/gpu/drm/i915/i915_irq.c 		I915_WRITE(GEN8_MASTER_IRQ, 0);
GEN8_MASTER_IRQ  2090 drivers/gpu/drm/i915/i915_irq.c 		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
GEN8_MASTER_IRQ  2807 drivers/gpu/drm/i915/i915_irq.c 	raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
GEN8_MASTER_IRQ  2815 drivers/gpu/drm/i915/i915_irq.c 	return raw_reg_read(regs, GEN8_MASTER_IRQ);
GEN8_MASTER_IRQ  2820 drivers/gpu/drm/i915/i915_irq.c 	raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
GEN8_MASTER_IRQ  3349 drivers/gpu/drm/i915/i915_irq.c 	I915_WRITE(GEN8_MASTER_IRQ, 0);
GEN8_MASTER_IRQ  3350 drivers/gpu/drm/i915/i915_irq.c 	POSTING_READ(GEN8_MASTER_IRQ);
GEN8_MASTER_IRQ  3891 drivers/gpu/drm/i915/i915_irq.c 	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
GEN8_MASTER_IRQ  3892 drivers/gpu/drm/i915/i915_irq.c 	POSTING_READ(GEN8_MASTER_IRQ);