GEN8_L3SQCREG4   2010 drivers/gpu/drm/i915/gt/intel_lrc.c 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
GEN8_L3SQCREG4   2016 drivers/gpu/drm/i915/gt/intel_lrc.c 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
GEN8_L3SQCREG4   2025 drivers/gpu/drm/i915/gt/intel_lrc.c 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
GEN8_L3SQCREG4   1081 drivers/gpu/drm/i915/gt/intel_workarounds.c 	whitelist_reg(w, GEN8_L3SQCREG4);
GEN8_L3SQCREG4   1102 drivers/gpu/drm/i915/gt/intel_workarounds.c 	whitelist_reg(w, GEN8_L3SQCREG4);
GEN8_L3SQCREG4   1269 drivers/gpu/drm/i915/gt/intel_workarounds.c 			    GEN8_L3SQCREG4,
GEN8_L3SQCREG4   1298 drivers/gpu/drm/i915/gt/intel_workarounds.c 			    GEN8_L3SQCREG4,
GEN8_L3SQCREG4   1368 drivers/gpu/drm/i915/gt/intel_workarounds.c 			    GEN8_L3SQCREG4,
GEN8_L3SQCREG4    895 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		{ GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
GEN8_L3SQCREG4    482 drivers/gpu/drm/i915/gvt/handlers.c 	GEN8_L3SQCREG4,//_MMIO(0xb118)
GEN8_L3SQCREG4   2820 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
GEN8_L3SQCREG4    105 drivers/gpu/drm/i915/gvt/mmio_context.c 	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */