GEN8_3LVL_PDPES  1012 drivers/gpu/drm/i915/gem/i915_gem_context.c 		cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
GEN8_3LVL_PDPES  1016 drivers/gpu/drm/i915/gem/i915_gem_context.c 		*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
GEN8_3LVL_PDPES  1017 drivers/gpu/drm/i915/gem/i915_gem_context.c 		for (i = GEN8_3LVL_PDPES; i--; ) {
GEN8_3LVL_PDPES  1928 drivers/gpu/drm/i915/gt/intel_lrc.c 	cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
GEN8_3LVL_PDPES  1933 drivers/gpu/drm/i915/gt/intel_lrc.c 	*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
GEN8_3LVL_PDPES  1934 drivers/gpu/drm/i915/gt/intel_lrc.c 	for (i = GEN8_3LVL_PDPES; i--; ) {
GEN8_3LVL_PDPES   134 drivers/gpu/drm/i915/gvt/gtt.h #define GVT_RING_CTX_NR_PDPS	GEN8_3LVL_PDPES
GEN8_3LVL_PDPES   157 drivers/gpu/drm/i915/gvt/gvt.h 		u64 i915_context_pdps[GEN8_3LVL_PDPES];
GEN8_3LVL_PDPES  1154 drivers/gpu/drm/i915/gvt/scheduler.c 		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
GEN8_3LVL_PDPES  1215 drivers/gpu/drm/i915/gvt/scheduler.c 		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
GEN8_3LVL_PDPES   852 drivers/gpu/drm/i915/i915_gem_gtt.c 		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
GEN8_3LVL_PDPES  1413 drivers/gpu/drm/i915/i915_gem_gtt.c 	GEM_BUG_ON(gen8_pd_top_count(vm) != GEN8_3LVL_PDPES);
GEN8_3LVL_PDPES  1415 drivers/gpu/drm/i915/i915_gem_gtt.c 	for (idx = 0; idx < GEN8_3LVL_PDPES; idx++) {