GEN7_HALF_SLICE_CHICKEN1 444 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, GEN7_HALF_SLICE_CHICKEN1 468 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, GEN7_HALF_SLICE_CHICKEN1 1947 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); GEN7_HALF_SLICE_CHICKEN1 106 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ GEN7_HALF_SLICE_CHICKEN1 9413 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, GEN7_HALF_SLICE_CHICKEN1 9504 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,