GC_HWIP           114 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 	[GC_HWIP]	= GC_HWID,
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_HWIP           617 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
GC_HWIP           618 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
GC_HWIP           628 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
GC_HWIP           629 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
GC_HWIP           112 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		base = adev->reg_offset[GC_HWIP][0][1];
GC_HWIP           116 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		base = adev->reg_offset[GC_HWIP][0][0];
GC_HWIP            79 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0;	\
GC_HWIP            80 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1;	\
GC_HWIP            81 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT;	\
GC_HWIP           102 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2;	\
GC_HWIP           103 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3;	\
GC_HWIP           104 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;   \
GC_HWIP           105 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;   \
GC_HWIP           118 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_HWIP            35 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));