GC 230 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); GC 231 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); GC 300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), GC 338 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - GC 381 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); GC 384 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); GC 389 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); GC 392 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) GC 399 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); GC 428 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), GC 430 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), GC 432 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), GC 434 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), GC 437 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), GC 442 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), GC 447 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); GC 474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); GC 475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) GC 604 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); GC 609 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && GC 610 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) GC 655 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); GC 725 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); GC 729 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); GC 890 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); GC 891 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); GC 900 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); GC 929 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); GC 930 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); GC 932 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), GC 934 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), GC 937 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); GC 938 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); GC 141 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); GC 142 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); GC 220 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), GC 282 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); GC 285 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); GC 290 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); GC 293 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) GC 300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); GC 329 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), GC 331 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), GC 333 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), GC 335 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), GC 337 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), GC 342 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), GC 347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); GC 374 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); GC 375 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) GC 500 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); GC 505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && GC 506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) GC 549 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); GC 563 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); GC 567 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); GC 757 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); GC 758 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); GC 767 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); GC 230 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c info = &bhdr->table_list[GC]; GC 393 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c le16_to_cpu(bhdr->table_list[GC].offset)); GC 94 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), GC 95 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), GC 96 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), GC 97 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), GC 98 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), GC 99 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 100 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), GC 101 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 102 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), GC 103 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), GC 104 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), GC 105 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), GC 106 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), GC 107 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), GC 108 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), GC 109 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), GC 110 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), GC 111 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), GC 112 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 113 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), GC 114 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), GC 115 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), GC 116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), GC 117 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), GC 118 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), GC 119 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), GC 120 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), GC 121 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), GC 122 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 123 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), GC 124 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), GC 125 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), GC 126 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), GC 127 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), GC 128 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), GC 129 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), GC 130 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) GC 140 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), GC 141 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 142 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), GC 143 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), GC 144 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), GC 145 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), GC 146 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 147 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 148 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 149 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), GC 150 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), GC 151 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), GC 152 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), GC 153 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), GC 154 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), GC 155 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), GC 156 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), GC 157 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), GC 158 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), GC 159 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 160 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), GC 161 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), GC 162 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), GC 163 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), GC 164 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), GC 165 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), GC 166 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), GC 167 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 168 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), GC 169 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), GC 170 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), GC 171 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), GC 172 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), GC 173 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), GC 174 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), GC 179 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), GC 180 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 181 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), GC 182 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), GC 183 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), GC 184 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), GC 185 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 186 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), GC 187 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 188 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), GC 189 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), GC 190 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), GC 191 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), GC 192 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), GC 193 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), GC 194 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), GC 195 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), GC 196 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), GC 197 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), GC 198 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), GC 199 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), GC 200 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), GC 201 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), GC 202 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), GC 203 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), GC 204 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), GC 205 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), GC 206 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), GC 207 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), GC 208 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), GC 209 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), GC 210 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), GC 211 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 212 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), GC 213 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), GC 214 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), GC 215 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), GC 216 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), GC 217 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), GC 218 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) GC 396 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); GC 952 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; GC 1112 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, GC 1115 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); GC 1122 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, GC 1128 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); GC 1209 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); GC 1519 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); GC 1526 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); GC 1527 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); GC 1616 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); GC 1617 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); GC 1625 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); GC 1626 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); GC 1627 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); GC 1628 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); GC 1643 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); GC 1644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); GC 1645 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); GC 1646 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); GC 1702 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); GC 1706 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); GC 1708 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); GC 1712 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); GC 1724 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | GC 1725 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); GC 1737 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); GC 1753 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); GC 1759 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); GC 1774 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); GC 1785 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); GC 1811 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, GC 1813 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, GC 1815 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); GC 1838 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); GC 1841 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); GC 1846 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); GC 1848 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); GC 1857 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); GC 1871 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); GC 1881 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); GC 1890 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); GC 1893 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); GC 1912 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, GC 1916 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, GC 1919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); GC 1947 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); GC 1950 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); GC 2223 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); GC 2224 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); GC 2225 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); GC 2227 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); GC 2234 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); GC 2251 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); GC 2253 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); GC 2257 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); GC 2272 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, GC 2274 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, GC 2288 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); GC 2290 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); GC 2294 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); GC 2309 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, GC 2311 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, GC 2325 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); GC 2327 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); GC 2331 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); GC 2346 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, GC 2348 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, GC 2362 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); GC 2364 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); GC 2368 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); GC 2383 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, GC 2385 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, GC 2398 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); GC 2399 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); GC 2437 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); GC 2446 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); GC 2449 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) GC 2495 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); GC 2497 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); GC 2501 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); GC 2516 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); GC 2521 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); GC 2522 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, GC 2524 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, GC 2565 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); GC 2567 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); GC 2571 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); GC 2586 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); GC 2591 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, GC 2593 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, GC 2634 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); GC 2636 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); GC 2640 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); GC 2655 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); GC 2660 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, GC 2662 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, GC 2707 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, GC 2709 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); GC 2742 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; GC 2781 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); GC 2784 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); GC 2792 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); GC 2802 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); GC 2805 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); GC 2807 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, GC 2820 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); GC 2823 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); GC 2837 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); GC 2841 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); GC 2842 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); GC 2846 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); GC 2847 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & GC 2851 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, GC 2853 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, GC 2857 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); GC 2860 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); GC 2861 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); GC 2863 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); GC 2875 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); GC 2878 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); GC 2879 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); GC 2882 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); GC 2883 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & GC 2886 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, GC 2888 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, GC 2892 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); GC 2895 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); GC 2896 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); GC 2897 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); GC 2922 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); GC 2924 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, GC 2955 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); GC 2957 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); GC 2961 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); GC 2976 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); GC 2980 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); GC 2982 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & GC 2984 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, GC 2988 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); GC 2991 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, GC 2994 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); GC 3010 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); GC 3013 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); GC 3015 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); GC 3035 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); GC 3042 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); GC 3048 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); GC 3053 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); GC 3075 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); GC 3084 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); GC 3097 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); GC 3112 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); GC 3113 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); GC 3116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); GC 3117 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); GC 3120 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); GC 3123 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); GC 3125 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, GC 3127 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); GC 3130 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); GC 3131 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); GC 3134 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); GC 3135 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); GC 3138 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); GC 3141 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); GC 3142 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); GC 3145 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); GC 3148 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); GC 3280 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); GC 3287 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); GC 3317 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); GC 3327 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); GC 3355 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); GC 3371 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); GC 3376 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); GC 3381 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); GC 3398 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); GC 3401 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, GC 3403 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, GC 3407 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, GC 3411 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, GC 3415 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { GC 3416 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); GC 3418 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) GC 3422 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, GC 3424 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, GC 3426 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, GC 3428 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, GC 3433 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, GC 3435 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, GC 3439 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, GC 3443 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, GC 3445 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, GC 3449 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, GC 3453 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, GC 3455 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, GC 3459 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, GC 3461 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, GC 3466 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, GC 3468 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, GC 3472 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, GC 3476 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, GC 3478 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, GC 3482 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); GC 3484 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, GC 3488 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, GC 3492 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); GC 3692 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); GC 3694 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); GC 3696 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); GC 3698 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { GC 3699 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); GC 3702 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); GC 3713 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); GC 3716 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << GC 3718 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << GC 3720 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3721 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3724 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << GC 3726 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << GC 3728 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3729 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3732 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << GC 3734 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << GC 3736 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3737 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3740 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << GC 3742 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << GC 3744 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3745 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3748 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << GC 3750 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << GC 3752 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3753 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3756 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << GC 3758 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << GC 3760 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3761 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3764 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << GC 3766 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << GC 3768 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); GC 3769 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); GC 3887 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), GC 3902 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & GC 3919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); GC 3941 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); GC 3958 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 3961 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); GC 3962 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 3967 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); GC 3968 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 3983 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); GC 3984 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | GC 3985 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); GC 4001 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, GC 4006 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, GC 4011 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, GC 4016 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, GC 4057 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); GC 4068 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); GC 4072 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) GC 4083 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); GC 4094 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4103 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4109 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4112 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); GC 4116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4119 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); GC 4124 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4130 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4133 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4136 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); GC 4140 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4143 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); GC 4156 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4161 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4163 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4170 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); GC 4173 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); GC 4177 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); GC 4180 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4186 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); GC 4196 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4205 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4208 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4215 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); GC 4218 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); GC 4222 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); GC 4224 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4229 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); GC 4325 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4330 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4339 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4344 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4349 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4372 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); GC 4373 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; GC 4388 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); GC 4389 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); GC 4606 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); GC 4863 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); GC 4866 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); GC 4910 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); GC 4913 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); GC 4916 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); GC 4919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); GC 5033 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5052 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5123 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); GC 5125 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); GC 5131 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); GC 5134 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); GC 5141 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); GC 5144 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); GC 5398 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); GC 5404 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); GC 5405 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); GC 503 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), GC 504 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), GC 505 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), GC 506 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), GC 507 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), GC 508 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 509 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), GC 510 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), GC 511 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), GC 512 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), GC 513 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), GC 514 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), GC 515 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), GC 516 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), GC 517 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), GC 518 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), GC 519 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), GC 520 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), GC 521 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), GC 522 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) GC 527 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), GC 528 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), GC 529 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), GC 530 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), GC 531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), GC 532 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), GC 533 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), GC 534 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), GC 535 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), GC 536 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), GC 537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), GC 538 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), GC 539 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), GC 540 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), GC 541 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), GC 542 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), GC 543 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), GC 544 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) GC 549 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), GC 550 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), GC 551 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), GC 552 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), GC 553 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), GC 554 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), GC 555 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), GC 556 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), GC 557 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), GC 558 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), GC 559 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) GC 564 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), GC 565 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), GC 566 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), GC 567 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), GC 568 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), GC 569 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), GC 570 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), GC 571 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), GC 572 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), GC 573 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), GC 575 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), GC 576 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), GC 577 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), GC 578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), GC 579 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), GC 580 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), GC 581 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), GC 582 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), GC 583 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), GC 584 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), GC 585 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), GC 586 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), GC 587 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) GC 592 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), GC 593 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), GC 594 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), GC 595 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), GC 596 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), GC 597 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), GC 598 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) GC 603 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), GC 604 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), GC 605 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), GC 606 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), GC 607 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), GC 608 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), GC 609 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), GC 610 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), GC 611 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), GC 612 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), GC 613 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), GC 614 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), GC 615 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), GC 616 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), GC 617 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), GC 618 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), GC 619 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), GC 620 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), GC 621 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), GC 626 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), GC 627 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), GC 628 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), GC 629 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), GC 630 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), GC 631 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), GC 632 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), GC 633 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 634 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), GC 635 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), GC 636 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), GC 637 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), GC 642 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), GC 643 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), GC 644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) GC 649 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), GC 650 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), GC 651 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), GC 652 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), GC 653 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), GC 654 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), GC 655 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), GC 656 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), GC 657 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), GC 658 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), GC 659 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), GC 660 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), GC 661 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), GC 662 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), GC 663 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), GC 664 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) GC 669 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), GC 670 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), GC 671 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), GC 672 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), GC 673 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), GC 674 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), GC 675 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), GC 676 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), GC 677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), GC 678 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), GC 679 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), GC 680 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), GC 681 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) GC 686 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), GC 687 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), GC 688 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), GC 689 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), GC 690 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), GC 691 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), GC 692 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), GC 693 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), GC 801 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); GC 1514 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); GC 1524 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); GC 1537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); GC 1538 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); GC 1539 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); GC 1540 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); GC 1543 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); GC 1546 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); GC 1551 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); GC 1557 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); GC 1560 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); GC 1563 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); GC 1575 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); GC 1586 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); GC 1587 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); GC 1588 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); GC 1589 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); GC 1592 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); GC 1595 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); GC 1600 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); GC 1606 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); GC 1609 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); GC 1612 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); GC 1624 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); GC 1632 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); GC 1778 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, GC 1783 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); GC 1790 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, GC 1798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); GC 1888 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); GC 1913 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); GC 1923 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); GC 2027 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); GC 2028 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); GC 2091 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); GC 2097 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); GC 2102 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); GC 2106 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); GC 2110 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); GC 2114 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); GC 2118 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); GC 2122 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); GC 2133 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), GC 2149 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); GC 2397 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); GC 2404 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); GC 2405 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); GC 2465 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); GC 2466 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); GC 2474 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); GC 2475 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); GC 2476 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); GC 2477 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); GC 2492 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); GC 2493 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); GC 2494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); GC 2495 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); GC 2504 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); GC 2510 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); GC 2523 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); GC 2524 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); GC 2530 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); GC 2535 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); GC 2556 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) GC 2578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) GC 2587 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); GC 2594 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); GC 2600 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), GC 2602 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), GC 2604 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), GC 2675 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); GC 2677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); GC 2680 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), GC 2683 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), GC 2687 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), GC 2692 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), GC 2698 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); GC 2702 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); GC 2703 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); GC 2707 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); GC 2720 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), GC 2722 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); GC 2725 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), GC 2728 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), GC 2734 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) GC 2738 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) GC 2750 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); GC 2787 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); GC 2790 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); GC 2798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); GC 2800 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); GC 2803 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); GC 2805 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); GC 2808 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); GC 2810 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); GC 2815 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); GC 2827 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2832 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2841 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2846 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2855 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2860 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2868 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2873 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2881 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2886 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2890 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); GC 2898 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2903 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2911 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); GC 2916 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); GC 2949 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); GC 2956 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); GC 2958 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); GC 2968 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); GC 2979 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); GC 2985 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); GC 2989 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); GC 3010 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, GC 3013 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); GC 3014 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); GC 3031 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); GC 3067 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); GC 3076 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); GC 3109 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); GC 3111 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); GC 3112 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); GC 3119 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); GC 3121 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); GC 3122 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); GC 3129 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); GC 3131 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); GC 3132 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); GC 3145 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); GC 3146 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); GC 3190 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); GC 3207 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); GC 3210 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); GC 3220 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); GC 3224 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); GC 3225 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); GC 3229 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); GC 3230 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); GC 3233 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); GC 3234 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); GC 3237 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); GC 3240 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); GC 3241 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); GC 3243 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); GC 3252 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); GC 3256 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); GC 3258 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, GC 3274 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); GC 3276 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, GC 3306 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); GC 3308 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, GC 3310 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, GC 3314 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, GC 3317 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, GC 3320 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, GC 3334 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); GC 3337 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); GC 3339 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); GC 3441 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); GC 3448 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); GC 3478 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); GC 3488 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); GC 3516 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); GC 3532 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); GC 3537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); GC 3542 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); GC 3559 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); GC 3561 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, GC 3563 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, GC 3567 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, GC 3571 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, GC 3575 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { GC 3576 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); GC 3578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) GC 3582 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, GC 3584 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, GC 3586 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, GC 3588 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, GC 3593 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, GC 3595 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, GC 3599 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, GC 3603 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, GC 3605 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, GC 3609 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, GC 3613 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, GC 3615 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, GC 3619 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, GC 3621 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, GC 3626 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, GC 3628 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, GC 3632 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, GC 3636 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, GC 3638 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, GC 3642 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); GC 3644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, GC 3648 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, GC 3652 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); GC 3663 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { GC 3665 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); GC 3668 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) GC 3677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); GC 3680 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, GC 3684 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); GC 3685 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); GC 3686 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); GC 3687 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); GC 3688 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); GC 3689 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); GC 3690 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); GC 3691 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); GC 3960 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); GC 3999 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), GC 4026 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); GC 4045 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); GC 4063 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 4066 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); GC 4067 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 4072 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); GC 4073 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); GC 4088 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); GC 4089 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | GC 4090 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); GC 4106 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, GC 4111 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, GC 4116 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, GC 4121 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, GC 4160 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, GC 4161 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, GC 4162 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, GC 4163 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, GC 4164 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */ GC 4165 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 }, GC 4166 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 }, GC 4167 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, GC 4168 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */ GC 4169 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ GC 4173 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, GC 4174 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, GC 4175 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, GC 4176 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, GC 4177 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */ GC 4178 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 }, GC 4179 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 }, GC 4180 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, GC 4181 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */ GC 4182 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, GC 4186 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, GC 4187 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, GC 4188 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, GC 4189 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, GC 4190 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, GC 4191 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, GC 4192 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, GC 4193 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, GC 4194 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, GC 4195 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, GC 4196 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, GC 4197 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, GC 4198 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, GC 4199 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, GC 4200 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, GC 4201 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, GC 4202 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, GC 4203 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, GC 4204 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, GC 4205 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, GC 4206 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, GC 4207 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, GC 4208 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, GC 4209 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, GC 4210 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, GC 4211 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, GC 4212 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, GC 4213 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, GC 4214 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, GC 4215 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, GC 4216 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, GC 4217 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, GC 4232 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); GC 4233 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); GC 4258 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); GC 4319 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) GC 4347 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) GC 4388 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); GC 4545 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); GC 4559 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); GC 4563 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) GC 4574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); GC 4626 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4639 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4645 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4648 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); GC 4652 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4655 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); GC 4660 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4671 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4674 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); GC 4681 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4684 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); GC 4704 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4709 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4712 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4720 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); GC 4723 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); GC 4727 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); GC 4730 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4736 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); GC 4750 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4759 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); GC 4762 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4774 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); GC 4777 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); GC 4781 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); GC 4783 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4788 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); GC 4912 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); GC 4917 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); GC 4926 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); GC 4931 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); GC 4937 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); GC 4961 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); GC 4962 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; GC 4977 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); GC 4978 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); GC 5167 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; GC 5233 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); GC 5234 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15_RLC(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); GC 5287 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); GC 5476 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmSQ_CMD, value); GC 5485 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5509 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); GC 5512 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); GC 5515 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); GC 5518 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); GC 5555 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5574 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5585 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ GC 5589 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ GC 5599 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5608 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, GC 5762 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, GC 5765 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, GC 5768 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, GC 5770 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, GC 5772 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, GC 5775 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, GC 5777 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, GC 5780 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, GC 5783 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, GC 5785 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, GC 5787 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, GC 5789 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, GC 5792 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, GC 5794 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), GC 5798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, GC 5802 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, GC 5805 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, GC 5809 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, GC 5813 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, GC 5817 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, GC 5820 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1, GC 5822 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, GC 5825 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, GC 5827 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, GC 5829 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, GC 5831 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16, GC 5833 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, GC 5835 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2, GC 5837 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5840 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5843 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5846 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5849 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5852 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5854 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5856 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5858 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5860 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5862 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16, GC 5864 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, GC 5866 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16, GC 5868 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, GC 5870 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), GC 5873 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, GC 5875 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), GC 5878 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, GC 5880 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72, GC 5882 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5885 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5888 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5890 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5892 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5894 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5897 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16, GC 5900 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, GC 5903 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, GC 5906 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16, GC 5908 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5911 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5914 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5917 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5920 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5923 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5926 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16, GC 5929 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), GC 5932 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, GC 5935 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), GC 5938 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, GC 5941 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), GC 5944 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1, GC 5947 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5950 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5953 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5956 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5960 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, GC 5963 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5965 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5967 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, GC 5970 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, GC 5972 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6, GC 5975 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5978 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5981 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5984 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5988 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, GC 5991 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5993 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5995 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, GC 5998 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6, GC 6000 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6003 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6006 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6009 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6012 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6015 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6017 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6019 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6021 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6023 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32, GC 6025 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6028 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6031 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6034 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6036 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6038 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6040 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6042 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6044 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32, GC 6432 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); GC 6439 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); GC 6440 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); GC 35 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; GC 45 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, GC 48 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, GC 58 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, GC 60 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, GC 63 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, GC 65 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, GC 74 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); GC 75 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); GC 76 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); GC 79 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, GC 89 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, GC 93 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, GC 99 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, GC 101 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, GC 105 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, GC 107 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, GC 110 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, GC 119 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); GC 132 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); GC 140 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); GC 149 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); GC 151 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); GC 154 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); GC 166 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); GC 171 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); GC 178 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); GC 181 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); GC 186 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, GC 188 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, GC 191 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, GC 193 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, GC 196 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); GC 197 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); GC 215 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); GC 241 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); GC 242 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); GC 243 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); GC 244 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, GC 246 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, GC 256 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, GC 258 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, GC 271 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, GC 273 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, GC 298 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); GC 301 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); GC 307 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); GC 310 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); GC 311 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); GC 324 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); GC 355 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); GC 363 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, GC 366 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, GC 369 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM); GC 371 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); GC 373 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); GC 375 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); GC 377 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); GC 379 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); GC 33 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); GC 48 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), GC 36 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); GC 46 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; GC 54 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, GC 57 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, GC 65 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, GC 67 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, GC 70 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, GC 72 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, GC 81 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); GC 82 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); GC 83 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); GC 86 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, GC 88 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, GC 94 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, GC 96 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, GC 100 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, GC 102 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, GC 105 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, GC 115 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); GC 127 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); GC 135 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); GC 146 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); GC 148 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); GC 151 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); GC 163 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); GC 168 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); GC 175 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); GC 178 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); GC 183 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, GC 185 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, GC 188 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, GC 190 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, GC 193 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); GC 194 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); GC 204 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); GC 229 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); GC 230 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); GC 231 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); GC 232 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, GC 234 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, GC 244 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, GC 246 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, GC 259 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, GC 261 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, GC 286 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); GC 289 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); GC 293 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); GC 296 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); GC 297 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); GC 310 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); GC 340 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); GC 348 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, GC 351 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, GC 354 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); GC 356 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); GC 358 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); GC 360 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); GC 362 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); GC 364 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); GC 192 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); GC 194 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); GC 197 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, GC 201 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); GC 204 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); GC 208 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); GC 210 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); GC 216 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); GC 241 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); GC 248 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, GC 252 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, GC 254 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, GC 258 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF); GC 261 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO, GC 263 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI, GC 267 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF); GC 270 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); GC 273 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); GC 276 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); GC 278 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); GC 97 drivers/gpu/drm/amd/amdgpu/nv.c address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); GC 98 drivers/gpu/drm/amd/amdgpu/nv.c data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); GC 111 drivers/gpu/drm/amd/amdgpu/nv.c address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); GC 112 drivers/gpu/drm/amd/amdgpu/nv.c data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); GC 140 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); GC 162 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, GC 163 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, GC 164 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, GC 165 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, GC 166 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, GC 167 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, GC 172 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, GC 173 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, GC 174 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, GC 175 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, GC 176 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, GC 177 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, GC 178 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, GC 179 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, GC 180 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, GC 181 drivers/gpu/drm/amd/amdgpu/nv.c { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, GC 208 drivers/gpu/drm/amd/amdgpu/nv.c if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) GC 259 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); GC 260 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); GC 265 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); GC 266 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); GC 271 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); GC 272 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); GC 277 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); GC 278 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); GC 283 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); GC 284 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); GC 289 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); GC 290 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); GC 583 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); GC 584 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); GC 589 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); GC 590 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); GC 595 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); GC 596 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); GC 601 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); GC 602 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); GC 607 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); GC 608 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); GC 614 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); GC 615 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); GC 413 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); GC 414 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); GC 419 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); GC 420 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); GC 425 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); GC 426 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); GC 431 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); GC 432 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); GC 437 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); GC 438 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); GC 443 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); GC 444 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); GC 491 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); GC 492 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); GC 497 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); GC 498 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); GC 503 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); GC 504 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); GC 509 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); GC 510 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); GC 515 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); GC 516 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); GC 521 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); GC 522 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); GC 65 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), GC 66 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 67 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 68 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 69 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 70 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 71 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 72 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 73 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 74 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 75 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 76 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), GC 77 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), GC 78 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 79 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 80 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 81 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 82 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 83 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 84 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 85 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 86 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 87 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 88 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) GC 92 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), GC 93 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), GC 97 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 98 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 102 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 103 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), GC 203 drivers/gpu/drm/amd/amdgpu/soc15.c address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); GC 204 drivers/gpu/drm/amd/amdgpu/soc15.c data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); GC 217 drivers/gpu/drm/amd/amdgpu/soc15.c address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); GC 218 drivers/gpu/drm/amd/amdgpu/soc15.c data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); GC 232 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); GC 233 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); GC 243 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); GC 244 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); GC 254 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); GC 255 drivers/gpu/drm/amd/amdgpu/soc15.c r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); GC 265 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); GC 266 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); GC 295 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); GC 350 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, GC 351 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, GC 352 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, GC 353 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, GC 354 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, GC 355 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, GC 358 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, GC 359 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, GC 360 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, GC 361 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, GC 362 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, GC 363 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, GC 364 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, GC 365 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, GC 366 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, GC 367 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, GC 368 drivers/gpu/drm/amd/amdgpu/soc15.c { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, GC 395 drivers/gpu/drm/amd/amdgpu/soc15.c if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) GC 397 drivers/gpu/drm/amd/amdgpu/soc15.c else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) GC 456 drivers/gpu/drm/amd/amdgpu/soc15.c if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || GC 457 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || GC 458 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || GC 459 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) GC 945 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); GC 960 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); GC 996 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); GC 1005 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); GC 1057 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); GC 1068 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); GC 1107 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); GC 1116 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); GC 1166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);