GAMMA_BIAS         42 arch/alpha/include/asm/core_t2.h #define T2_CONF		        (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
GAMMA_BIAS         43 arch/alpha/include/asm/core_t2.h #define T2_IO			(IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
GAMMA_BIAS         44 arch/alpha/include/asm/core_t2.h #define T2_SPARSE_MEM		(IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
GAMMA_BIAS         45 arch/alpha/include/asm/core_t2.h #define T2_DENSE_MEM	        (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
GAMMA_BIAS         47 arch/alpha/include/asm/core_t2.h #define T2_IOCSR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
GAMMA_BIAS         48 arch/alpha/include/asm/core_t2.h #define T2_CERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
GAMMA_BIAS         49 arch/alpha/include/asm/core_t2.h #define T2_CERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
GAMMA_BIAS         50 arch/alpha/include/asm/core_t2.h #define T2_CERR3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
GAMMA_BIAS         51 arch/alpha/include/asm/core_t2.h #define T2_PERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
GAMMA_BIAS         52 arch/alpha/include/asm/core_t2.h #define T2_PERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
GAMMA_BIAS         53 arch/alpha/include/asm/core_t2.h #define T2_PSCR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
GAMMA_BIAS         54 arch/alpha/include/asm/core_t2.h #define T2_HAE_1		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
GAMMA_BIAS         55 arch/alpha/include/asm/core_t2.h #define T2_HAE_2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
GAMMA_BIAS         56 arch/alpha/include/asm/core_t2.h #define T2_HBASE		(IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
GAMMA_BIAS         57 arch/alpha/include/asm/core_t2.h #define T2_WBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
GAMMA_BIAS         58 arch/alpha/include/asm/core_t2.h #define T2_WMASK1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
GAMMA_BIAS         59 arch/alpha/include/asm/core_t2.h #define T2_TBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
GAMMA_BIAS         60 arch/alpha/include/asm/core_t2.h #define T2_WBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
GAMMA_BIAS         61 arch/alpha/include/asm/core_t2.h #define T2_WMASK2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
GAMMA_BIAS         62 arch/alpha/include/asm/core_t2.h #define T2_TBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
GAMMA_BIAS         63 arch/alpha/include/asm/core_t2.h #define T2_TLBBR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
GAMMA_BIAS         64 arch/alpha/include/asm/core_t2.h #define T2_IVR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
GAMMA_BIAS         65 arch/alpha/include/asm/core_t2.h #define T2_HAE_3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
GAMMA_BIAS         66 arch/alpha/include/asm/core_t2.h #define T2_HAE_4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
GAMMA_BIAS         69 arch/alpha/include/asm/core_t2.h #define T2_WBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
GAMMA_BIAS         70 arch/alpha/include/asm/core_t2.h #define T2_WMASK3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
GAMMA_BIAS         71 arch/alpha/include/asm/core_t2.h #define T2_TBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
GAMMA_BIAS         73 arch/alpha/include/asm/core_t2.h #define T2_TDR0			(IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
GAMMA_BIAS         74 arch/alpha/include/asm/core_t2.h #define T2_TDR1			(IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
GAMMA_BIAS         75 arch/alpha/include/asm/core_t2.h #define T2_TDR2			(IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
GAMMA_BIAS         76 arch/alpha/include/asm/core_t2.h #define T2_TDR3			(IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
GAMMA_BIAS         77 arch/alpha/include/asm/core_t2.h #define T2_TDR4			(IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
GAMMA_BIAS         78 arch/alpha/include/asm/core_t2.h #define T2_TDR5			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
GAMMA_BIAS         79 arch/alpha/include/asm/core_t2.h #define T2_TDR6			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
GAMMA_BIAS         80 arch/alpha/include/asm/core_t2.h #define T2_TDR7			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
GAMMA_BIAS         82 arch/alpha/include/asm/core_t2.h #define T2_WBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
GAMMA_BIAS         83 arch/alpha/include/asm/core_t2.h #define T2_WMASK4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
GAMMA_BIAS         84 arch/alpha/include/asm/core_t2.h #define T2_TBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
GAMMA_BIAS         86 arch/alpha/include/asm/core_t2.h #define T2_AIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
GAMMA_BIAS         87 arch/alpha/include/asm/core_t2.h #define T2_VAR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
GAMMA_BIAS         88 arch/alpha/include/asm/core_t2.h #define T2_DIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
GAMMA_BIAS         89 arch/alpha/include/asm/core_t2.h #define T2_ICE			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
GAMMA_BIAS        128 arch/alpha/include/asm/core_t2.h #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
GAMMA_BIAS        129 arch/alpha/include/asm/core_t2.h #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
GAMMA_BIAS        130 arch/alpha/include/asm/core_t2.h #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
GAMMA_BIAS        131 arch/alpha/include/asm/core_t2.h #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
GAMMA_BIAS        135 arch/alpha/include/asm/core_t2.h #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
GAMMA_BIAS        136 arch/alpha/include/asm/core_t2.h #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
GAMMA_BIAS        137 arch/alpha/include/asm/core_t2.h #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
GAMMA_BIAS        138 arch/alpha/include/asm/core_t2.h #define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
GAMMA_BIAS        577 arch/alpha/kernel/sys_sable.c #undef GAMMA_BIAS
GAMMA_BIAS        608 arch/alpha/kernel/sys_sable.c #undef GAMMA_BIAS