G4X_WM_LEVEL_HPLL 1064 drivers/gpu/drm/i915/intel_pm.c 	dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
G4X_WM_LEVEL_HPLL 1066 drivers/gpu/drm/i915/intel_pm.c 	dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
G4X_WM_LEVEL_HPLL 1103 drivers/gpu/drm/i915/intel_pm.c 	case G4X_WM_LEVEL_HPLL:
G4X_WM_LEVEL_HPLL 1274 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
G4X_WM_LEVEL_HPLL 1279 drivers/gpu/drm/i915/intel_pm.c 				      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
G4X_WM_LEVEL_HPLL 1324 drivers/gpu/drm/i915/intel_pm.c 	if (level <= G4X_WM_LEVEL_HPLL) {
G4X_WM_LEVEL_HPLL 1382 drivers/gpu/drm/i915/intel_pm.c 	level = G4X_WM_LEVEL_HPLL;
G4X_WM_LEVEL_HPLL 1414 drivers/gpu/drm/i915/intel_pm.c 	else if (level >= G4X_WM_LEVEL_HPLL &&
G4X_WM_LEVEL_HPLL 1415 drivers/gpu/drm/i915/intel_pm.c 		 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
G4X_WM_LEVEL_HPLL 1476 drivers/gpu/drm/i915/intel_pm.c 		 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
G4X_WM_LEVEL_HPLL 1478 drivers/gpu/drm/i915/intel_pm.c 		 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
G4X_WM_LEVEL_HPLL 6017 drivers/gpu/drm/i915/intel_pm.c 			max_level = G4X_WM_LEVEL_HPLL;