Fld 67 arch/arm/include/asm/hardware/sa1111.h #define SMCR_DRAC Fld(3, 2) Fld 89 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ Fld 92 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ Fld 95 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ Fld 98 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ Fld 101 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ Fld 104 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ Fld 107 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ Fld 110 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ Fld 126 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ Fld 129 arch/arm/mach-pxa/include/mach/regs-lcd.h #define LCCR3_ACB Fld (8, 8) /* AC Bias */ Fld 137 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCAR_ADD Fld (7, 0) /* function ADDress */ Fld 139 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ Fld 145 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ Fld 177 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ Fld 179 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCWC_WC Fld (4, 0) /* Write Count */ Fld 181 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ Fld 337 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ Fld 338 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ Fld 378 arch/arm/mach-sa1100/include/mach/SA-1100.h #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ Fld 474 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ Fld 476 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ Fld 477 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ Fld 497 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ Fld 565 arch/arm/mach-sa1100/include/mach/SA-1100.h #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ Fld 567 arch/arm/mach-sa1100/include/mach/SA-1100.h #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ Fld 637 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ Fld 650 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ Fld 680 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ Fld 684 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ Fld 687 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ Fld 692 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ Fld 696 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ Fld 758 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ Fld 761 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SSCR0_FRF Fld (2, 4) /* FRame Format */ Fld 771 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ Fld 800 arch/arm/mach-sa1100/include/mach/SA-1100.h #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ Fld 945 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ Fld 1054 arch/arm/mach-sa1100/include/mach/SA-1100.h #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ Fld 1059 arch/arm/mach-sa1100/include/mach/SA-1100.h #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ Fld 1380 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ Fld 1385 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ Fld 1390 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ Fld 1395 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ Fld 1398 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ Fld 1409 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ Fld 1412 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ Fld 1413 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ Fld 1415 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ Fld 1420 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ Fld 1423 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ Fld 1424 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ Fld 1426 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ Fld 1448 arch/arm/mach-sa1100/include/mach/SA-1100.h Fld (16, ((Nb) Modulo 2)*16) Fld 1454 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ Fld 1466 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ Fld 1478 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ Fld 1490 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ Fld 1516 arch/arm/mach-sa1100/include/mach/SA-1100.h Fld (15, (Nb)*16) Fld 1520 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ Fld 1525 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ Fld 1531 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ Fld 1543 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDREFR_TRASR Fld (4, 0) Fld 1544 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDREFR_DRI Fld (12, 4) Fld 1628 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ Fld 1629 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ Fld 1630 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ Fld 1631 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ Fld 1632 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ Fld 1685 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ Fld 1712 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ Fld 1715 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ Fld 1720 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ Fld 1725 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ Fld 1731 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ Fld 1734 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ Fld 1739 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ Fld 1744 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ Fld 1750 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ Fld 1762 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ Fld 1772 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ Fld 17 drivers/video/fbdev/mbx/reg_bits.h #define SYSCLKSRC_SEL Fld(2,0) Fld 23 drivers/video/fbdev/mbx/reg_bits.h #define PIXCLKSRC_SEL Fld(2,0) Fld 32 drivers/video/fbdev/mbx/reg_bits.h #define CORE_PLL_M Fld(6,7) Fld 34 drivers/video/fbdev/mbx/reg_bits.h #define CORE_PLL_N Fld(3,4) Fld 36 drivers/video/fbdev/mbx/reg_bits.h #define CORE_PLL_P Fld(3,1) Fld 41 drivers/video/fbdev/mbx/reg_bits.h #define DISP_PLL_M Fld(6,7) Fld 43 drivers/video/fbdev/mbx/reg_bits.h #define DISP_PLL_N Fld(3,4) Fld 45 drivers/video/fbdev/mbx/reg_bits.h #define DISP_PLL_P Fld(3,1) Fld 65 drivers/video/fbdev/mbx/reg_bits.h #define MBXCLK_DIV Fld(2,2) Fld 70 drivers/video/fbdev/mbx/reg_bits.h #define MBXCLK_EN Fld(2,0) Fld 76 drivers/video/fbdev/mbx/reg_bits.h #define M24CLK_DIV Fld(2,1) Fld 87 drivers/video/fbdev/mbx/reg_bits.h #define PIXCLKDIV_PD Fld(9,0) Fld 91 drivers/video/fbdev/mbx/reg_bits.h #define LCDCFG_IN_FMT Fld(3,28) Fld 112 drivers/video/fbdev/mbx/reg_bits.h #define ODFBPWR_MODE Fld(2,0) Fld 135 drivers/video/fbdev/mbx/reg_bits.h #define LMPWR_MC_PWR_CNT Fld(2,0) Fld 141 drivers/video/fbdev/mbx/reg_bits.h #define LMPWRSTAT_MC_PWR_CNT Fld(2,0) Fld 147 drivers/video/fbdev/mbx/reg_bits.h #define LMTYPE_CASLAT Fld(3,10) Fld 151 drivers/video/fbdev/mbx/reg_bits.h #define LMTYPE_BKSZ Fld(2,8) Fld 154 drivers/video/fbdev/mbx/reg_bits.h #define LMTYPE_ROWSZ Fld(4,4) Fld 158 drivers/video/fbdev/mbx/reg_bits.h #define LMTYPE_COLSZ Fld(4,0) Fld 167 drivers/video/fbdev/mbx/reg_bits.h #define LMTIM_TRAS Fld(4,16) Fld 169 drivers/video/fbdev/mbx/reg_bits.h #define LMTIM_TRP Fld(4,12) Fld 171 drivers/video/fbdev/mbx/reg_bits.h #define LMTIM_TRCD Fld(4,8) Fld 173 drivers/video/fbdev/mbx/reg_bits.h #define LMTIM_TRC Fld(4,4) Fld 175 drivers/video/fbdev/mbx/reg_bits.h #define LMTIM_TDPL Fld(4,0) Fld 179 drivers/video/fbdev/mbx/reg_bits.h #define LMREFRESH_TREF Fld(2,0) Fld 184 drivers/video/fbdev/mbx/reg_bits.h #define GSCTRL_GPIXFMT Fld(4,27) Fld 193 drivers/video/fbdev/mbx/reg_bits.h #define GSCTRL_GSWIDTH Fld(11,11) Fld 197 drivers/video/fbdev/mbx/reg_bits.h #define GSCTRL_GSHEIGHT Fld(11,0) Fld 202 drivers/video/fbdev/mbx/reg_bits.h #define GBBASE_GLALPHA Fld(8,24) Fld 205 drivers/video/fbdev/mbx/reg_bits.h #define GBBASE_COLKEY Fld(24,0) Fld 213 drivers/video/fbdev/mbx/reg_bits.h #define GDRCTRL_COLKEYM Fld(24,0) Fld 220 drivers/video/fbdev/mbx/reg_bits.h #define GSCADR_BLEND_M Fld(2,27) Fld 225 drivers/video/fbdev/mbx/reg_bits.h #define GSCADR_BLEND_POS Fld(2,24) Fld 229 drivers/video/fbdev/mbx/reg_bits.h #define GSCADR_GBASE_ADR Fld(23,0) Fld 233 drivers/video/fbdev/mbx/reg_bits.h #define GSADR_SRCSTRIDE Fld(10,22) Fld 235 drivers/video/fbdev/mbx/reg_bits.h #define GSADR_XSTART Fld(11,11) Fld 237 drivers/video/fbdev/mbx/reg_bits.h #define GSADR_YSTART Fld(11,0) Fld 241 drivers/video/fbdev/mbx/reg_bits.h #define GPLUT_LUTADR Fld(8,24) Fld 243 drivers/video/fbdev/mbx/reg_bits.h #define GPLUT_LUTDATA Fld(24,0) Fld 247 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VPIXFMT Fld(4,27) Fld 256 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VSWIDTH Fld(11,11) Fld 259 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VSHEIGHT Fld(11,0) Fld 264 drivers/video/fbdev/mbx/reg_bits.h #define VBBASE_GLALPHA Fld(8,24) Fld 267 drivers/video/fbdev/mbx/reg_bits.h #define VBBASE_COLKEY Fld(24,0) Fld 271 drivers/video/fbdev/mbx/reg_bits.h #define VCMSK_COLKEY_M Fld(24,0) Fld 278 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_BLEND_M Fld(2,27) Fld 283 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_BLEND_POS Fld(2,24) Fld 287 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_VBASE_ADR Fld(23,0) Fld 292 drivers/video/fbdev/mbx/reg_bits.h #define VUBASE_UBASE_ADR Fld(24,0) Fld 296 drivers/video/fbdev/mbx/reg_bits.h #define VVBASE_VBASE_ADR Fld(24,0) Fld 300 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_SRCSTRIDE Fld(10,22) Fld 302 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_XSTART Fld(11,11) Fld 304 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_YSTART Fld(11,0) Fld 308 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VPIXFMT Fld(4,27) Fld 317 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VSWIDTH Fld(11,11) Fld 320 drivers/video/fbdev/mbx/reg_bits.h #define VSCTRL_VSHEIGHT Fld(11,0) Fld 325 drivers/video/fbdev/mbx/reg_bits.h #define VBBASE_GLALPHA Fld(8,24) Fld 328 drivers/video/fbdev/mbx/reg_bits.h #define VBBASE_COLKEY Fld(24,0) Fld 332 drivers/video/fbdev/mbx/reg_bits.h #define VCMSK_COLKEY_M Fld(24,0) Fld 339 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_BLEND_M Fld(2,27) Fld 344 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_BLEND_POS Fld(2,24) Fld 348 drivers/video/fbdev/mbx/reg_bits.h #define VSCADR_VBASE_ADR Fld(23,0) Fld 353 drivers/video/fbdev/mbx/reg_bits.h #define VUBASE_UBASE_ADR Fld(24,0) Fld 357 drivers/video/fbdev/mbx/reg_bits.h #define VVBASE_VBASE_ADR Fld(24,0) Fld 361 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_SRCSTRIDE Fld(10,22) Fld 363 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_XSTART Fld(11,11) Fld 365 drivers/video/fbdev/mbx/reg_bits.h #define VSADR_YSTART Fld(11,0) Fld 372 drivers/video/fbdev/mbx/reg_bits.h #define HCCTRL_BLEND_M Fld(2,26) Fld 377 drivers/video/fbdev/mbx/reg_bits.h #define HCCTRL_CPIXFMT Fld(3,23) Fld 381 drivers/video/fbdev/mbx/reg_bits.h #define HCCTRL_CBASE_ADR Fld(23,0) Fld 385 drivers/video/fbdev/mbx/reg_bits.h #define HCSIZE_BLEND_POS Fld(2,29) Fld 389 drivers/video/fbdev/mbx/reg_bits.h #define HCSIZE_CWIDTH Fld(3,16) Fld 391 drivers/video/fbdev/mbx/reg_bits.h #define HCSIZE_CHEIGHT Fld(3,0) Fld 396 drivers/video/fbdev/mbx/reg_bits.h #define HCPOS_CURBLINK Fld(6,24) Fld 398 drivers/video/fbdev/mbx/reg_bits.h #define HCPOS_XSTART Fld(12,12) Fld 400 drivers/video/fbdev/mbx/reg_bits.h #define HCPOS_YSTART Fld(12,0) Fld 404 drivers/video/fbdev/mbx/reg_bits.h #define HCBADR_GLALPHA Fld(8,24) Fld 406 drivers/video/fbdev/mbx/reg_bits.h #define HCBADR_COLKEY Fld(24,0) Fld 410 drivers/video/fbdev/mbx/reg_bits.h #define HCCKMSK_COLKEY_M Fld(24,0) Fld 420 drivers/video/fbdev/mbx/reg_bits.h #define DSCTRL_UPDWAIT Fld(4,16) Fld 434 drivers/video/fbdev/mbx/reg_bits.h #define DHT01_HBPS Fld(12,16) Fld 436 drivers/video/fbdev/mbx/reg_bits.h #define DHT01_HT Fld(12,0) Fld 440 drivers/video/fbdev/mbx/reg_bits.h #define DHT02_HAS Fld(12,16) Fld 442 drivers/video/fbdev/mbx/reg_bits.h #define DHT02_HLBS Fld(12,0) Fld 446 drivers/video/fbdev/mbx/reg_bits.h #define DHT03_HFPS Fld(12,16) Fld 448 drivers/video/fbdev/mbx/reg_bits.h #define DHT03_HRBS Fld(12,0) Fld 452 drivers/video/fbdev/mbx/reg_bits.h #define DVT01_VBPS Fld(12,16) Fld 454 drivers/video/fbdev/mbx/reg_bits.h #define DVT01_VT Fld(12,0) Fld 458 drivers/video/fbdev/mbx/reg_bits.h #define DVT02_VAS Fld(12,16) Fld 460 drivers/video/fbdev/mbx/reg_bits.h #define DVT02_VTBS Fld(12,0) Fld 464 drivers/video/fbdev/mbx/reg_bits.h #define DVT03_VFPS Fld(12,16) Fld 466 drivers/video/fbdev/mbx/reg_bits.h #define DVT03_VBBS Fld(12,0) Fld 470 drivers/video/fbdev/mbx/reg_bits.h #define DVECTRL_VEVENT Fld(12,16) Fld 472 drivers/video/fbdev/mbx/reg_bits.h #define DVECTRL_VFETCH Fld(12,0) Fld 476 drivers/video/fbdev/mbx/reg_bits.h #define DHDET_HDES Fld(12,16) Fld 478 drivers/video/fbdev/mbx/reg_bits.h #define DHDET_HDEF Fld(12,0) Fld 482 drivers/video/fbdev/mbx/reg_bits.h #define DVDET_VDES Fld(12,16) Fld 484 drivers/video/fbdev/mbx/reg_bits.h #define DVDET_VDEF Fld(12,0) Fld 490 drivers/video/fbdev/mbx/reg_bits.h #define DODMSK_MASK_B Fld(8,16) Fld 492 drivers/video/fbdev/mbx/reg_bits.h #define DODMSK_MASK_G Fld(8,8) Fld 494 drivers/video/fbdev/mbx/reg_bits.h #define DODMSK_MASK_R Fld(8,0) Fld 498 drivers/video/fbdev/mbx/reg_bits.h #define DBCOL_BORDCOL Fld(24,0) Fld 502 drivers/video/fbdev/mbx/reg_bits.h #define DVLNUM_VLINE Fld(12,0) Fld 506 drivers/video/fbdev/mbx/reg_bits.h #define DMCTRL_MEM_REF Fld(2,30) Fld 511 drivers/video/fbdev/mbx/reg_bits.h #define DMCTRL_UV_THRHLD Fld(6,24) Fld 513 drivers/video/fbdev/mbx/reg_bits.h #define DMCTRL_V_THRHLD Fld(7,16) Fld 515 drivers/video/fbdev/mbx/reg_bits.h #define DMCTRL_D_THRHLD Fld(7,8) Fld 517 drivers/video/fbdev/mbx/reg_bits.h #define DMCTRL_BURSTLEN Fld(6,0) Fld 574 drivers/video/fbdev/mbx/reg_bits.h #define DLLCTRL_RLD_ADRLN Fld(8,24) Fld 578 drivers/video/fbdev/mbx/reg_bits.h #define CLIPCTRL_HSKIP Fld(11,16) Fld 580 drivers/video/fbdev/mbx/reg_bits.h #define CLIPCTRL_VSKIP Fld(11,0) Fld 588 drivers/video/fbdev/mbx/reg_bits.h #define SPOCTRL_VORDER Fld(2,16) Fld 592 drivers/video/fbdev/mbx/reg_bits.h #define SPOCTRL_VPITCH Fld(16,0) Fld 596 drivers/video/fbdev/mbx/reg_bits.h #define SVCTRL_INITIAL1 Fld(16,16) Fld 598 drivers/video/fbdev/mbx/reg_bits.h #define SVCTRL_INITIAL2 Fld(16,0) Fld 602 drivers/video/fbdev/mbx/reg_bits.h #define SHCTRL_HINITIAL Fld(16,16) Fld 605 drivers/video/fbdev/mbx/reg_bits.h #define SHCTRL_HPITCH Fld(15,0) Fld 609 drivers/video/fbdev/mbx/reg_bits.h #define SSSIZE_SC_WIDTH Fld(11,16) Fld 611 drivers/video/fbdev/mbx/reg_bits.h #define SSSIZE_SC_HEIGHT Fld(11,0)