F_MODE_MASK       659 drivers/gpu/drm/i915/gvt/gvt.h 	return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
F_MODE_MASK      1907 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
F_MODE_MASK      1911 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      1913 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      1920 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1921 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      1923 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1924 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1925 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1927 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1928 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1929 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1931 drivers/gpu/drm/i915/gvt/handlers.c 		 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1932 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1934 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      1936 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      1945 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1946 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      1947 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2657 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2768 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
F_MODE_MASK      2792 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2812 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      2814 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      2843 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2844 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2845 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      2846 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      3049 drivers/gpu/drm/i915/gvt/handlers.c 		 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
F_MODE_MASK      3050 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      3098 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      3101 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
F_MODE_MASK      3103 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,