F_CMD_ACCESS 620 drivers/gpu/drm/i915/gvt/gvt.h return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; F_CMD_ACCESS 1830 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) F_CMD_ACCESS 1854 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) F_CMD_ACCESS 1864 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, F_CMD_ACCESS 1872 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1882 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1886 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1899 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1900 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1901 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1902 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); F_CMD_ACCESS 1907 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, F_CMD_ACCESS 1911 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 1913 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 1915 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, F_CMD_ACCESS 1917 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, F_CMD_ACCESS 1920 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1921 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 1923 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1924 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1925 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1927 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1928 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1929 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1931 drivers/gpu/drm/i915/gvt/handlers.c F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1932 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1933 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1934 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 1936 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 1938 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1939 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1940 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1941 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1942 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1943 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1944 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1945 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1946 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 1947 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2489 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2490 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2568 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2622 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2623 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2624 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2625 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2626 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2628 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); F_CMD_ACCESS 2631 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2632 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2633 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2635 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2636 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2637 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2639 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2640 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2641 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2642 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2643 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2644 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2645 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2646 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2647 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2648 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2649 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); F_CMD_ACCESS 2655 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2657 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2659 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2660 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2661 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2662 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2663 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2664 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2665 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2666 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2667 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2741 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, F_CMD_ACCESS 2755 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, F_CMD_ACCESS 2760 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2792 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2812 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 2814 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 2816 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2818 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2819 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2820 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2821 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2822 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2825 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, F_CMD_ACCESS 2831 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2834 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2843 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2844 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2845 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2846 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2848 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2850 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2851 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2852 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2853 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2854 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2855 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2856 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2857 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2858 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2859 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 2890 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3035 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3040 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, F_CMD_ACCESS 3042 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, F_CMD_ACCESS 3049 drivers/gpu/drm/i915/gvt/handlers.c F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3050 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 3054 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3055 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3056 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3057 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3058 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3059 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS, F_CMD_ACCESS 3068 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3098 drivers/gpu/drm/i915/gvt/handlers.c MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 3101 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 3103 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, F_CMD_ACCESS 3280 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); F_CMD_ACCESS 3282 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);