ALCHEMY_GPIO2_BASE   42 arch/mips/alchemy/common/gpiolib.c 	return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
ALCHEMY_GPIO2_BASE   47 arch/mips/alchemy/common/gpiolib.c 	alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
ALCHEMY_GPIO2_BASE   52 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
ALCHEMY_GPIO2_BASE   58 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
ALCHEMY_GPIO2_BASE   64 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
ALCHEMY_GPIO2_BASE  114 arch/mips/alchemy/common/gpiolib.c 		.base			= ALCHEMY_GPIO2_BASE,
ALCHEMY_GPIO2_BASE   23 arch/mips/include/asm/mach-au1x00/gpio-au1000.h #define ALCHEMY_GPIO2_MAX	(ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
ALCHEMY_GPIO2_BASE   78 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE   97 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
ALCHEMY_GPIO2_BASE   99 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
ALCHEMY_GPIO2_BASE  101 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
ALCHEMY_GPIO2_BASE  103 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + 8;
ALCHEMY_GPIO2_BASE  116 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE  130 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + 8;
ALCHEMY_GPIO2_BASE  151 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE  170 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
ALCHEMY_GPIO2_BASE  174 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
ALCHEMY_GPIO2_BASE  187 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE  205 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
ALCHEMY_GPIO2_BASE  207 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + 3;
ALCHEMY_GPIO2_BASE  209 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
ALCHEMY_GPIO2_BASE  287 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
ALCHEMY_GPIO2_BASE  302 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
ALCHEMY_GPIO2_BASE  311 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 				(1 << (gpio - ALCHEMY_GPIO2_BASE));
ALCHEMY_GPIO2_BASE  335 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
ALCHEMY_GPIO2_BASE  397 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio2 -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE  421 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio2 -= ALCHEMY_GPIO2_BASE;
ALCHEMY_GPIO2_BASE  469 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return (gpio >= ALCHEMY_GPIO2_BASE) ?
ALCHEMY_GPIO2_BASE  476 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return (gpio >= ALCHEMY_GPIO2_BASE) ?
ALCHEMY_GPIO2_BASE  483 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return (gpio >= ALCHEMY_GPIO2_BASE) ?
ALCHEMY_GPIO2_BASE  490 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	if (gpio >= ALCHEMY_GPIO2_BASE)
ALCHEMY_GPIO2_BASE  498 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return (gpio >= ALCHEMY_GPIO2_BASE) ?
ALCHEMY_GPIO2_BASE  510 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return (gpio >= ALCHEMY_GPIO2_BASE) ?