ALCHEMY_GPIO1_BASE   70 arch/mips/alchemy/common/gpiolib.c 	return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE   76 arch/mips/alchemy/common/gpiolib.c 	alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
ALCHEMY_GPIO1_BASE   81 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE   87 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
ALCHEMY_GPIO1_BASE   93 arch/mips/alchemy/common/gpiolib.c 	return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  104 arch/mips/alchemy/common/gpiolib.c 		.base			= ALCHEMY_GPIO1_BASE,
ALCHEMY_GPIO1_BASE   22 arch/mips/include/asm/mach-au1x00/gpio-au1000.h #define ALCHEMY_GPIO1_MAX	(ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
ALCHEMY_GPIO1_BASE   47 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE   58 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
ALCHEMY_GPIO1_BASE   65 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO1_BASE;
ALCHEMY_GPIO1_BASE   95 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
ALCHEMY_GPIO1_BASE  111 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  128 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
ALCHEMY_GPIO1_BASE  138 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	gpio -= ALCHEMY_GPIO1_BASE;
ALCHEMY_GPIO1_BASE  167 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
ALCHEMY_GPIO1_BASE  172 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
ALCHEMY_GPIO1_BASE  182 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  203 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 		return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
ALCHEMY_GPIO1_BASE  220 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  227 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  233 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
ALCHEMY_GPIO1_BASE  249 arch/mips/include/asm/mach-au1x00/gpio-au1000.h 	return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));