FW_BLC_SELF_EN    469 drivers/gpu/drm/gma500/cdv_intel_display.c 	if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
FW_BLC_SELF_EN    472 drivers/gpu/drm/gma500/cdv_intel_display.c 		REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
FW_BLC_SELF_EN    532 drivers/gpu/drm/gma500/cdv_intel_display.c 		REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
FW_BLC_SELF_EN   1424 drivers/gpu/drm/i915/i915_debugfs.c 		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
FW_BLC_SELF_EN    380 drivers/gpu/drm/i915/intel_pm.c 		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
FW_BLC_SELF_EN    381 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
FW_BLC_SELF_EN    393 drivers/gpu/drm/i915/intel_pm.c 		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
FW_BLC_SELF_EN    394 drivers/gpu/drm/i915/intel_pm.c 		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
FW_BLC_SELF_EN    395 drivers/gpu/drm/i915/intel_pm.c 			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
FW_BLC_SELF_EN   5993 drivers/gpu/drm/i915/intel_pm.c 	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;