FW_BLC_SELF 469 drivers/gpu/drm/gma500/cdv_intel_display.c if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { FW_BLC_SELF 472 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); FW_BLC_SELF 473 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(FW_BLC_SELF); FW_BLC_SELF 532 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); FW_BLC_SELF 533 drivers/gpu/drm/gma500/cdv_intel_display.c REG_READ(FW_BLC_SELF); FW_BLC_SELF 1424 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; FW_BLC_SELF 380 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; FW_BLC_SELF 381 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); FW_BLC_SELF 382 drivers/gpu/drm/i915/intel_pm.c POSTING_READ(FW_BLC_SELF); FW_BLC_SELF 393 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; FW_BLC_SELF 396 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FW_BLC_SELF, val); FW_BLC_SELF 397 drivers/gpu/drm/i915/intel_pm.c POSTING_READ(FW_BLC_SELF); FW_BLC_SELF 2401 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FW_BLC_SELF, FW_BLC_SELF 2404 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FW_BLC_SELF, srwm & 0x3f); FW_BLC_SELF 5993 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;