FTM_SC_PS_MASK     54 drivers/clocksource/timer-fsl-ftm.c 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
FTM_SC_PS_MASK     65 drivers/clocksource/timer-fsl-ftm.c 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
FTM_SC_PS_MASK    126 drivers/counter/ftm-quaddec.c 	*cnt_mode = FIELD_GET(FTM_SC_PS_MASK, scflags);
FTM_SC_PS_MASK    140 drivers/counter/ftm-quaddec.c 	FTM_FIELD_UPDATE(ftm, FTM_SC, FTM_SC_PS_MASK, cnt_mode);
FTM_SC_PS_MASK    276 drivers/pwm/pwm-fsl-ftm.c 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
FTM_SC_PS_MASK     34 drivers/rtc/rtc-fsl-ftm-alarm.c #define MAX_FREQ_DIV		(1 << FTM_SC_PS_MASK)
FTM_SC_PS_MASK     68 drivers/rtc/rtc-fsl-ftm-alarm.c 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
FTM_SC_PS_MASK     69 drivers/rtc/rtc-fsl-ftm-alarm.c 	val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
FTM_SC_PS_MASK     79 drivers/rtc/rtc-fsl-ftm-alarm.c 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);