A0 82 arch/m68k/fpsp040/fpsp.h .set USER_DA,LV+0 | save space for D0-D1,A0-A1 A0 85 arch/m68k/fpsp040/fpsp.h .set USER_A0,LV+8 | saved user A0 A0 323 arch/mips/kvm/entry.c UASM_i_LW(&p, A0, offsetof(struct kvm, arch.gpa_mm.pgd), S0); A0 328 arch/mips/kvm/entry.c UASM_i_MTC0(&p, A0, C0_PWBASE); A0 413 arch/mips/kvm/entry.c UASM_i_LW(&p, A0, (int)offsetof(struct mm_struct, pgd) - A0 724 arch/mips/kvm/entry.c UASM_i_LW(&p, A0, A0 730 arch/mips/kvm/entry.c UASM_i_MTC0(&p, A0, C0_PWBASE); A0 795 arch/mips/kvm/entry.c uasm_i_move(&p, A0, S0); A0 236 arch/mips/mm/page.c uasm_i_sd(buf, ZERO, off, A0); A0 238 arch/mips/mm/page.c uasm_i_sw(buf, ZERO, off, A0); A0 249 arch/mips/mm/page.c A0); A0 252 arch/mips/mm/page.c uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); A0 264 arch/mips/mm/page.c uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); A0 302 arch/mips/mm/page.c pg_addiu(&buf, A2, A0, off); A0 304 arch/mips/mm/page.c uasm_i_ori(&buf, A2, A0, off); A0 321 arch/mips/mm/page.c pg_addiu(&buf, A0, A0, 2 * off); A0 326 arch/mips/mm/page.c uasm_il_bne(&buf, &r, A0, A2, label_clear_pref); A0 332 arch/mips/mm/page.c pg_addiu(&buf, A2, A0, pref_bias_clear_store); A0 339 arch/mips/mm/page.c pg_addiu(&buf, A0, A0, 2 * off); A0 343 arch/mips/mm/page.c uasm_il_bne(&buf, &r, A0, A2, A0 379 arch/mips/mm/page.c uasm_i_sd(buf, reg, off, A0); A0 381 arch/mips/mm/page.c uasm_i_sw(buf, reg, off, A0); A0 401 arch/mips/mm/page.c A0); A0 404 arch/mips/mm/page.c uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); A0 416 arch/mips/mm/page.c uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); A0 453 arch/mips/mm/page.c pg_addiu(&buf, A2, A0, off); A0 455 arch/mips/mm/page.c uasm_i_ori(&buf, A2, A0, off); A0 493 arch/mips/mm/page.c pg_addiu(&buf, A0, A0, 2 * off); A0 512 arch/mips/mm/page.c uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both); A0 518 arch/mips/mm/page.c pg_addiu(&buf, A2, A0, A0 538 arch/mips/mm/page.c pg_addiu(&buf, A0, A0, 2 * off); A0 553 arch/mips/mm/page.c uasm_il_bne(&buf, &r, A2, A0, A0 561 arch/mips/mm/page.c pg_addiu(&buf, A2, A0, pref_bias_copy_store); A0 576 arch/mips/mm/page.c pg_addiu(&buf, A0, A0, 2 * off); A0 587 arch/mips/mm/page.c uasm_il_bne(&buf, &r, A2, A0, A0 2178 drivers/gpu/drm/amd/display/dc/core/dc_resource.c hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; A0 64 drivers/gpu/drm/amd/display/include/set_mode_types.h uint8_t A0:1; A0 1770 drivers/gpu/drm/amd/display/modules/color/color_gamma.c regamma->coeff.A0[i], 10000000); A0 62 drivers/gpu/drm/amd/display/modules/color/color_gamma.h int A0[3]; A0 669 drivers/pinctrl/sh-pfc/pfc-r8a77470.c PINMUX_IPSR_GPSR(IP4_7_4, A0), A0 572 drivers/pinctrl/sh-pfc/pfc-r8a7778.c PINMUX_IPSR_GPSR(IP0_14_12, A0), A0 616 drivers/pinctrl/sh-pfc/pfc-r8a7779.c PINMUX_IPSR_GPSR(IP0_7_6, A0), A0 900 drivers/pinctrl/sh-pfc/pfc-r8a7790.c PINMUX_IPSR_GPSR(IP1_27_26, A0), A0 827 drivers/pinctrl/sh-pfc/pfc-r8a7791.c PINMUX_IPSR_GPSR(IP0_18_16, A0), A0 363 drivers/pinctrl/sh-pfc/pfc-r8a7792.c PINMUX_SINGLE(A0), A0 782 drivers/pinctrl/sh-pfc/pfc-r8a7794.c PINMUX_IPSR_GPSR(IP1_23_22, A0), A0 127 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c #define GPSR1_0 F_(A0, IP1_31_28) A0 269 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 729 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c PINMUX_IPSR_GPSR(IP1_31_28, A0), A0 128 drivers/pinctrl/sh-pfc/pfc-r8a7795.c #define GPSR1_0 F_(A0, IP1_31_28) A0 270 drivers/pinctrl/sh-pfc/pfc-r8a7795.c #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 736 drivers/pinctrl/sh-pfc/pfc-r8a7795.c PINMUX_IPSR_GPSR(IP1_31_28, A0), A0 132 drivers/pinctrl/sh-pfc/pfc-r8a7796.c #define GPSR1_0 F_(A0, IP1_31_28) A0 274 drivers/pinctrl/sh-pfc/pfc-r8a7796.c #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 739 drivers/pinctrl/sh-pfc/pfc-r8a7796.c PINMUX_IPSR_GPSR(IP1_31_28, A0), A0 133 drivers/pinctrl/sh-pfc/pfc-r8a77965.c #define GPSR1_0 F_(A0, IP1_31_28) A0 275 drivers/pinctrl/sh-pfc/pfc-r8a77965.c #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 742 drivers/pinctrl/sh-pfc/pfc-r8a77965.c PINMUX_IPSR_GPSR(IP1_31_28, A0), A0 153 drivers/pinctrl/sh-pfc/pfc-r8a77970.c #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 386 drivers/pinctrl/sh-pfc/pfc-r8a77970.c PINMUX_IPSR_GPSR(IP0_3_0, A0), A0 186 drivers/pinctrl/sh-pfc/pfc-r8a77980.c #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 455 drivers/pinctrl/sh-pfc/pfc-r8a77980.c PINMUX_IPSR_GPSR(IP0_3_0, A0), A0 110 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define GPSR1_0 F_(A0, IP2_31_28) A0 237 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) A0 653 drivers/pinctrl/sh-pfc/pfc-r8a77990.c PINMUX_IPSR_GPSR(IP2_31_28, A0), A0 954 drivers/pinctrl/sh-pfc/pfc-sh7203.c GPIO_FN(A0), A0 1287 drivers/pinctrl/sh-pfc/pfc-sh7264.c GPIO_FN(A0), A0 1725 drivers/pinctrl/sh-pfc/pfc-sh7269.c GPIO_FN(A0), A0 764 drivers/pinctrl/sh-pfc/pfc-sh7720.c GPIO_FN(A0), A0 591 drivers/pinctrl/sh-pfc/pfc-sh7734.c PINMUX_IPSR_GPSR(IP0_1_0, A0), A0 1365 drivers/pinctrl/sh-pfc/pfc-sh7734.c GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A), A0 1650 drivers/pinctrl/sh-pfc/pfc-sh7757.c GPIO_FN(A0), A0 22 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[0] = REG(A0); A0 58 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[2] = REG(A0); A0 31 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[10] = REG(A0);