FRS               394 arch/powerpc/xmon/ppc-opc.c #define FRT FRS
FRS               399 arch/powerpc/xmon/ppc-opc.c #define FRSp FRS + 1
FRS              3099 arch/powerpc/xmon/ppc-opc.c {"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	0,		{FRS,RA,RB,PSWM,PSQM}},
FRS              3174 arch/powerpc/xmon/ppc-opc.c {"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	0,		{FRS,RA,RB,PSWM,PSQM}},
FRS              4793 arch/powerpc/xmon/ppc-opc.c {"mffprd",	X(31,51),	XX1RB_MASK|1, PPCVSX2,	0,		{RA, FRS}},
FRS              4873 arch/powerpc/xmon/ppc-opc.c {"mffprwz",	X(31,115),	XX1RB_MASK|1, PPCVSX2,	0,		{RA, FRS}},
FRS              5910 arch/powerpc/xmon/ppc-opc.c {"stfsx",	X(31,663),	X_MASK,	     COM,	PPCEFS,		{FRS, RA0, RB}},
FRS              5931 arch/powerpc/xmon/ppc-opc.c {"stfsux",	X(31,695),	X_MASK,	     COM,	PPCEFS,		{FRS, RAS, RB}},
FRS              5964 arch/powerpc/xmon/ppc-opc.c {"stfdx",	X(31,727),	X_MASK,	     COM,	PPCEFS,		{FRS, RA0, RB}},
FRS              5973 arch/powerpc/xmon/ppc-opc.c {"stfdepx",	X(31,735),	X_MASK,	  E500MC|PPCA2, 0,		{FRS, RA0, RB}},
FRS              6010 arch/powerpc/xmon/ppc-opc.c {"stfdux",	X(31,759),	X_MASK,	     COM,	PPCEFS,		{FRS, RAS, RB}},
FRS              6161 arch/powerpc/xmon/ppc-opc.c {"stfqx",	X(31,919),	X_MASK,	     POWER2,	0,		{FRS, RA0, RB}},
FRS              6174 arch/powerpc/xmon/ppc-opc.c {"stfddx",	X(31,931),	X_MASK,	     E500MC,	0,		{FRS, RA, RB}},
FRS              6203 arch/powerpc/xmon/ppc-opc.c {"stfqux",	X(31,951),	X_MASK,	     POWER2,	0,		{FRS, RA, RB}},
FRS              6236 arch/powerpc/xmon/ppc-opc.c {"stfiwx",	X(31,983),	X_MASK,	     PPC,	PPCEFS,		{FRS, RA0, RB}},
FRS              6330 arch/powerpc/xmon/ppc-opc.c {"stfs",	OP(52),		OP_MASK,     COM,	PPCEFS|PPCVLE,	{FRS, D, RA0}},
FRS              6332 arch/powerpc/xmon/ppc-opc.c {"stfsu",	OP(53),		OP_MASK,     COM,	PPCEFS|PPCVLE,	{FRS, D, RAS}},
FRS              6334 arch/powerpc/xmon/ppc-opc.c {"stfd",	OP(54),		OP_MASK,     COM,	PPCEFS|PPCVLE,	{FRS, D, RA0}},
FRS              6336 arch/powerpc/xmon/ppc-opc.c {"stfdu",	OP(55),		OP_MASK,     COM,	PPCEFS|PPCVLE,	{FRS, D, RAS}},
FRS              6662 arch/powerpc/xmon/ppc-opc.c {"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCVLE,		{FRS,PSD,RA,PSW,PSQ}},
FRS              6663 arch/powerpc/xmon/ppc-opc.c {"stfq",	OP(60),		OP_MASK,     POWER2,	PPCVLE,		{FRS, D, RA}},
FRS              6670 arch/powerpc/xmon/ppc-opc.c {"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCVLE,		{FRS,PSD,RA,PSW,PSQ}},
FRS              6671 arch/powerpc/xmon/ppc-opc.c {"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCVLE,		{FRS, D, RA}},