FRQCR 55 arch/sh/boards/mach-hp6xx/pm.c frqcr = __raw_readw(FRQCR); FRQCR 57 arch/sh/boards/mach-hp6xx/pm.c __raw_writew(frqcr, FRQCR); FRQCR 85 arch/sh/boards/mach-hp6xx/pm.c frqcr = __raw_readw(FRQCR); FRQCR 87 arch/sh/boards/mach-hp6xx/pm.c __raw_writew(frqcr, FRQCR); FRQCR 90 arch/sh/boards/mach-hp6xx/pm.c __raw_writew(frqcr, FRQCR); FRQCR 44 arch/sh/kernel/cpu/sh2a/clock-sh7264.c return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1]; FRQCR 82 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT FRQCR 84 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT), FRQCR 110 arch/sh/kernel/cpu/sh2a/clock-sh7269.c [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT FRQCR 112 arch/sh/kernel/cpu/sh2a/clock-sh7269.c [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT FRQCR 28 arch/sh/kernel/cpu/sh3/clock-sh3.c int frqcr = __raw_readw(FRQCR); FRQCR 40 arch/sh/kernel/cpu/sh3/clock-sh3.c int frqcr = __raw_readw(FRQCR); FRQCR 52 arch/sh/kernel/cpu/sh3/clock-sh3.c int frqcr = __raw_readw(FRQCR); FRQCR 64 arch/sh/kernel/cpu/sh3/clock-sh3.c int frqcr = __raw_readw(FRQCR); FRQCR 32 arch/sh/kernel/cpu/sh3/clock-sh7705.c clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; FRQCR 41 arch/sh/kernel/cpu/sh3/clock-sh7705.c int idx = __raw_readw(FRQCR) & 0x0003; FRQCR 51 arch/sh/kernel/cpu/sh3/clock-sh7705.c int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; FRQCR 61 arch/sh/kernel/cpu/sh3/clock-sh7705.c int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; FRQCR 24 arch/sh/kernel/cpu/sh3/clock-sh7706.c int frqcr = __raw_readw(FRQCR); FRQCR 36 arch/sh/kernel/cpu/sh3/clock-sh7706.c int frqcr = __raw_readw(FRQCR); FRQCR 48 arch/sh/kernel/cpu/sh3/clock-sh7706.c int frqcr = __raw_readw(FRQCR); FRQCR 60 arch/sh/kernel/cpu/sh3/clock-sh7706.c int frqcr = __raw_readw(FRQCR); FRQCR 24 arch/sh/kernel/cpu/sh3/clock-sh7709.c int frqcr = __raw_readw(FRQCR); FRQCR 36 arch/sh/kernel/cpu/sh3/clock-sh7709.c int frqcr = __raw_readw(FRQCR); FRQCR 48 arch/sh/kernel/cpu/sh3/clock-sh7709.c int frqcr = __raw_readw(FRQCR); FRQCR 61 arch/sh/kernel/cpu/sh3/clock-sh7709.c int frqcr = __raw_readw(FRQCR); FRQCR 26 arch/sh/kernel/cpu/sh3/clock-sh7710.c clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; FRQCR 35 arch/sh/kernel/cpu/sh3/clock-sh7710.c int idx = (__raw_readw(FRQCR) & 0x0007); FRQCR 45 arch/sh/kernel/cpu/sh3/clock-sh7710.c int idx = (__raw_readw(FRQCR) & 0x0700) >> 8; FRQCR 55 arch/sh/kernel/cpu/sh3/clock-sh7710.c int idx = (__raw_readw(FRQCR) & 0x0070) >> 4; FRQCR 23 arch/sh/kernel/cpu/sh3/clock-sh7712.c int frqcr = __raw_readw(FRQCR); FRQCR 35 arch/sh/kernel/cpu/sh3/clock-sh7712.c int frqcr = __raw_readw(FRQCR); FRQCR 47 arch/sh/kernel/cpu/sh3/clock-sh7712.c int frqcr = __raw_readw(FRQCR); FRQCR 28 arch/sh/kernel/cpu/sh4/clock-sh4.c clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; FRQCR 37 arch/sh/kernel/cpu/sh4/clock-sh4.c int idx = (__raw_readw(FRQCR) & 0x0007); FRQCR 47 arch/sh/kernel/cpu/sh4/clock-sh4.c int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; FRQCR 57 arch/sh/kernel/cpu/sh4/clock-sh4.c int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; FRQCR 67 arch/sh/kernel/cpu/sh4a/clock-sh7343.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); FRQCR 109 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 110 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 111 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 112 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 113 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 114 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), FRQCR 68 arch/sh/kernel/cpu/sh4a/clock-sh7366.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); FRQCR 112 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), FRQCR 113 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 114 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 115 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 116 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 117 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), FRQCR 71 arch/sh/kernel/cpu/sh4a/clock-sh7722.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); FRQCR 114 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), FRQCR 115 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 116 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 117 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 118 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), FRQCR 119 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), FRQCR 72 arch/sh/kernel/cpu/sh4a/clock-sh7723.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); FRQCR 115 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), FRQCR 116 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), FRQCR 117 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), FRQCR 118 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), FRQCR 119 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), FRQCR 120 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), FRQCR 63 arch/sh/kernel/cpu/sh4a/clock-sh7757.c SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) FRQCR 24 arch/sh/kernel/cpu/sh4a/clock-sh7763.c clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; FRQCR 33 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); FRQCR 43 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); FRQCR 70 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); FRQCR 21 arch/sh/kernel/cpu/sh4a/clock-sh7770.c clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; FRQCR 30 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); FRQCR 40 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = (__raw_readl(FRQCR) & 0x000f); FRQCR 50 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); FRQCR 24 arch/sh/kernel/cpu/sh4a/clock-sh7780.c clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; FRQCR 33 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = (__raw_readl(FRQCR) & 0x0003); FRQCR 43 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); FRQCR 53 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); FRQCR 76 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);