FMT_PIXEL_ENCODING 389 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c FMT_PIXEL_ENCODING, 0, FMT_PIXEL_ENCODING 394 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c FMT_PIXEL_ENCODING, 0, FMT_PIXEL_ENCODING 399 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c FMT_PIXEL_ENCODING, 1, FMT_PIXEL_ENCODING 404 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c FMT_PIXEL_ENCODING, 2, FMT_PIXEL_ENCODING 120 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ FMT_PIXEL_ENCODING 190 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ FMT_PIXEL_ENCODING 234 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h type FMT_PIXEL_ENCODING; \ FMT_PIXEL_ENCODING 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); FMT_PIXEL_ENCODING 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1); FMT_PIXEL_ENCODING 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); FMT_PIXEL_ENCODING 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ FMT_PIXEL_ENCODING 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h type FMT_PIXEL_ENCODING; \