FMT_CONTROL       190 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 				REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       194 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 				REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       200 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 			REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       388 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_UPDATE_3(FMT_CONTROL,
FMT_CONTROL       393 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       398 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       403 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_UPDATE_3(FMT_CONTROL,
FMT_CONTROL       443 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_CONTROL,
FMT_CONTROL       496 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_UPDATE(FMT_CONTROL,
FMT_CONTROL       500 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
FMT_CONTROL        46 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CONTROL, FMT, id), \
FMT_CONTROL       111 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
FMT_CONTROL       120 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
FMT_CONTROL       121 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
FMT_CONTROL       122 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
FMT_CONTROL       126 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
FMT_CONTROL       127 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
FMT_CONTROL       128 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
FMT_CONTROL       132 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
FMT_CONTROL       133 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
FMT_CONTROL       134 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
FMT_CONTROL       140 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
FMT_CONTROL       141 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
FMT_CONTROL       142 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
FMT_CONTROL       143 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
FMT_CONTROL       144 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
FMT_CONTROL       145 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
FMT_CONTROL       250 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	uint32_t FMT_CONTROL;
FMT_CONTROL        79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 			REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL        83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 			REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL        90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE_2(FMT_CONTROL,
FMT_CONTROL       168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
FMT_CONTROL       171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
FMT_CONTROL       174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
FMT_CONTROL       320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
FMT_CONTROL        38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_CONTROL, FMT, id), \
FMT_CONTROL        55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	uint32_t FMT_CONTROL; \