FMT_BIT_DEPTH_CONTROL 531 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 532 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 533 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 534 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); FMT_BIT_DEPTH_CONTROL 536 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 537 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); FMT_BIT_DEPTH_CONTROL 543 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 544 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 545 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 546 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 547 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); FMT_BIT_DEPTH_CONTROL 549 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 550 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); FMT_BIT_DEPTH_CONTROL 556 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 557 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 558 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 559 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 560 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); FMT_BIT_DEPTH_CONTROL 562 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 563 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); FMT_BIT_DEPTH_CONTROL 557 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 558 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 559 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 560 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); FMT_BIT_DEPTH_CONTROL 562 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 563 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); FMT_BIT_DEPTH_CONTROL 569 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 570 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 571 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 572 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 573 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); FMT_BIT_DEPTH_CONTROL 575 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 576 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); FMT_BIT_DEPTH_CONTROL 582 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 583 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 584 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); FMT_BIT_DEPTH_CONTROL 585 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); FMT_BIT_DEPTH_CONTROL 586 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); FMT_BIT_DEPTH_CONTROL 588 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); FMT_BIT_DEPTH_CONTROL 589 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); FMT_BIT_DEPTH_CONTROL 111 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 120 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 126 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 136 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 165 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 170 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 175 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 237 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 247 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 269 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 274 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 278 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 289 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 304 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 307 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 313 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_UPDATE(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 45 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ FMT_BIT_DEPTH_CONTROL 90 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ FMT_BIT_DEPTH_CONTROL 91 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ FMT_BIT_DEPTH_CONTROL 92 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ FMT_BIT_DEPTH_CONTROL 93 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ FMT_BIT_DEPTH_CONTROL 94 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ FMT_BIT_DEPTH_CONTROL 95 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ FMT_BIT_DEPTH_CONTROL 96 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ FMT_BIT_DEPTH_CONTROL 97 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ FMT_BIT_DEPTH_CONTROL 98 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ FMT_BIT_DEPTH_CONTROL 99 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ FMT_BIT_DEPTH_CONTROL 103 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ FMT_BIT_DEPTH_CONTROL 104 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ FMT_BIT_DEPTH_CONTROL 105 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ FMT_BIT_DEPTH_CONTROL 106 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ FMT_BIT_DEPTH_CONTROL 107 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ FMT_BIT_DEPTH_CONTROL 108 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ FMT_BIT_DEPTH_CONTROL 109 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ FMT_BIT_DEPTH_CONTROL 110 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ FMT_BIT_DEPTH_CONTROL 249 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h uint32_t FMT_BIT_DEPTH_CONTROL; FMT_BIT_DEPTH_CONTROL 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, FMT_BIT_DEPTH_CONTROL 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ FMT_BIT_DEPTH_CONTROL 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h uint32_t FMT_BIT_DEPTH_CONTROL; \ FMT_BIT_DEPTH_CONTROL 8805 drivers/gpu/drm/radeon/cik.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); FMT_BIT_DEPTH_CONTROL 1348 drivers/gpu/drm/radeon/evergreen.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); FMT_BIT_DEPTH_CONTROL 346 drivers/gpu/drm/radeon/r600.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);