FD 66 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c FD(reg_name##__##field) FD 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c FD(reg_name##__##field) FD 49 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) FD 52 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) FD 55 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) FD 58 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4) FD 61 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5) FD 64 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val) FD 67 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) FD 70 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) FD 265 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 1, FD 266 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst, FD 267 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY, FD 270 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY, FD 272 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0, FD 273 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 1); FD 289 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 0, FD 290 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), 0, FD 291 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY, FD 292 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY, FD 294 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0, FD 295 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0); FD 331 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT), trig_src_select, FD 332 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT), TRIGGER_POLARITY_SELECT_LOGIC_ZERO, FD 333 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL), rising_edge, FD 334 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL), falling_edge, FD 336 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT), 0, FD 338 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY), 0, FD 340 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR), 1); FD 561 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1, FD 562 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1, FD 563 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0, FD 564 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0, FD 565 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN), 0, FD 566 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0); FD 574 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0, FD 575 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0, FD 576 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0, FD 577 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0, FD 578 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0); FD 61 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FD(reg_name##__##field) FD 1793 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); FD 1949 drivers/net/ethernet/amd/xgbe/xgbe-dev.c if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { FD 458 drivers/net/ethernet/cadence/macb_main.c reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); FD 463 drivers/net/ethernet/cadence/macb_main.c reg |= MACB_BIT(FD); FD 50 tools/perf/lib/evsel.c FD(evsel, cpu, thread) = -1; FD 110 tools/perf/lib/evsel.c FD(evsel, cpu, thread) = fd; FD 123 tools/perf/lib/evsel.c close(FD(evsel, cpu, thread)); FD 124 tools/perf/lib/evsel.c FD(evsel, cpu, thread) = -1; FD 175 tools/perf/lib/evsel.c if (FD(evsel, cpu, thread) < 0) FD 178 tools/perf/lib/evsel.c if (readn(FD(evsel, cpu, thread), count->values, size) <= 0) FD 191 tools/perf/lib/evsel.c int fd = FD(evsel, cpu, thread), FD 40 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(FD); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break; FD 365 tools/perf/util/evlist.c int err = ioctl(FD(evsel, cpu, thread), PERF_EVENT_IOC_ENABLE, 0); FD 383 tools/perf/util/evlist.c int err = ioctl(FD(evsel, cpu, thread), PERF_EVENT_IOC_ENABLE, 0); FD 670 tools/perf/util/evlist.c fd = FD(evsel, cpu, thread); FD 1389 tools/perf/util/evsel.c if (FD(leader, cpu, thread) < 0) FD 1392 tools/perf/util/evsel.c if (readn(FD(leader, cpu, thread), data, size) <= 0) FD 1414 tools/perf/util/evsel.c if (FD(evsel, cpu, thread) < 0) FD 1420 tools/perf/util/evsel.c if (readn(FD(evsel, cpu, thread), &count, nv * sizeof(u64)) <= 0) FD 1443 tools/perf/util/evsel.c fd = FD(leader, cpu, thread); FD 1455 tools/perf/util/evsel.c FD(pos, cpu, thread) = FD(pos, cpu, thread + 1); FD 1665 tools/perf/util/evsel.c FD(evsel, cpu, thread) = fd; FD 1817 tools/perf/util/evsel.c close(FD(evsel, cpu, thread)); FD 1818 tools/perf/util/evsel.c FD(evsel, cpu, thread) = -1; FD 2526 tools/perf/util/evsel.c int fd = FD(evsel, cpu, thread);