FCRT 866 arch/powerpc/xmon/ppc-opc.c #define FSL FCRT + 1 FCRT 4697 arch/powerpc/xmon/ppc-opc.c {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4771 arch/powerpc/xmon/ppc-opc.c {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4835 arch/powerpc/xmon/ppc-opc.c {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4861 arch/powerpc/xmon/ppc-opc.c {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4899 arch/powerpc/xmon/ppc-opc.c {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4951 arch/powerpc/xmon/ppc-opc.c {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 4983 arch/powerpc/xmon/ppc-opc.c {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5023 arch/powerpc/xmon/ppc-opc.c {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5075 arch/powerpc/xmon/ppc-opc.c {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5435 arch/powerpc/xmon/ppc-opc.c {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5760 arch/powerpc/xmon/ppc-opc.c {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5813 arch/powerpc/xmon/ppc-opc.c {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5836 arch/powerpc/xmon/ppc-opc.c {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5866 arch/powerpc/xmon/ppc-opc.c {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5884 arch/powerpc/xmon/ppc-opc.c {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5924 arch/powerpc/xmon/ppc-opc.c {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5943 arch/powerpc/xmon/ppc-opc.c {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 5981 arch/powerpc/xmon/ppc-opc.c {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 6021 arch/powerpc/xmon/ppc-opc.c {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, FCRT 6138 arch/powerpc/xmon/ppc-opc.c {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},